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charset="utf-8" Signed-off-by: Aaron Lindsay --- target/arm/helper.c | 44 ++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 42 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 06e2e2c..4f8d11c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -955,6 +955,15 @@ static bool event_always_supported(CPUARMState *env) return true; } =20 +static uint64_t swinc_get_count(CPUARMState *env, uint64_t cycles) +{ + /* + * SW_INCR events are written directly to the pmevcntr's by writes to + * PMSWINC, so there is no underlying count maintained by the PMU itse= lf + */ + return 0; +} + #ifndef CONFIG_USER_ONLY static uint64_t cycles_get_count(CPUARMState *env, uint64_t cycles) { @@ -974,6 +983,10 @@ static uint64_t instructions_get_count(CPUARMState *en= v, uint64_t cycles) =20 #define SUPPORTED_EVENT_SENTINEL UINT16_MAX static const pm_event pm_events[] =3D { + { .number =3D 0x000, /* SW_INCR */ + .supported =3D event_always_supported, + .get_count =3D swinc_get_count + }, #ifndef CONFIG_USER_ONLY { .number =3D 0x008, /* INST_RETIRED */ .supported =3D instructions_supported, @@ -1273,6 +1286,29 @@ static void pmcr_write(CPUARMState *env, const ARMCP= RegInfo *ri, pmu_op_finish(env, saved_cycles); } =20 +static void pmswinc_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + unsigned int i; + for (i =3D 0; i < PMU_NUM_COUNTERS(env); i++) { + /* Increment a counter's count iff: */ + if ((value & (1 << i)) && /* counter's bit is set */ + /* counter is enabled and not filtered */ + pmu_counter_enabled(env, i) && + !pmu_counter_filtered(env, env->cp15.c14_pmevtyper[i]) && + /* counter is SW_INCR */ + (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) =3D=3D = 0x0) { + uint64_t cycles =3D 0; +#ifndef CONFIG_USER_ONLY + cycles =3D get_cycle_count(env); +#endif + pmu_sync_counter(env, i, cycles); + env->cp15.c14_pmevcntr[i]++; + pmu_sync_counter(env, i, cycles); + } + } +} + static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) { uint64_t ret; @@ -1619,9 +1655,13 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmovsr), .writefn =3D pmovsr_write, .raw_writefn =3D raw_write }, - /* Unimplemented so WI. */ { .name =3D "PMSWINC", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D = 0, .opc2 =3D 4, - .access =3D PL0_W, .accessfn =3D pmreg_access_swinc, .type =3D ARM_C= P_NOP }, + .access =3D PL0_W, .accessfn =3D pmreg_access_swinc, .type =3D ARM_C= P_NO_RAW, + .writefn =3D pmswinc_write }, + { .name =3D "PMSWINC_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 4, + .access =3D PL0_W, .accessfn =3D pmreg_access_swinc, .type =3D ARM_C= P_NO_RAW, + .writefn =3D pmswinc_write }, { .name =3D "PMSELR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 5, .access =3D PL0_RW, .type =3D ARM_CP_ALIAS, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmselr), --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.