From nobody Sat Oct 25 13:20:48 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521233727863216.68439786672172; Fri, 16 Mar 2018 13:55:27 -0700 (PDT) Received: from localhost ([::1]:59590 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewwNq-0007gy-N4 for importer@patchew.org; Fri, 16 Mar 2018 16:55:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44694) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eww1l-0006Bw-R3 for qemu-devel@nongnu.org; Fri, 16 Mar 2018 16:32:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eww1k-0003mC-Ai for qemu-devel@nongnu.org; Fri, 16 Mar 2018 16:32:37 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:56804) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eww1g-0003fs-R4; Fri, 16 Mar 2018 16:32:33 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 6976860C66; Fri, 16 Mar 2018 20:32:24 +0000 (UTC) Received: from mossypile.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: alindsay@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 6C64860FED; Fri, 16 Mar 2018 20:32:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521232351; bh=hD2JAL+smX2M7pgyuu36QrwMtC3z+hPAeONI/PxEw7U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=M/YJFfkRizn++NBZA7mxxf84TXHc7CJ97rkfiEGovO540TvcI5SNb27P8/BYEh8nL 1V16q6nmGXQCyMt3VeQJr7nC375+uqSXuiECUrPq6O46oXIUVNEWdsL+ybDi2w08Vk p/xR1LDAUdOqt6W3BfZeSh91EDcAyYxXHL7HI7go= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521232343; bh=hD2JAL+smX2M7pgyuu36QrwMtC3z+hPAeONI/PxEw7U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TqgqGHkxlsiPquEdHzQyN6aexi9IARSqFzGzgDPJXZavnz/g/EpKOK0rgdywGXlLb 5RyhvDLz0YuF13MHfvt+wkahGOcro1GdfuvCU8Cr2hhThsykvW/u5k8rElX0Rst7MV OK4pa/+HScmtNuPaIZtPFcCmYL50c25MUWHjPnSo= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 6C64860FED Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alindsay@codeaurora.org From: Aaron Lindsay To: qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Wei Huang , Peter Crosthwaite Date: Fri, 16 Mar 2018 16:31:18 -0400 Message-Id: <1521232280-13089-21-git-send-email-alindsay@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> References: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.96 Subject: [Qemu-devel] [PATCH v3 20/22] target/arm: PMU: Add instruction and cycle events X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Spradling , qemu-devel@nongnu.org, Digant Desai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The instruction event is only enabled when icount is used, cycles are always supported. Always defining get_cycle_count (but altering its behavior depending on CONFIG_USER_ONLY) allows us to remove some CONFIG_USER_ONLY #defines throughout the rest of the code. Signed-off-by: Aaron Lindsay Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/helper.c | 99 ++++++++++++++++++++++++++++---------------------= ---- 1 file changed, 52 insertions(+), 47 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 2fa8308..679897a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -15,6 +15,7 @@ #include "arm_ldst.h" #include /* For crc32 */ #include "exec/semihost.h" +#include "sysemu/cpus.h" #include "sysemu/kvm.h" #include "fpu/softfloat.h" =20 @@ -935,8 +936,54 @@ typedef struct pm_event { uint64_t (*get_count)(CPUARMState *, uint64_t cycles); } pm_event; =20 +/* + * Return the underlying cycle count for the PMU cycle counters. If we're = in + * usermode, simply return 0. + */ +static uint64_t get_cycle_count(CPUARMState *env) +{ +#ifndef CONFIG_USER_ONLY + return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); +#else + return 0; +#endif +} + +static bool event_always_supported(CPUARMState *env) +{ + return true; +} + +#ifndef CONFIG_USER_ONLY +static uint64_t cycles_get_count(CPUARMState *env, uint64_t cycles) +{ + return cycles; +} + +static bool instructions_supported(CPUARMState *env) +{ + return use_icount =3D=3D 1 /* Precise instruction counting */; +} + +static uint64_t instructions_get_count(CPUARMState *env, uint64_t cycles) +{ + return (uint64_t)cpu_get_icount_raw(); +} +#endif + #define SUPPORTED_EVENT_SENTINEL UINT16_MAX static const pm_event pm_events[] =3D { +#ifndef CONFIG_USER_ONLY + { .number =3D 0x008, /* INST_RETIRED */ + .supported =3D instructions_supported, + .get_count =3D instructions_get_count + }, + { .number =3D 0x011, /* CPU_CYCLES */ + .supported =3D event_always_supported, + .get_count =3D cycles_get_count + }, +#endif { .number =3D SUPPORTED_EVENT_SENTINEL } }; static uint16_t supported_event_map[0x3f]; @@ -1016,8 +1063,6 @@ static CPAccessResult pmreg_access_swinc(CPUARMState = *env, return pmreg_access(env, ri, isread); } =20 -#ifndef CONFIG_USER_ONLY - static CPAccessResult pmreg_access_selr(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) @@ -1126,11 +1171,7 @@ static inline bool pmu_counter_filtered(CPUARMState = *env, uint64_t pmxevtyper) */ uint64_t pmccntr_op_start(CPUARMState *env) { - uint64_t cycles =3D 0; -#ifndef CONFIG_USER_ONLY - cycles =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), - ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); -#endif + uint64_t cycles =3D get_cycle_count(env); =20 if (arm_ccnt_enabled(env) && !pmu_counter_filtered(env, env->cp15.pmccfiltr_el0)) { @@ -1268,26 +1309,6 @@ static void pmccntr_write32(CPUARMState *env, const = ARMCPRegInfo *ri, pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value)); } =20 -#else /* CONFIG_USER_ONLY */ - -uint64_t pmccntr_op_start(CPUARMState *env) -{ -} - -void pmccntr_op_finish(CPUARMState *env, uint64_t prev_cycles) -{ -} - -uint64_t pmu_op_start(CPUARMState *env) -{ -} - -void pmu_op_finish(CPUARMState *env, uint64_t prev_cycles) -{ -} - -#endif - static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -1346,11 +1367,7 @@ static void pmevtyper_write(CPUARMState *env, const = ARMCPRegInfo *ri, if (counter =3D=3D 0x1f) { pmccfiltr_write(env, ri, value); } else if (counter < PMU_NUM_COUNTERS(env)) { - uint64_t cycles =3D 0; -#ifndef CONFIG_USER_ONLY - cycles =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), - ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); -#endif + uint64_t cycles =3D get_cycle_count(env); pmu_sync_counter(env, counter, cycles); env->cp15.c14_pmevtyper[counter] =3D value & 0xfe0003ff; pmu_sync_counter(env, counter, cycles); @@ -1404,11 +1421,7 @@ static void pmevcntr_write(CPUARMState *env, const A= RMCPRegInfo *ri, uint64_t value, uint8_t counter) { if (counter < PMU_NUM_COUNTERS(env)) { - uint64_t cycles =3D 0; -#ifndef CONFIG_USER_ONLY - cycles =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), - ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); -#endif + uint64_t cycles =3D get_cycle_count(env); env->cp15.c14_pmevcntr[counter] =3D value; pmu_sync_counter(env, counter, cycles); } @@ -1420,12 +1433,8 @@ static uint64_t pmevcntr_read(CPUARMState *env, cons= t ARMCPRegInfo *ri, uint8_t counter) { if (counter < PMU_NUM_COUNTERS(env)) { - uint64_t ret; - uint64_t cycles =3D 0; -#ifndef CONFIG_USER_ONLY - cycles =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), - ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); -#endif + uint64_t ret, cycles; + cycles =3D get_cycle_count(env); pmu_sync_counter(env, counter, cycles); ret =3D env->cp15.c14_pmevcntr[counter]; pmu_sync_counter(env, counter, cycles); @@ -1613,7 +1622,6 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { /* Unimplemented so WI. */ { .name =3D "PMSWINC", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D = 0, .opc2 =3D 4, .access =3D PL0_W, .accessfn =3D pmreg_access_swinc, .type =3D ARM_C= P_NOP }, -#ifndef CONFIG_USER_ONLY { .name =3D "PMSELR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 5, .access =3D PL0_RW, .type =3D ARM_CP_ALIAS, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmselr), @@ -1633,7 +1641,6 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .access =3D PL0_RW, .accessfn =3D pmreg_access_ccntr, .type =3D ARM_CP_IO, .readfn =3D pmccntr_read, .writefn =3D pmccntr_write, }, -#endif { .name =3D "PMCCFILTR", .cp =3D 15, .opc1 =3D 0, .crn =3D 14, .crm = =3D 15, .opc2 =3D 7, .writefn =3D pmccfiltr_write_a32, .readfn =3D pmccfiltr_read_a32, .access =3D PL0_RW, .accessfn =3D pmreg_access, @@ -5171,7 +5178,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) * field as main ID register, and we implement only the cycle * count register. */ -#ifndef CONFIG_USER_ONLY ARMCPRegInfo pmcr =3D { .name =3D "PMCR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 = =3D 0, .opc2 =3D 0, .access =3D PL0_RW, @@ -5225,7 +5231,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) g_free(pmevtyper_name); g_free(pmevtyper_el0_name); } -#endif ARMCPRegInfo clidr =3D { .name =3D "CLIDR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 1, .opc2 =3D 1, --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.