From nobody Sat Oct 25 02:27:18 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521232526449600.469165389708; Fri, 16 Mar 2018 13:35:26 -0700 (PDT) Received: from localhost ([::1]:59440 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eww4T-0007si-LE for importer@patchew.org; Fri, 16 Mar 2018 16:35:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43765) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eww1D-0005cR-0q for qemu-devel@nongnu.org; Fri, 16 Mar 2018 16:32:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eww1C-00033j-5i for qemu-devel@nongnu.org; Fri, 16 Mar 2018 16:32:03 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:55236) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eww16-0002vf-NP; Fri, 16 Mar 2018 16:31:56 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id BA15560C5F; Fri, 16 Mar 2018 20:31:55 +0000 (UTC) Received: from mossypile.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: alindsay@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 24F6860390; Fri, 16 Mar 2018 20:31:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521232315; bh=fAmTx2/b74GGKbiY+3IVPm0hnhFIxlupKtSdYtK5Cu0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kBWMXqb74K5QB9sNFc9bj+wsEMTLbNjmSSE1S2N849nXKSl2W+Fmd2y0gXdnRiKgk XLM9GJWLqimL126nG99OqGeNDUz+Aifjwk85H6OI0rRKIPvZY/nNs4x5XJjkI3r53a t5p4U5volyqWFvhHAOYq4mz25OiX0IVxtojko/r0= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521232315; bh=fAmTx2/b74GGKbiY+3IVPm0hnhFIxlupKtSdYtK5Cu0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kBWMXqb74K5QB9sNFc9bj+wsEMTLbNjmSSE1S2N849nXKSl2W+Fmd2y0gXdnRiKgk XLM9GJWLqimL126nG99OqGeNDUz+Aifjwk85H6OI0rRKIPvZY/nNs4x5XJjkI3r53a t5p4U5volyqWFvhHAOYq4mz25OiX0IVxtojko/r0= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 24F6860390 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alindsay@codeaurora.org From: Aaron Lindsay To: qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Wei Huang , Peter Crosthwaite Date: Fri, 16 Mar 2018 16:30:59 -0400 Message-Id: <1521232280-13089-2-git-send-email-alindsay@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> References: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.96 Subject: [Qemu-devel] [PATCH v3 01/22] target/arm: A53: Initialize PMCEID[01] X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Spradling , qemu-devel@nongnu.org, Digant Desai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" A53 advertises ARM_FEATURE_PMU, but wasn't initializing pmceid[01]. pmceid[01] are already being initialized to zero for both A15 and A57. Signed-off-by: Aaron Lindsay --- target/arm/cpu64.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 991d764..8c4db31 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -201,6 +201,8 @@ static void aarch64_a53_initfn(Object *obj) cpu->id_isar5 =3D 0x00011121; cpu->id_aa64pfr0 =3D 0x00002222; cpu->id_aa64dfr0 =3D 0x10305106; + cpu->pmceid0 =3D 0x00000000; + cpu->pmceid1 =3D 0x00000000; cpu->id_aa64isar0 =3D 0x00011120; cpu->id_aa64mmfr0 =3D 0x00001122; /* 40 bit physical addr */ cpu->dbgdidr =3D 0x3516d000; --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. From nobody Sat Oct 25 02:27:18 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15212326516431016.3223793483409; Fri, 16 Mar 2018 13:37:31 -0700 (PDT) Received: from localhost ([::1]:59459 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eww6U-0001Hq-Lb for importer@patchew.org; Fri, 16 Mar 2018 16:37:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43795) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eww1D-0005eS-RU for qemu-devel@nongnu.org; Fri, 16 Mar 2018 16:32:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eww1D-00034h-0i for qemu-devel@nongnu.org; Fri, 16 Mar 2018 16:32:03 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:55364) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eww1A-000315-RT; Fri, 16 Mar 2018 16:32:00 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id E2D7360C66; Fri, 16 Mar 2018 20:31:59 +0000 (UTC) Received: from mossypile.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: alindsay@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 6CBFA60C4F; Fri, 16 Mar 2018 20:31:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521232319; bh=TidfQxPX4pOaIvomEefQibfdPlA8IL9evII85VkavH0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nJjdAXHjQ6CdzN5ZiLThdOH+M3Ude9JZmLQYp++GIDDsCIwMrtL/1OIyQqxycGokb 5X4VWgDvIhC3dgDUO+HfajVVG9aBGXYTfS14nqzRURv6pHXI0wGxd51s1O368Uc3N8 lYFtaM6B8QgiMpRSBS6ctWrtXJvQV+FXOEyzdUZ4= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521232319; bh=TidfQxPX4pOaIvomEefQibfdPlA8IL9evII85VkavH0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nJjdAXHjQ6CdzN5ZiLThdOH+M3Ude9JZmLQYp++GIDDsCIwMrtL/1OIyQqxycGokb 5X4VWgDvIhC3dgDUO+HfajVVG9aBGXYTfS14nqzRURv6pHXI0wGxd51s1O368Uc3N8 lYFtaM6B8QgiMpRSBS6ctWrtXJvQV+FXOEyzdUZ4= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 6CBFA60C4F Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alindsay@codeaurora.org From: Aaron Lindsay To: qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Wei Huang , Peter Crosthwaite Date: Fri, 16 Mar 2018 16:31:00 -0400 Message-Id: <1521232280-13089-3-git-send-email-alindsay@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> References: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.96 Subject: [Qemu-devel] [PATCH v3 02/22] target/arm: A15 PMCEID0 initialization style nit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Spradling , qemu-devel@nongnu.org, Digant Desai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell --- target/arm/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 022d8c5..072cbbf 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1524,7 +1524,7 @@ static void cortex_a15_initfn(Object *obj) cpu->id_pfr0 =3D 0x00001131; cpu->id_pfr1 =3D 0x00011011; cpu->id_dfr0 =3D 0x02010555; - cpu->pmceid0 =3D 0x0000000; + cpu->pmceid0 =3D 0x00000000; cpu->pmceid1 =3D 0x00000000; cpu->id_afr0 =3D 0x00000000; cpu->id_mmfr0 =3D 0x10201105; --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. From nobody Sat Oct 25 02:27:18 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521232489232430.95943380341464; Fri, 16 Mar 2018 13:34:49 -0700 (PDT) Received: from localhost ([::1]:59439 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eww3s-0007Qi-DT for importer@patchew.org; Fri, 16 Mar 2018 16:34:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43837) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eww1F-0005gq-8N for qemu-devel@nongnu.org; Fri, 16 Mar 2018 16:32:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eww1E-00037e-Bh for qemu-devel@nongnu.org; Fri, 16 Mar 2018 16:32:05 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:55446) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eww1C-00032r-5K; Fri, 16 Mar 2018 16:32:02 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 47B3A60F6D; Fri, 16 Mar 2018 20:32:01 +0000 (UTC) Received: from mossypile.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: alindsay@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 8E6AF60C5F; Fri, 16 Mar 2018 20:31:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521232321; bh=QGACvL5j2mW267acZxwzp/A8X9+G3iPASyt8JaZBUI8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HVKaHtNinm8L71hSDO9Fvp2W/3Ys2mAV1IUPUkA8yAUBUuUN18xqTou+xf7MS6h+j IWAtMdRT3Qb6LtAjVD82cGMRE4rIpZX0ekn60XXwFiNdqa0OSBxToQ4PgYzgODvuXt aW9aRzq12MdvTM/3Zx1Z2UQU6hefQnVT8KTRGtGs= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521232320; bh=QGACvL5j2mW267acZxwzp/A8X9+G3iPASyt8JaZBUI8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=X3UwNDP6iFtvsa00aCxTJKdRYHJ/YVebPulXW7/aHnlqtPBJMRAWlf10sCzgz9N9a cOIgE0kMXDIMsEHRc7cL3N40LFbgpwCMesx4gSPWNj5qOF7Nrj/Iv1kdDQx1Vo53iE Y2SChQFmYNwrl5ERvj1ieFkv7ePQfgHIrFh5405Q= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 8E6AF60C5F Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alindsay@codeaurora.org From: Aaron Lindsay To: qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Wei Huang , Peter Crosthwaite Date: Fri, 16 Mar 2018 16:31:01 -0400 Message-Id: <1521232280-13089-4-git-send-email-alindsay@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> References: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.96 Subject: [Qemu-devel] [PATCH v3 03/22] target/arm: Check PMCNTEN for whether PMCCNTR is enabled X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Spradling , qemu-devel@nongnu.org, Digant Desai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 09893e3..5e48982 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -994,7 +994,7 @@ static inline bool arm_ccnt_enabled(CPUARMState *env) { /* This does not support checking PMCCFILTR_EL0 register */ =20 - if (!(env->cp15.c9_pmcr & PMCRE)) { + if (!(env->cp15.c9_pmcr & PMCRE) || !(env->cp15.c9_pmcnten & (1 << 31)= )) { return false; } =20 --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. From nobody Sat Oct 25 02:27:18 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521232666963200.2570369791057; Fri, 16 Mar 2018 13:37:46 -0700 (PDT) Received: from localhost ([::1]:59461 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eww6f-0001UH-Mq for importer@patchew.org; Fri, 16 Mar 2018 16:37:41 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43873) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eww1G-0005iV-SK for qemu-devel@nongnu.org; Fri, 16 Mar 2018 16:32:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eww1G-00039u-0W for qemu-devel@nongnu.org; Fri, 16 Mar 2018 16:32:06 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:55512) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eww1D-00034I-8B; Fri, 16 Mar 2018 16:32:03 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 4B94560F71; Fri, 16 Mar 2018 20:32:02 +0000 (UTC) Received: from mossypile.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: alindsay@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id B3C5060F5C; Fri, 16 Mar 2018 20:32:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521232322; bh=F0eczBJ8qIiSvzJV57Z/jtH2JVu0o4r0fUmil4HtDUo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ad0hi1kDngS68clfk0K9kdtkC/14hdhfKtE15cE8o/1AGEcj9HDpSD1zoz2FwdiVU QFIq6/No2RnCxV3+gFHh3IIujjfI+hC4k6/p7B3WtIC8xJAst8jf9edy+6SUkKIH2q a36QLmJXGCkNySAMpjjeIpytlNthxoUHZWEiBGkU= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521232321; bh=F0eczBJ8qIiSvzJV57Z/jtH2JVu0o4r0fUmil4HtDUo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FKzOinkMW71Gjme2wGt35AVAKPEYno5uMSPj7vcD/NYJ7YSzk10BJJKbxhfZ4K3Oa iHh/yBDHaC8qhQLIwRIC4Hc3GZg3oV7+mWqeINVlXoUHuVAO+2N0tq2p58Q8Hi7b5h QafrLnZ6l+zZH9YxVmsK3XjlvCcQq8ZS+VEPf0YQ= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org B3C5060F5C Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alindsay@codeaurora.org From: Aaron Lindsay To: qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Wei Huang , Peter Crosthwaite Date: Fri, 16 Mar 2018 16:31:02 -0400 Message-Id: <1521232280-13089-5-git-send-email-alindsay@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> References: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.96 Subject: [Qemu-devel] [PATCH v3 04/22] target/arm: Treat PMCCNTR as alias of PMCCNTR_EL0 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Spradling , qemu-devel@nongnu.org, Digant Desai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" They share the same underlying state Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 5e48982..5634561 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1318,7 +1318,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmselr), .writefn =3D pmselr_write, .raw_writefn =3D raw_write, }, { .name =3D "PMCCNTR", .cp =3D 15, .crn =3D 9, .crm =3D 13, .opc1 =3D = 0, .opc2 =3D 0, - .access =3D PL0_RW, .resetvalue =3D 0, .type =3D ARM_CP_IO, + .access =3D PL0_RW, .resetvalue =3D 0, .type =3D ARM_CP_ALIAS | ARM_= CP_IO, .readfn =3D pmccntr_read, .writefn =3D pmccntr_write32, .accessfn =3D pmreg_access_ccntr }, { .name =3D "PMCCNTR_EL0", .state =3D ARM_CP_STATE_AA64, --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. From nobody Sat Oct 25 02:27:18 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521232734514383.0800473809038; Fri, 16 Mar 2018 13:38:54 -0700 (PDT) Received: from localhost ([::1]:59463 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eww7f-0002P7-S3 for importer@patchew.org; Fri, 16 Mar 2018 16:38:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43953) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eww1L-0005mh-6R for qemu-devel@nongnu.org; Fri, 16 Mar 2018 16:32:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eww1I-0003C3-H6 for qemu-devel@nongnu.org; Fri, 16 Mar 2018 16:32:11 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:55554) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eww1E-000375-JM; Fri, 16 Mar 2018 16:32:04 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 6A6CC607A2; Fri, 16 Mar 2018 20:32:03 +0000 (UTC) Received: from mossypile.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: alindsay@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id DB95360F6E; Fri, 16 Mar 2018 20:32:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521232323; bh=XR0w3vuhnIaJKlecQsU8wpBF+97ful+VGDzHZuSfjMc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ounrQ/oyDku7lE7GSfozhN3nk1o+zg2RJcZEAWAhQwAuMlXuQWXhx6zCvypu881qo Mb/3nhuukWCCsa9rQFL9v3hf5gTd42PJfpjGGcQt+I9KvjATT2szKKc1bQ/69l/80g uoArGgqVoE7gFqHRmkpq+crdVOwlqoU2CzCL1wFo= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521232322; bh=XR0w3vuhnIaJKlecQsU8wpBF+97ful+VGDzHZuSfjMc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Q8hRg/dr8o78IVFOnftPQZYcl8JZAa1EIU8kj291HrSFp+nugyPdtcWSEx5mtQrCw BHnyqiIZtby+JarXdDG70nCf7aMOs8tO7oDCjmKC82zY1QT5GEInFg0j3TU8pbWOpx ie+UWVnA9kJCfk7v6b/VyZ9cv+4Z/7o/0d34aZd4= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org DB95360F6E Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alindsay@codeaurora.org From: Aaron Lindsay To: qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Wei Huang , Peter Crosthwaite Date: Fri, 16 Mar 2018 16:31:03 -0400 Message-Id: <1521232280-13089-6-git-send-email-alindsay@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> References: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.96 Subject: [Qemu-devel] [PATCH v3 05/22] target/arm: Reorganize PMCCNTR read, write, sync X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Spradling , qemu-devel@nongnu.org, Digant Desai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" pmccntr_read and pmccntr_write contained duplicate code that was already being handled by pmccntr_sync. Split pmccntr_sync into pmccntr_op_start and pmccntr_op_finish, passing the clock value between the two, to avoid losing time between the two calls. Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell --- target/arm/helper.c | 101 +++++++++++++++++++++++++++++-------------------= ---- 1 file changed, 56 insertions(+), 45 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 5634561..6480b80 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1000,28 +1000,58 @@ static inline bool arm_ccnt_enabled(CPUARMState *en= v) =20 return true; } - -void pmccntr_sync(CPUARMState *env) +/* + * Ensure c15_ccnt is the guest-visible count so that operations such as + * enabling/disabling the counter or filtering, modifying the count itself, + * etc. can be done logically. This is essentially a no-op if the counter = is + * not enabled at the time of the call. + * + * The current cycle count is returned so that it can be passed into the p= aired + * pmccntr_op_finish() call which must follow each call to pmccntr_op_star= t(). + */ +uint64_t pmccntr_op_start(CPUARMState *env) { - uint64_t temp_ticks; - - temp_ticks =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + uint64_t cycles =3D 0; +#ifndef CONFIG_USER_ONLY + cycles =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); +#endif + + if (arm_ccnt_enabled(env)) { =20 - if (env->cp15.c9_pmcr & PMCRD) { - /* Increment once every 64 processor clock cycles */ - temp_ticks /=3D 64; + uint64_t eff_cycles =3D cycles; + if (env->cp15.c9_pmcr & PMCRD) { + /* Increment once every 64 processor clock cycles */ + eff_cycles /=3D 64; + } + + env->cp15.c15_ccnt =3D eff_cycles - env->cp15.c15_ccnt; } + return cycles; +} =20 +/* + * If enabled, convert c15_ccnt back into the delta between the clock and = the + * guest-visible count. A call to pmccntr_op_finish should follow every ca= ll to + * pmccntr_op_start. + */ +void pmccntr_op_finish(CPUARMState *env, uint64_t prev_cycles) +{ if (arm_ccnt_enabled(env)) { - env->cp15.c15_ccnt =3D temp_ticks - env->cp15.c15_ccnt; + + if (env->cp15.c9_pmcr & PMCRD) { + /* Increment once every 64 processor clock cycles */ + prev_cycles /=3D 64; + } + + env->cp15.c15_ccnt =3D prev_cycles - env->cp15.c15_ccnt; } } =20 static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - pmccntr_sync(env); + uint64_t saved_cycles =3D pmccntr_op_start(env); =20 if (value & PMCRC) { /* The counter has been reset */ @@ -1032,26 +1062,16 @@ static void pmcr_write(CPUARMState *env, const ARMC= PRegInfo *ri, env->cp15.c9_pmcr &=3D ~0x39; env->cp15.c9_pmcr |=3D (value & 0x39); =20 - pmccntr_sync(env); + pmccntr_op_finish(env, saved_cycles); } =20 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) { - uint64_t total_ticks; - - if (!arm_ccnt_enabled(env)) { - /* Counter is disabled, do not change value */ - return env->cp15.c15_ccnt; - } - - total_ticks =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), - ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); - - if (env->cp15.c9_pmcr & PMCRD) { - /* Increment once every 64 processor clock cycles */ - total_ticks /=3D 64; - } - return total_ticks - env->cp15.c15_ccnt; + uint64_t ret; + uint64_t saved_cycles =3D pmccntr_op_start(env); + ret =3D env->cp15.c15_ccnt; + pmccntr_op_finish(env, saved_cycles); + return ret; } =20 static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -1068,22 +1088,9 @@ static void pmselr_write(CPUARMState *env, const ARM= CPRegInfo *ri, static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - uint64_t total_ticks; - - if (!arm_ccnt_enabled(env)) { - /* Counter is disabled, set the absolute value */ - env->cp15.c15_ccnt =3D value; - return; - } - - total_ticks =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), - ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); - - if (env->cp15.c9_pmcr & PMCRD) { - /* Increment once every 64 processor clock cycles */ - total_ticks /=3D 64; - } - env->cp15.c15_ccnt =3D total_ticks - value; + uint64_t saved_cycles =3D pmccntr_op_start(env); + env->cp15.c15_ccnt =3D value; + pmccntr_op_finish(env, saved_cycles); } =20 static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri, @@ -1096,7 +1103,11 @@ static void pmccntr_write32(CPUARMState *env, const = ARMCPRegInfo *ri, =20 #else /* CONFIG_USER_ONLY */ =20 -void pmccntr_sync(CPUARMState *env) +uint64_t pmccntr_op_start(CPUARMState *env) +{ +} + +void pmccntr_op_finish(CPUARMState *env, uint64_t prev_cycles) { } =20 @@ -1105,9 +1116,9 @@ void pmccntr_sync(CPUARMState *env) static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - pmccntr_sync(env); + uint64_t saved_cycles =3D pmccntr_op_start(env); env->cp15.pmccfiltr_el0 =3D value & 0x7E000000; - pmccntr_sync(env); + pmccntr_op_finish(env, saved_cycles); } =20 static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. 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charset="utf-8" This is in preparation for enabling counters other than PMCCNTR Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell --- target/arm/helper.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 6480b80..5d5c738 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -52,11 +52,6 @@ typedef struct V8M_SAttributes { static void v8m_security_lookup(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_i= dx, V8M_SAttributes *sattrs); - -/* Definitions for the PMCCNTR and PMCR registers */ -#define PMCRD 0x8 -#define PMCRC 0x4 -#define PMCRE 0x1 #endif =20 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) @@ -906,6 +901,17 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { REGINFO_SENTINEL }; =20 +/* Definitions for the PMU registers */ +#define PMCRN_MASK 0xf800 +#define PMCRN_SHIFT 11 +#define PMCRD 0x8 +#define PMCRC 0x4 +#define PMCRE 0x1 + +#define PMU_NUM_COUNTERS(env) ((env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_S= HIFT) +/* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */ +#define PMU_COUNTER_MASK(env) ((1 << 31) | ((1 << PMU_NUM_COUNTERS(env)) -= 1)) + static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *r= i, bool isread) { @@ -1124,14 +1130,14 @@ static void pmccfiltr_write(CPUARMState *env, const= ARMCPRegInfo *ri, static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - value &=3D (1 << 31); + value &=3D PMU_COUNTER_MASK(env); env->cp15.c9_pmcnten |=3D value; } =20 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - value &=3D (1 << 31); + value &=3D PMU_COUNTER_MASK(env); env->cp15.c9_pmcnten &=3D ~value; } =20 @@ -1179,14 +1185,14 @@ static void pmintenset_write(CPUARMState *env, cons= t ARMCPRegInfo *ri, uint64_t value) { /* We have no event counters so only the C bit can be changed */ - value &=3D (1 << 31); + value &=3D PMU_COUNTER_MASK(env); env->cp15.c9_pminten |=3D value; } =20 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - value &=3D (1 << 31); + value &=3D PMU_COUNTER_MASK(env); env->cp15.c9_pminten &=3D ~value; } =20 --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. From nobody Sat Oct 25 02:27:18 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521232837978360.38537848882186; Fri, 16 Mar 2018 13:40:37 -0700 (PDT) Received: from localhost ([::1]:59477 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eww9V-0004AG-5O for importer@patchew.org; Fri, 16 Mar 2018 16:40:37 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44034) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eww1O-0005ot-6j for qemu-devel@nongnu.org; Fri, 16 Mar 2018 16:32:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eww1N-0003Hk-6W for qemu-devel@nongnu.org; Fri, 16 Mar 2018 16:32:14 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:55730) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eww1I-0003BW-Eu; Fri, 16 Mar 2018 16:32:08 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 4A23C60F6C; Fri, 16 Mar 2018 20:32:06 +0000 (UTC) Received: from mossypile.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: alindsay@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 4936060C66; Fri, 16 Mar 2018 20:32:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521232327; bh=/eCsgLQSA5KHnEe41gnOXtRGEqqomhKq/bclOqgGKng=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FpA4hhyABD8NAJU5GhgoOa2UoVkOUKLoLviJbYO3ljSiEEvxLQJ/KJCpXLt/JaMi3 z6QqOvqyHQyYe497LiDQWPX4ePxswUEgBcZyWSjafInKl/NmzNmQl8+Se13gdYcTKV X7Tghf9WDJJaTBz0bH5JylOVpaO6O6cY4BOQGULQ= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521232325; bh=/eCsgLQSA5KHnEe41gnOXtRGEqqomhKq/bclOqgGKng=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lPpN6pTaLEWg2mj8iyxF9aMqakH8ky6yAk2vLRiE2Tyxw24p0cnlvkaXrrvuumQly tUZd59ufV74e+mTlIxjsyNNwwMm0auhbm3AP4WFWloMnkJ1mDqz5IIpOksZIhdSavQ smwK9pTNcLa6aIVt0QrPeaMS4llVubLB+kAAICsQ= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 4936060C66 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alindsay@codeaurora.org From: Aaron Lindsay To: qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Wei Huang , Peter Crosthwaite Date: Fri, 16 Mar 2018 16:31:05 -0400 Message-Id: <1521232280-13089-8-git-send-email-alindsay@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> References: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.96 Subject: [Qemu-devel] [PATCH v3 07/22] target/arm: Fetch GICv3 state directly from CPUARMState X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Spradling , qemu-devel@nongnu.org, Digant Desai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This eliminates the need for fetching it from el_change_hook_opaque, and allows for supporting multiple el_change_hooks without having to hack something together to find the registered opaque belonging to GICv3. Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell --- hw/intc/arm_gicv3_cpuif.c | 10 ++-------- target/arm/cpu.h | 10 ---------- 2 files changed, 2 insertions(+), 18 deletions(-) diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 5cbafaf..801f91b 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -29,11 +29,7 @@ void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *= s) =20 static GICv3CPUState *icc_cs_from_env(CPUARMState *env) { - /* Given the CPU, find the right GICv3CPUState struct. - * Since we registered the CPU interface with the EL change hook as - * the opaque pointer, we can just directly get from the CPU to it. - */ - return arm_get_el_change_hook_opaque(arm_env_get_cpu(env)); + return env->gicv3state; } =20 static bool gicv3_use_ns_bank(CPUARMState *env) @@ -2615,9 +2611,7 @@ void gicv3_init_cpuif(GICv3State *s) * it might be with code translated by CPU 0 but run by CPU 1, in * which case we'd get the wrong value. * So instead we define the regs with no ri->opaque info, and - * get back to the GICv3CPUState from the ARMCPU by reading back - * the opaque pointer from the el_change_hook, which we're going - * to need to register anyway. + * get back to the GICv3CPUState from the CPUARMState. */ define_arm_cp_regs(cpu, gicv3_cpuif_reginfo); if (arm_feature(&cpu->env, ARM_FEATURE_EL2) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1e7e1f8..f17592b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2904,16 +2904,6 @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELC= hangeHook *hook, void *opaque); =20 /** - * arm_get_el_change_hook_opaque: - * Return the opaque data that will be used by the el_change_hook - * for this CPU. - */ -static inline void *arm_get_el_change_hook_opaque(ARMCPU *cpu) -{ - return cpu->el_change_hook_opaque; -} - -/** * aa32_vfp_dreg: * Return a pointer to the Dn register within env in 32-bit mode. */ --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. 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h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GHG1Oy2a8efoshu+o0yBccOTd39C7Syg4wYWGh0+YTpDAJwvwRSUWDPfxtLlEgHnA lbabjSEZahYu3ljWd6o8LkFvWlIrcgBQ9JDaE+is7FwwKcAlX4ee5rgAVpwFMPSfEq MovvNvok8oTV3K/XHT8sqfTdC/X48/DfUYAFObJs= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521232326; bh=sDuiE6LXXfdX5487SXN6aqIm5QZvYG3GALksd6/HLRs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NVWtpkXnz0h2DzfcDngwegkw3fq+FoD3w77K08wzVKMLJJENZcaoUXJWOqfiTBRkt 8nIYbxUDHfQaVKlO1gJtB4yKjTOEcXfhw5v9olGbvdB2NZZ726WE6CClDQKNLmgK/Z 5HHYMUrL1sTnx7tznRyaaTJLy8BjuK8SANMJjEDs= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org AE9156055D Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alindsay@codeaurora.org From: Aaron Lindsay To: qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Wei Huang , Peter Crosthwaite Date: Fri, 16 Mar 2018 16:31:06 -0400 Message-Id: <1521232280-13089-9-git-send-email-alindsay@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> References: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.96 Subject: [Qemu-devel] [PATCH v3 08/22] target/arm: Support multiple EL change hooks X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Spradling , qemu-devel@nongnu.org, Digant Desai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Aaron Lindsay --- target/arm/cpu.c | 15 ++++++++++----- target/arm/cpu.h | 23 ++++++++++++----------- target/arm/internals.h | 7 ++++--- 3 files changed, 26 insertions(+), 19 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 072cbbf..5f782bf 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -55,13 +55,16 @@ static bool arm_cpu_has_work(CPUState *cs) | CPU_INTERRUPT_EXITTB); } =20 -void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook, +void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void *opaque) { - /* We currently only support registering a single hook function */ - assert(!cpu->el_change_hook); - cpu->el_change_hook =3D hook; - cpu->el_change_hook_opaque =3D opaque; + ARMELChangeHook *entry; + entry =3D g_malloc0(sizeof (*entry)); + + entry->hook =3D hook; + entry->opaque =3D opaque; + + QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); } =20 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) @@ -744,6 +747,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error *= *errp) return; } =20 + QLIST_INIT(&cpu->el_change_hooks); + /* Some features automatically imply others: */ if (arm_feature(env, ARM_FEATURE_V8)) { set_feature(env, ARM_FEATURE_V7); diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f17592b..3b45d3d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -633,11 +633,17 @@ typedef struct CPUARMState { =20 /** * ARMELChangeHook: - * type of a function which can be registered via arm_register_el_change_h= ook() - * to get callbacks when the CPU changes its exception level or mode. + * Support registering functions with ARMELChangeHookFn's signature via + * arm_register_el_change_hook() to get callbacks when the CPU changes its + * exception level or mode. */ -typedef void ARMELChangeHook(ARMCPU *cpu, void *opaque); - +typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); +typedef struct ARMELChangeHook ARMELChangeHook; +struct ARMELChangeHook { + ARMELChangeHookFn *hook; + void *opaque; + QLIST_ENTRY(ARMELChangeHook) node; +}; =20 /* These values map onto the return values for * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ @@ -826,8 +832,7 @@ struct ARMCPU { */ bool cfgend; =20 - ARMELChangeHook *el_change_hook; - void *el_change_hook_opaque; + QLIST_HEAD(, ARMELChangeHook) el_change_hooks; =20 int32_t node_id; /* NUMA node this CPU belongs to */ =20 @@ -2895,12 +2900,8 @@ static inline AddressSpace *arm_addressspace(CPUStat= e *cs, MemTxAttrs attrs) * CPU changes exception level or mode. The hook function will be * passed a pointer to the ARMCPU and the opaque data pointer passed * to this function when the hook was registered. - * - * Note that we currently only support registering a single hook function, - * and will assert if this function is called twice. - * This facility is intended for the use of the GICv3 emulation. */ -void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook, +void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void *opaque); =20 /** diff --git a/target/arm/internals.h b/target/arm/internals.h index 47cc224..7df3eda 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -727,11 +727,12 @@ void arm_cpu_do_transaction_failed(CPUState *cs, hwad= dr physaddr, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retaddr= ); =20 -/* Call the EL change hook if one has been registered */ +/* Call any registered EL change hooks */ static inline void arm_call_el_change_hook(ARMCPU *cpu) { - if (cpu->el_change_hook) { - cpu->el_change_hook(cpu, cpu->el_change_hook_opaque); + ARMELChangeHook *hook, *next; + QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { + hook->hook(cpu, hook->opaque); } } =20 --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. From nobody Sat Oct 25 02:27:18 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521233156250348.33538933905515; Fri, 16 Mar 2018 13:45:56 -0700 (PDT) Received: from localhost ([::1]:59528 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewwEd-0000jm-CS for importer@patchew.org; Fri, 16 Mar 2018 16:45:55 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44107) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eww1Q-0005sI-TV for qemu-devel@nongnu.org; Fri, 16 Mar 2018 16:32:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eww1P-0003Kh-Es for qemu-devel@nongnu.org; Fri, 16 Mar 2018 16:32:16 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:55930) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eww1M-0003Fs-9W; Fri, 16 Mar 2018 16:32:12 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 0D1BC60D81; Fri, 16 Mar 2018 20:32:09 +0000 (UTC) Received: from mossypile.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: alindsay@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 25E2660FA8; Fri, 16 Mar 2018 20:32:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521232331; bh=3l8vY/oVAgpFoTIYeZx9r5HsOKCzalxyT4ouiCTQrDg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=P5A8F1Ng+psp1ZUQNkkDAGGtgQMDDXvyMB6btZUVEvhfEB+NkhNt/37hGEF2mavfI R5ZmcPIKVloJISsHOfMrk1av+6pU+sUQciUkpMeym4alHtxp2tNsByB9K9EZWLg4q9 QiPVTbCGOOJ3pJsJWXgqsAuxl1TfdanFbueJrwtM= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521232328; bh=3l8vY/oVAgpFoTIYeZx9r5HsOKCzalxyT4ouiCTQrDg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oonkuxFkGOylWKywpPflIeEk9njcW5WQUc9dXVSAAEBqmqDlkl5Hp9QWl/2Oe4r32 sWNdmwfyn5htQdAcms8gFp0KbRz/mYjafHH42c9nd8Ri0cj/lrsazAi5cmgx0AKhBp 6z8+ifKsXzxUleUErHSdjy6GoKnkr5Tfuum97YqU= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 25E2660FA8 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alindsay@codeaurora.org From: Aaron Lindsay To: qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Wei Huang , Peter Crosthwaite Date: Fri, 16 Mar 2018 16:31:07 -0400 Message-Id: <1521232280-13089-10-git-send-email-alindsay@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> References: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.96 Subject: [Qemu-devel] [PATCH v3 09/22] target/arm: Add pre-EL change hooks X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Spradling , qemu-devel@nongnu.org, Digant Desai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Because the design of the PMU requires that the counter values be converted between their delta and guest-visible forms for mode filtering, an additional hook which occurs before the EL is changed is necessary. Signed-off-by: Aaron Lindsay --- target/arm/cpu.c | 13 +++++++++++++ target/arm/cpu.h | 12 ++++++++---- target/arm/helper.c | 14 ++++++++------ target/arm/internals.h | 7 +++++++ target/arm/op_helper.c | 8 ++++++++ 5 files changed, 44 insertions(+), 10 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5f782bf..a2cb21e 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -55,6 +55,18 @@ static bool arm_cpu_has_work(CPUState *cs) | CPU_INTERRUPT_EXITTB); } =20 +void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, + void *opaque) +{ + ARMELChangeHook *entry; + entry =3D g_malloc0(sizeof (*entry)); + + entry->hook =3D hook; + entry->opaque =3D opaque; + + QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); +} + void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void *opaque) { @@ -747,6 +759,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error *= *errp) return; } =20 + QLIST_INIT(&cpu->pre_el_change_hooks); QLIST_INIT(&cpu->el_change_hooks); =20 /* Some features automatically imply others: */ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 3b45d3d..b0ef727 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -832,6 +832,7 @@ struct ARMCPU { */ bool cfgend; =20 + QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; QLIST_HEAD(, ARMELChangeHook) el_change_hooks; =20 int32_t node_id; /* NUMA node this CPU belongs to */ @@ -2895,12 +2896,15 @@ static inline AddressSpace *arm_addressspace(CPUSta= te *cs, MemTxAttrs attrs) #endif =20 /** + * arm_register_pre_el_change_hook: * arm_register_el_change_hook: - * Register a hook function which will be called back whenever this - * CPU changes exception level or mode. The hook function will be - * passed a pointer to the ARMCPU and the opaque data pointer passed - * to this function when the hook was registered. + * Register a hook function which will be called back before or after this= CPU + * changes exception level or mode. The hook function will be passed a poi= nter + * to the ARMCPU and the opaque data pointer passed to this function when = the + * hook was registered. */ +void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, + void *opaque); void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void *opaque); =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index 5d5c738..50eaed7 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8253,6 +8253,14 @@ void arm_cpu_do_interrupt(CPUState *cs) return; } =20 + /* Hooks may change global state so BQL should be held, also the + * BQL needs to be held for any modification of + * cs->interrupt_request. + */ + g_assert(qemu_mutex_iothread_locked()); + + arm_call_pre_el_change_hook(cpu); + assert(!excp_is_internal(cs->exception_index)); if (arm_el_is_aa64(env, new_el)) { arm_cpu_do_interrupt_aarch64(cs); @@ -8260,12 +8268,6 @@ void arm_cpu_do_interrupt(CPUState *cs) arm_cpu_do_interrupt_aarch32(cs); } =20 - /* Hooks may change global state so BQL should be held, also the - * BQL needs to be held for any modification of - * cs->interrupt_request. - */ - g_assert(qemu_mutex_iothread_locked()); - arm_call_el_change_hook(cpu); =20 if (!kvm_enabled()) { diff --git a/target/arm/internals.h b/target/arm/internals.h index 7df3eda..6ea6766 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -728,6 +728,13 @@ void arm_cpu_do_transaction_failed(CPUState *cs, hwadd= r physaddr, MemTxResult response, uintptr_t retaddr= ); =20 /* Call any registered EL change hooks */ +static inline void arm_call_pre_el_change_hook(ARMCPU *cpu) +{ + ARMELChangeHook *hook, *next; + QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { + hook->hook(cpu, hook->opaque); + } +} static inline void arm_call_el_change_hook(ARMCPU *cpu) { ARMELChangeHook *hook, *next; diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 7a88fd2..be417ce 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -496,6 +496,10 @@ void HELPER(cpsr_write)(CPUARMState *env, uint32_t val= , uint32_t mask) /* Write the CPSR for a 32-bit exception return */ void HELPER(cpsr_write_eret)(CPUARMState *env, uint32_t val) { + qemu_mutex_lock_iothread(); + arm_call_pre_el_change_hook(arm_env_get_cpu(env)); + qemu_mutex_unlock_iothread(); + cpsr_write(env, val, CPSR_ERET_MASK, CPSRWriteExceptionReturn); =20 /* Generated code has already stored the new PC value, but @@ -1013,6 +1017,10 @@ void HELPER(exception_return)(CPUARMState *env) goto illegal_return; } =20 + qemu_mutex_lock_iothread(); + arm_call_pre_el_change_hook(arm_env_get_cpu(env)); + qemu_mutex_unlock_iothread(); + if (!return_to_aa64) { env->aarch64 =3D 0; /* We do a raw CPSR write because aarch64_sync_64_to_32() --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. From nobody Sat Oct 25 02:27:18 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 15212333209001017.5408602926672; Fri, 16 Mar 2018 13:48:40 -0700 (PDT) Received: from localhost ([::1]:59540 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewwHD-0002hi-1J for importer@patchew.org; Fri, 16 Mar 2018 16:48:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44195) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eww1V-0005wg-AI for qemu-devel@nongnu.org; Fri, 16 Mar 2018 16:32:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eww1R-0003NJ-Jf for qemu-devel@nongnu.org; Fri, 16 Mar 2018 16:32:21 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:56030) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eww1O-0003JS-T5; Fri, 16 Mar 2018 16:32:15 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id C7ACA60F5F; Fri, 16 Mar 2018 20:32:10 +0000 (UTC) Received: from mossypile.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: alindsay@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 6633C60F8D; Fri, 16 Mar 2018 20:32:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521232334; bh=H4BJ0JtiSDLo4BBdMiQXq3me1X+hprXnYd3d0940vl8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RUbvExjyK8uuIB8VJB+5uTWvoREr1tMr9eR5rGoSxabntj/CCXdn283Iwmio9nUAv 2E6IgZKQFMaCsryWuq/Gg4DSkM+K+dRA6GBvuQsZpcv0ZP6fdnf5T6TyhpI+T09AgK 8s1HisVoNJdOqaB117htuHkswcby18LAM9VlRG1A= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521232329; bh=H4BJ0JtiSDLo4BBdMiQXq3me1X+hprXnYd3d0940vl8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gAakCXulPwI5/b16r8iFbYsRkyuhHfyQozbLA4KU/VFdir0RGn9/2CWuZBhRv8P1b vNT8fVIOcS/fcQ+cRHCwZqsWZeHUylUtohUVHrD78vU7cRQYBoI6S4Z95DLci4DDbt t1zhvsw6uvjMkMin12iZU4plMCMvI94GoxLRLUWA= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 6633C60F8D Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alindsay@codeaurora.org From: Aaron Lindsay To: qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Wei Huang , Peter Crosthwaite Date: Fri, 16 Mar 2018 16:31:08 -0400 Message-Id: <1521232280-13089-11-git-send-email-alindsay@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> References: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.96 Subject: [Qemu-devel] [PATCH v3 10/22] target/arm: Allow EL change hooks to do IO X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Spradling , qemu-devel@nongnu.org, Digant Desai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" During code generation, surround CPSR writes and exception returns which call the EL change hooks with gen_io_start/end. The immediate need is for the PMU to access the clock and icount during EL change to support mode filtering. Signed-off-by: Aaron Lindsay --- target/arm/translate-a64.c | 2 ++ target/arm/translate.c | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 31ff047..e1ae676 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1919,7 +1919,9 @@ static void disas_uncond_b_reg(DisasContext *s, uint3= 2_t insn) unallocated_encoding(s); return; } + gen_io_start(); gen_helper_exception_return(cpu_env); + gen_io_end(); /* Must exit loop to check un-masked IRQs */ s->base.is_jmp =3D DISAS_EXIT; return; diff --git a/target/arm/translate.c b/target/arm/translate.c index ba6ab7d..fd5871e 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4536,7 +4536,9 @@ static void gen_rfe(DisasContext *s, TCGv_i32 pc, TCG= v_i32 cpsr) * appropriately depending on the new Thumb bit, so it must * be called after storing the new PC. */ + gen_io_start(); gen_helper_cpsr_write_eret(cpu_env, cpsr); + gen_io_end(); tcg_temp_free_i32(cpsr); /* Must exit loop to check un-masked IRQs */ s->base.is_jmp =3D DISAS_EXIT; @@ -9828,7 +9830,9 @@ static void disas_arm_insn(DisasContext *s, unsigned = int insn) if (exc_return) { /* Restore CPSR from SPSR. */ tmp =3D load_cpu_field(spsr); + gen_io_start(); gen_helper_cpsr_write_eret(cpu_env, tmp); + gen_io_end(); tcg_temp_free_i32(tmp); /* Must exit loop to check un-masked IRQs */ s->base.is_jmp =3D DISAS_EXIT; --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. From nobody Sat Oct 25 02:27:18 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521233512630528.2648313429789; Fri, 16 Mar 2018 13:51:52 -0700 (PDT) Received: from localhost ([::1]:59562 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewwJu-0004yK-QH for importer@patchew.org; Fri, 16 Mar 2018 16:51:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44301) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eww1Y-0005yt-E4 for qemu-devel@nongnu.org; Fri, 16 Mar 2018 16:32:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eww1X-0003UM-Kb for qemu-devel@nongnu.org; Fri, 16 Mar 2018 16:32:24 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:56094) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eww1Q-0003Kv-CT; Fri, 16 Mar 2018 16:32:16 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 2975E60591; Fri, 16 Mar 2018 20:32:11 +0000 (UTC) Received: from mossypile.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: alindsay@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id B97A360F94; Fri, 16 Mar 2018 20:32:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521232335; bh=Mei56ULqGTG+C/oz1buEngvG2VoWQjuJdwMqt+rhk5Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=l6zjIb64i0/xm1FeD2+KNVs71xvIEyAVEabv+NzJ4HnEc6Tt8CKafBdb0ItHSdXFI 5geDGJ2GIJJmGy+JLKj4F0fb5t19N2QvDGdE1R0/62gxi+6lyI0FDIWOL/bk4SL2Mp 68RITqvlPjFJaU8e+RGCdmrpvtvTRhcwVOhrnywM= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521232330; bh=Mei56ULqGTG+C/oz1buEngvG2VoWQjuJdwMqt+rhk5Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=I88OiByOZlYos5hFdMp1VbRCWT5SkacFLp49X0JrxCu/kFNE+VFoTFO1TRb781GoP T8j56YorD4kHPmF75lD+fItxA1XsqVtZKNdrNtDKRvnQGisdSygEjnaBM635ZlDGZv TWmOX2CW5NCHebwvnQKeklsVVNrB4NpSA6YFTfkk= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org B97A360F94 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alindsay@codeaurora.org From: Aaron Lindsay To: qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Wei Huang , Peter Crosthwaite Date: Fri, 16 Mar 2018 16:31:09 -0400 Message-Id: <1521232280-13089-12-git-send-email-alindsay@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> References: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.96 Subject: [Qemu-devel] [PATCH v3 11/22] target/arm: Fix bitmask for PMCCFILTR writes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Spradling , qemu-devel@nongnu.org, Digant Desai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" It was shifted to the left one bit too few. Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 50eaed7..0102357 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1123,7 +1123,7 @@ static void pmccfiltr_write(CPUARMState *env, const A= RMCPRegInfo *ri, uint64_t value) { uint64_t saved_cycles =3D pmccntr_op_start(env); - env->cp15.pmccfiltr_el0 =3D value & 0x7E000000; + env->cp15.pmccfiltr_el0 =3D value & 0xfc000000; pmccntr_op_finish(env, saved_cycles); } =20 --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. From nobody Sat Oct 25 02:27:18 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521233582629391.18692840171775; Fri, 16 Mar 2018 13:53:02 -0700 (PDT) Received: from localhost ([::1]:59577 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewwLR-0006EZ-RE for importer@patchew.org; Fri, 16 Mar 2018 16:52:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44345) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eww1Z-00060c-MP for qemu-devel@nongnu.org; Fri, 16 Mar 2018 16:32:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eww1X-0003Um-QY for qemu-devel@nongnu.org; Fri, 16 Mar 2018 16:32:25 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:56158) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eww1R-0003Mj-QZ; Fri, 16 Mar 2018 16:32:18 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 96A066055D; Fri, 16 Mar 2018 20:32:14 +0000 (UTC) Received: from mossypile.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: alindsay@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 1A91160FB1; Fri, 16 Mar 2018 20:32:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521232336; bh=0ZHlk6YlDd/LOItzoFxI6o1v1+n4NV0kN0IjqDQ1YF0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JB1a21fanLbT/fFUHntyyd3gmCDv8R5KDzcRi71OKMDHEtNEkTKkfMzgkLQJQo3p7 XDNwtpDNy1mzENb+wXy8iIW1iT0avYiZLF+soQh5O4g/dJCe1E3M/o+rW+2x3oSFkJ y4tSzU9RTTrjfyKUKUw62XvcpODOdEexw8nqhZeM= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521232332; bh=0ZHlk6YlDd/LOItzoFxI6o1v1+n4NV0kN0IjqDQ1YF0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=e9WjWsJTxFa+u/lI45Hvxv6Z9A0sRxtO1oVHPfBaGq5wMI1bQnhPGZhJgArk1vPc+ CiyEoUxr3yzGbCD14o5knJ92TuXMcnBFb6URVeWzvxkqkip8I0L99plJS8s/c8CNuO XRUC+8on8yuajFYocd+xg6rkimQQYxnAvg1AFO3k= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 1A91160FB1 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alindsay@codeaurora.org From: Aaron Lindsay To: qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Wei Huang , Peter Crosthwaite Date: Fri, 16 Mar 2018 16:31:10 -0400 Message-Id: <1521232280-13089-13-git-send-email-alindsay@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> References: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.96 Subject: [Qemu-devel] [PATCH v3 12/22] target/arm: Filter cycle counter based on PMCCFILTR_EL0 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Spradling , qemu-devel@nongnu.org, Digant Desai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The pmu_counter_filtered and pmu_op_start/finish functions are generic (as opposed to PMCCNTR-specific) to allow for the implementation of other events. Signed-off-by: Aaron Lindsay --- target/arm/cpu.c | 3 ++ target/arm/cpu.h | 37 +++++++++++++++++++---- target/arm/helper.c | 87 +++++++++++++++++++++++++++++++++++++++++++++++++= +--- 3 files changed, 116 insertions(+), 11 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index a2cb21e..b0d032c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -887,6 +887,9 @@ static void arm_cpu_realizefn(DeviceState *dev, Error *= *errp) if (!cpu->has_pmu) { unset_feature(env, ARM_FEATURE_PMU); cpu->id_aa64dfr0 &=3D ~0xf00; + } else { + arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); + arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); } =20 if (!arm_feature(env, ARM_FEATURE_EL2)) { diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b0ef727..9c3b5ef 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -458,6 +458,11 @@ typedef struct CPUARMState { * was reset. Otherwise it stores the counter value */ uint64_t c15_ccnt; + /* ccnt_cached_cycles is used to hold the last cycle count when + * c15_ccnt holds the guest-visible count instead of the delta dur= ing + * PMU operations which require this. + */ + uint64_t ccnt_cached_cycles; uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ uint64_t vpidr_el2; /* Virtualization Processor ID Register */ uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register = */ @@ -896,15 +901,35 @@ int cpu_arm_signal_handler(int host_signum, void *pin= fo, void *puc); =20 /** - * pmccntr_sync + * pmccntr_op_start/finish * @env: CPUARMState * - * Synchronises the counter in the PMCCNTR. This must always be called twi= ce, - * once before any action that might affect the timer and again afterwards. - * The function is used to swap the state of the register if required. - * This only happens when not in user mode (!CONFIG_USER_ONLY) + * Convert the counter in the PMCCNTR between its delta form (the typical = mode + * when it's enabled) and the guest-visible value. These two calls must al= ways + * surround any action which might affect the counter, and the return value + * from pmccntr_op_start must be supplied as the second argument to + * pmccntr_op_finish. + */ +uint64_t pmccntr_op_start(CPUARMState *env); +void pmccntr_op_finish(CPUARMState *env, uint64_t prev_cycles); + +/** + * pmu_op_start/finish + * @env: CPUARMState + * + * Convert all PMU counters between their delta form (the typical mode when + * they are enabled) and the guest-visible values. These two calls must + * surround any action which might affect the counters, and the return val= ue + * from pmu_op_start must be supplied as the second argument to pmu_op_fin= ish. + */ +uint64_t pmu_op_start(CPUARMState *env); +void pmu_op_finish(CPUARMState *env, uint64_t prev_cycles); + +/** + * Functions to register as EL change hooks for PMU mode filtering */ -void pmccntr_sync(CPUARMState *env); +void pmu_pre_el_change(ARMCPU *cpu, void *ignored); +void pmu_post_el_change(ARMCPU *cpu, void *ignored); =20 /* SCTLR bit meanings. Several bits have been reused in newer * versions of the architecture; in that case we define constants diff --git a/target/arm/helper.c b/target/arm/helper.c index 0102357..95b09d6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -908,6 +908,15 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { #define PMCRC 0x4 #define PMCRE 0x1 =20 +#define PMXEVTYPER_P 0x80000000 +#define PMXEVTYPER_U 0x40000000 +#define PMXEVTYPER_NSK 0x20000000 +#define PMXEVTYPER_NSU 0x10000000 +#define PMXEVTYPER_NSH 0x08000000 +#define PMXEVTYPER_M 0x04000000 +#define PMXEVTYPER_MT 0x02000000 +#define PMXEVTYPER_EVTCOUNT 0x000003ff + #define PMU_NUM_COUNTERS(env) ((env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_S= HIFT) /* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */ #define PMU_COUNTER_MASK(env) ((1 << 31) | ((1 << PMU_NUM_COUNTERS(env)) -= 1)) @@ -998,7 +1007,7 @@ static CPAccessResult pmreg_access_ccntr(CPUARMState *= env, =20 static inline bool arm_ccnt_enabled(CPUARMState *env) { - /* This does not support checking PMCCFILTR_EL0 register */ + /* Does not check PMCCFILTR_EL0, which is handled by pmu_counter_filte= red */ =20 if (!(env->cp15.c9_pmcr & PMCRE) || !(env->cp15.c9_pmcnten & (1 << 31)= )) { return false; @@ -1006,6 +1015,44 @@ static inline bool arm_ccnt_enabled(CPUARMState *env) =20 return true; } + +/* Returns true if the counter corresponding to the passed-in pmevtyper or + * pmccfiltr value is filtered using the current state */ +static inline bool pmu_counter_filtered(CPUARMState *env, uint64_t pmxevty= per) +{ + bool secure =3D arm_is_secure(env); + int el =3D arm_current_el(env); + + bool P =3D pmxevtyper & PMXEVTYPER_P; + bool U =3D pmxevtyper & PMXEVTYPER_U; + bool NSK =3D pmxevtyper & PMXEVTYPER_NSK; + bool NSU =3D pmxevtyper & PMXEVTYPER_NSU; + bool NSH =3D pmxevtyper & PMXEVTYPER_NSH; + bool M =3D pmxevtyper & PMXEVTYPER_M; + + if (el =3D=3D 1 && P) { + return true; + } else if (el =3D=3D 0 && U) { + return true; + } + + if (arm_feature(env, ARM_FEATURE_EL3)) { + if (el =3D=3D 1 && !secure && NSK !=3D P) { + return true; + } else if (el =3D=3D 0 && !secure && NSU !=3D U) { + return true; + } else if (el =3D=3D 3 && secure && M !=3D P) { + return true; + } + } + + if (arm_feature(env, ARM_FEATURE_EL2) && el =3D=3D 2 && !secure && !NS= H) { + return true; + } + + return false; +} + /* * Ensure c15_ccnt is the guest-visible count so that operations such as * enabling/disabling the counter or filtering, modifying the count itself, @@ -1023,7 +1070,8 @@ uint64_t pmccntr_op_start(CPUARMState *env) ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); #endif =20 - if (arm_ccnt_enabled(env)) { + if (arm_ccnt_enabled(env) && + !pmu_counter_filtered(env, env->cp15.pmccfiltr_el0)) { =20 uint64_t eff_cycles =3D cycles; if (env->cp15.c9_pmcr & PMCRD) { @@ -1043,7 +1091,8 @@ uint64_t pmccntr_op_start(CPUARMState *env) */ void pmccntr_op_finish(CPUARMState *env, uint64_t prev_cycles) { - if (arm_ccnt_enabled(env)) { + if (arm_ccnt_enabled(env) && + !pmu_counter_filtered(env, env->cp15.pmccfiltr_el0)) { =20 if (env->cp15.c9_pmcr & PMCRD) { /* Increment once every 64 processor clock cycles */ @@ -1054,10 +1103,30 @@ void pmccntr_op_finish(CPUARMState *env, uint64_t p= rev_cycles) } } =20 +uint64_t pmu_op_start(CPUARMState *env) +{ + return pmccntr_op_start(env); +} + +void pmu_op_finish(CPUARMState *env, uint64_t prev_cycles) +{ + pmccntr_op_finish(env, prev_cycles); +} + +void pmu_pre_el_change(ARMCPU *cpu, void *ignored) +{ + cpu->env.cp15.ccnt_cached_cycles =3D pmu_op_start(&cpu->env); +} + +void pmu_post_el_change(ARMCPU *cpu, void *ignored) +{ + pmu_op_finish(&cpu->env, cpu->env.cp15.ccnt_cached_cycles); +} + static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - uint64_t saved_cycles =3D pmccntr_op_start(env); + uint64_t saved_cycles =3D pmu_op_start(env); =20 if (value & PMCRC) { /* The counter has been reset */ @@ -1068,7 +1137,7 @@ static void pmcr_write(CPUARMState *env, const ARMCPR= egInfo *ri, env->cp15.c9_pmcr &=3D ~0x39; env->cp15.c9_pmcr |=3D (value & 0x39); =20 - pmccntr_op_finish(env, saved_cycles); + pmu_op_finish(env, saved_cycles); } =20 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) @@ -1117,6 +1186,14 @@ void pmccntr_op_finish(CPUARMState *env, uint64_t pr= ev_cycles) { } =20 +uint64_t pmu_op_start(CPUARMState *env) +{ +} + +void pmu_op_finish(CPUARMState *env, uint64_t prev_cycles) +{ +} + #endif =20 static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. 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h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YDMryC0e8oJf7moCb9zY959joZgHHsrPhDRZbGpH/OfHCVmZY36a07dfINhwbLOxO z3pgq68bnp3jsqgI6jpmbDKiQ6wB646UikOfjQ0IXCMesDTCwtlpcfsX9KzLnxKTeQ ddrIAKNAFUkBzj3ewEe+nfr0atkQpJDZJaRHFgn8= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521232333; bh=48LzR25TMpECrCpkAtlTu/zGR0jWMtcfoMzCMPW8niA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RhqFqqcw3WK600ve2IalsGneZQWDjbndLUXOmXSdYB2unq17cTGziznshe6OTQD4z TOvHcXZDw/ylV15lJHEMaNrr71poYzAV+GYGlQpMrLDkZmFJGUStUhYStMgSSjttpK LJSVsiQ7N5HVKouWKq7p8F41YykivZQZnA6c2ls8= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 707B260F94 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alindsay@codeaurora.org From: Aaron Lindsay To: qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Wei Huang , Peter Crosthwaite Date: Fri, 16 Mar 2018 16:31:11 -0400 Message-Id: <1521232280-13089-14-git-send-email-alindsay@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> References: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.96 Subject: [Qemu-devel] [PATCH v3 13/22] target/arm: Allow AArch32 access for PMCCFILTR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Spradling , qemu-devel@nongnu.org, Digant Desai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Aaron Lindsay --- target/arm/helper.c | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 95b09d6..d4f06e6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -917,6 +917,10 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { #define PMXEVTYPER_MT 0x02000000 #define PMXEVTYPER_EVTCOUNT 0x000003ff =20 +#define PMCCFILTR 0xf8000000 +#define PMCCFILTR_M PMXEVTYPER_M +#define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M) + #define PMU_NUM_COUNTERS(env) ((env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_S= HIFT) /* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */ #define PMU_COUNTER_MASK(env) ((1 << 31) | ((1 << PMU_NUM_COUNTERS(env)) -= 1)) @@ -1200,10 +1204,26 @@ static void pmccfiltr_write(CPUARMState *env, const= ARMCPRegInfo *ri, uint64_t value) { uint64_t saved_cycles =3D pmccntr_op_start(env); - env->cp15.pmccfiltr_el0 =3D value & 0xfc000000; + env->cp15.pmccfiltr_el0 =3D value & PMCCFILTR_EL0; + pmccntr_op_finish(env, saved_cycles); +} + +static void pmccfiltr_write_a32(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint64_t saved_cycles =3D pmccntr_op_start(env); + /* M is not accessible from AArch32 */ + env->cp15.pmccfiltr_el0 =3D (env->cp15.pmccfiltr_el0 & PMCCFILTR_M) | + (value & PMCCFILTR); pmccntr_op_finish(env, saved_cycles); } =20 +static uint64_t pmccfiltr_read_a32(CPUARMState *env, const ARMCPRegInfo *r= i) +{ + /* M is not visible in AArch32 */ + return env->cp15.pmccfiltr_el0 & PMCCFILTR; +} + static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -1421,6 +1441,11 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .type =3D ARM_CP_IO, .readfn =3D pmccntr_read, .writefn =3D pmccntr_write, }, #endif + { .name =3D "PMCCFILTR", .cp =3D 15, .opc1 =3D 0, .crn =3D 14, .crm = =3D 15, .opc2 =3D 7, + .writefn =3D pmccfiltr_write_a32, .readfn =3D pmccfiltr_read_a32, + .access =3D PL0_RW, .accessfn =3D pmreg_access, + .type =3D ARM_CP_ALIAS | ARM_CP_IO, + .resetvalue =3D 0, }, { .name =3D "PMCCFILTR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 15, .opc2 =3D 7, .writefn =3D pmccfiltr_write, --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. From nobody Sat Oct 25 02:27:18 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521232773328300.026993449159; Fri, 16 Mar 2018 13:39:33 -0700 (PDT) Received: from localhost ([::1]:59472 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eww8S-0003DO-Cz for importer@patchew.org; Fri, 16 Mar 2018 16:39:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44304) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eww1Y-0005z2-IB for qemu-devel@nongnu.org; Fri, 16 Mar 2018 16:32:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eww1X-0003UJ-Kj for qemu-devel@nongnu.org; Fri, 16 Mar 2018 16:32:24 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:56308) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eww1V-0003QJ-2F; Fri, 16 Mar 2018 16:32:21 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 0987F60FF4; Fri, 16 Mar 2018 20:32:15 +0000 (UTC) Received: from mossypile.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: alindsay@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id E82C460F61; Fri, 16 Mar 2018 20:32:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521232340; bh=PHnf6i8wD/cY6te2bgq1733P+y+k3iE7tmKwMegAp2M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JpWjBCz2hhA7uIXcT4xW4LlaMJT59bCkvtDvx55fTxqkMW0pIvYS7QK4PL5TqMzLD 7buVYuDI2XXglcQnGcTPj9tgTXtFTreBY4a3uyTTJre2rin3K5ezBkmqNp7vjTdKkK l8HbTLuJTKPtfZLMZFjycmz7+1l4LXy+2HmM7aBc= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521232335; bh=PHnf6i8wD/cY6te2bgq1733P+y+k3iE7tmKwMegAp2M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UxG5OZvDcVB7V/vgh1h3OsZ8sXFMLYN6cAZdJfLpNRbgBrhSPEt3IvFZ32e6FkXn3 ER0SRymAzXXB79l49BGaIgzDaoKcl3G4YPUzW/Pw+Jy0VF6nLeMUcdSIhPqzJWAyT3 lqhsFtj1UIQiJC8TuuZVfEeV1FddxmgBlnnmMSf8= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org E82C460F61 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alindsay@codeaurora.org From: Aaron Lindsay To: qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Wei Huang , Peter Crosthwaite Date: Fri, 16 Mar 2018 16:31:12 -0400 Message-Id: <1521232280-13089-15-git-send-email-alindsay@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> References: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.96 Subject: [Qemu-devel] [PATCH v3 14/22] target/arm: Make PMOVSCLR 64 bits wide X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Spradling , qemu-devel@nongnu.org, Digant Desai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is a bug fix to ensure 64-bit reads of this register don't read adjacent data. Signed-off-by: Aaron Lindsay --- target/arm/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9c3b5ef..fb2f983 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -367,7 +367,7 @@ typedef struct CPUARMState { uint32_t c9_data; uint64_t c9_pmcr; /* performance monitor control register */ uint64_t c9_pmcnten; /* perf monitor counter enables */ - uint32_t c9_pmovsr; /* perf monitor overflow status */ + uint64_t c9_pmovsr; /* perf monitor overflow status */ uint32_t c9_pmuserenr; /* perf monitor user enable */ uint64_t c9_pmselr; /* perf monitor counter selection register */ uint64_t c9_pminten; /* perf monitor interrupt enables */ --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. 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charset="utf-8" Signed-off-by: Aaron Lindsay Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu.c | 3 +++ target/arm/cpu.h | 1 + 2 files changed, 4 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index b0d032c..e544f1d 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -765,6 +765,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error *= *errp) /* Some features automatically imply others: */ if (arm_feature(env, ARM_FEATURE_V8)) { set_feature(env, ARM_FEATURE_V7); + set_feature(env, ARM_FEATURE_V7VE); set_feature(env, ARM_FEATURE_ARM_DIV); set_feature(env, ARM_FEATURE_LPAE); } @@ -1481,6 +1482,7 @@ static void cortex_a7_initfn(Object *obj) =20 cpu->dtb_compatible =3D "arm,cortex-a7"; set_feature(&cpu->env, ARM_FEATURE_V7); + set_feature(&cpu->env, ARM_FEATURE_V7VE); set_feature(&cpu->env, ARM_FEATURE_VFP4); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); @@ -1526,6 +1528,7 @@ static void cortex_a15_initfn(Object *obj) =20 cpu->dtb_compatible =3D "arm,cortex-a15"; set_feature(&cpu->env, ARM_FEATURE_V7); + set_feature(&cpu->env, ARM_FEATURE_V7VE); set_feature(&cpu->env, ARM_FEATURE_VFP4); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); diff --git a/target/arm/cpu.h b/target/arm/cpu.h index fb2f983..cc1e2fb 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1439,6 +1439,7 @@ enum arm_features { ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ ARM_FEATURE_THUMB2EE, ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ + ARM_FEATURE_V7VE, /* v7 with Virtualization Extensions */ ARM_FEATURE_V4T, ARM_FEATURE_V5, ARM_FEATURE_STRONGARM, --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. From nobody Sat Oct 25 02:27:18 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15212331767641010.8876908119851; Fri, 16 Mar 2018 13:46:16 -0700 (PDT) Received: from localhost ([::1]:59531 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewwEy-0000xG-09 for importer@patchew.org; Fri, 16 Mar 2018 16:46:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44655) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eww1k-0006Ab-RU for qemu-devel@nongnu.org; Fri, 16 Mar 2018 16:32:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eww1j-0003lj-SZ for qemu-devel@nongnu.org; Fri, 16 Mar 2018 16:32:36 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:56608) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eww1b-0003ZA-OP; Fri, 16 Mar 2018 16:32:28 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 6A13360C54; Fri, 16 Mar 2018 20:32:19 +0000 (UTC) Received: from mossypile.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: alindsay@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id B06CA60F61; Fri, 16 Mar 2018 20:32:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521232346; bh=eG1gJdVM0L+S3BQp9pYDN7H+pP36YyBh7KdF2OSGB2Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gQgJUgFp7c+RphSMQR61YiCuuYMu+PpDW9RPXlSZ52WbLOsf4ZMTDmZ7W5AYNx1Il CvB375GcXWVwlYVkja+aeHxqhGJ2TTnfyMHaG+/OqFfug36+kxkCHlma54wIq5BKyC o2bQP1FGw3cXH2G44fNZPAFcWP4+19ThqpocfPks= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521232337; bh=eG1gJdVM0L+S3BQp9pYDN7H+pP36YyBh7KdF2OSGB2Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GFB6/60+mFwpeipSOYAerrn3/pGcxYW+6/dkQRltOP+Z+PzzukFVfm/AKVxQ9d5Dn ANF/Lx8IXq5LMsincQrxBOMmIzFsDMGrSSx5VzgRWOnPgEKpee0fMTPwbr+oeGSED1 WIng1rpSXcFhk2S4pVauhpAnbGo7PoWRC9zsoQ1M= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org B06CA60F61 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alindsay@codeaurora.org From: Aaron Lindsay To: qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Wei Huang , Peter Crosthwaite Date: Fri, 16 Mar 2018 16:31:14 -0400 Message-Id: <1521232280-13089-17-git-send-email-alindsay@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> References: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.96 Subject: [Qemu-devel] [PATCH v3 16/22] target/arm: Implement PMOVSSET X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Spradling , qemu-devel@nongnu.org, Digant Desai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Adding an array for v7VE+ CP registers was necessary so that PMOVSSET wasn't defined for all v7 processors. Signed-off-by: Aaron Lindsay --- target/arm/helper.c | 32 +++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index d4f06e6..f5e800e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1241,9 +1241,17 @@ static void pmcntenclr_write(CPUARMState *env, const= ARMCPRegInfo *ri, static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { + value &=3D PMU_COUNTER_MASK(env); env->cp15.c9_pmovsr &=3D ~value; } =20 +static void pmovsset_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + value &=3D PMU_COUNTER_MASK(env); + env->cp15.c9_pmovsr |=3D value; +} + static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -1406,7 +1414,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcnten), .writefn =3D pmcntenclr_write }, { .name =3D "PMOVSR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 3, - .access =3D PL0_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_p= movsr), + .access =3D PL0_RW, .fieldoffset =3D offsetoflow32(CPUARMState, cp15= .c9_pmovsr), .accessfn =3D pmreg_access, .writefn =3D pmovsr_write, .raw_writefn =3D raw_write }, @@ -1592,6 +1600,25 @@ static const ARMCPRegInfo v7mp_cp_reginfo[] =3D { REGINFO_SENTINEL }; =20 +static const ARMCPRegInfo v7ve_cp_reginfo[] =3D { + /* Performance monitor registers which are not implemented in v7 before + * v7ve: + */ + { .name =3D "PMOVSSET", .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D = 14, .opc2 =3D 3, + .access =3D PL0_RW, .accessfn =3D pmreg_access, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmovsr), + .writefn =3D pmovsset_write, + .raw_writefn =3D raw_write }, + { .name =3D "PMOVSSET_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 14, .opc2 =3D 3, + .access =3D PL0_RW, .accessfn =3D pmreg_access, + .type =3D ARM_CP_ALIAS, + .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmovsr), + .writefn =3D pmovsset_write, + .raw_writefn =3D raw_write }, + REGINFO_SENTINEL +}; + static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -4943,6 +4970,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) !arm_feature(env, ARM_FEATURE_PMSA)) { define_arm_cp_regs(cpu, v7mp_cp_reginfo); } + if (arm_feature(env, ARM_FEATURE_V7VE)) { + define_arm_cp_regs(cpu, v7ve_cp_reginfo); + } if (arm_feature(env, ARM_FEATURE_V7)) { /* v7 performance monitor control register: same implementor * field as main ID register, and we implement only the cycle --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. 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charset="utf-8" Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell --- target/arm/helper.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index f5e800e..2073d56 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1009,17 +1009,22 @@ static CPAccessResult pmreg_access_ccntr(CPUARMStat= e *env, return pmreg_access(env, ri, isread); } =20 -static inline bool arm_ccnt_enabled(CPUARMState *env) +static inline bool pmu_counter_enabled(CPUARMState *env, uint8_t counter) { /* Does not check PMCCFILTR_EL0, which is handled by pmu_counter_filte= red */ - - if (!(env->cp15.c9_pmcr & PMCRE) || !(env->cp15.c9_pmcnten & (1 << 31)= )) { + if (!(env->cp15.c9_pmcr & PMCRE) || + !(env->cp15.c9_pmcnten & (1 << counter))) { return false; } =20 return true; } =20 +static inline bool arm_ccnt_enabled(CPUARMState *env) +{ + return pmu_counter_enabled(env, 31); +} + /* Returns true if the counter corresponding to the passed-in pmevtyper or * pmccfiltr value is filtered using the current state */ static inline bool pmu_counter_filtered(CPUARMState *env, uint64_t pmxevty= per) --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. From nobody Sat Oct 25 02:27:18 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521233101368583.24382655628; Fri, 16 Mar 2018 13:45:01 -0700 (PDT) Received: from localhost ([::1]:59520 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewwDe-0008Cm-Ji for importer@patchew.org; Fri, 16 Mar 2018 16:44:54 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44527) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eww1g-00068h-Ha for qemu-devel@nongnu.org; Fri, 16 Mar 2018 16:32:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eww1f-0003ew-Dh for qemu-devel@nongnu.org; Fri, 16 Mar 2018 16:32:32 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:56492) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eww1Z-0003Vf-6v; Fri, 16 Mar 2018 16:32:25 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id E4C9F60FF0; Fri, 16 Mar 2018 20:32:21 +0000 (UTC) Received: from mossypile.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: alindsay@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 9DE33607A2; Fri, 16 Mar 2018 20:32:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521232344; bh=yzoqbs4P5Iex9Ul3iVM12jHg/u0/AhPoLIV/ZWAuxic=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BwNiXTN0bCsoqBnIxVkzJZSAKHFMHnTe/faaxGHciRFHUZcRk5IWL2KXLZ7IiLHtO oYgww4y/fxb1XR0GrPSUJUXI6G/Ae9/NClOkYY+euVbmh2wnYpywpLpmgSnSdnP1ba w6inr5VC95iGbQVXuR49crZ5KRQWp+3MALtOk6hA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521232340; bh=yzoqbs4P5Iex9Ul3iVM12jHg/u0/AhPoLIV/ZWAuxic=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=m+OWEsflL6/xK7AcOWqFvBi8I/5Zlst6Au/4joPOdXzz/wOVmg7De60JAT0UL99y6 4o1P8YmOXNaqk0biGYegmNpeiaiHIY7ZsuT7FW+NetmMMJGvzGdSklHF61sC2Qv/Ob I/Tu9QcC+3FnKn8lPbcpw2GrQ7qVCu9M/qCOw1K4= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 9DE33607A2 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alindsay@codeaurora.org From: Aaron Lindsay To: qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Wei Huang , Peter Crosthwaite Date: Fri, 16 Mar 2018 16:31:16 -0400 Message-Id: <1521232280-13089-19-git-send-email-alindsay@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> References: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.96 Subject: [Qemu-devel] [PATCH v3 18/22] target/arm: Add array for supported PMU events, generate PMCEID[01] X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Spradling , qemu-devel@nongnu.org, Digant Desai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This commit doesn't add any supported events, but provides the framework for adding them. We store the pm_event structs in a simple array, and provide the mapping from the event numbers to array indexes in the supported_event_map array. Signed-off-by: Aaron Lindsay --- target/arm/cpu.c | 4 ++++ target/arm/cpu.h | 10 ++++++++++ target/arm/helper.c | 37 +++++++++++++++++++++++++++++++++++++ 3 files changed, 51 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index e544f1d..69d6a80 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -889,6 +889,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Error = **errp) unset_feature(env, ARM_FEATURE_PMU); cpu->id_aa64dfr0 &=3D ~0xf00; } else { + uint64_t pmceid =3D get_pmceid(&cpu->env); + cpu->pmceid0 =3D pmceid & 0xffffffff; + cpu->pmceid1 =3D (pmceid >> 32) & 0xffffffff; + arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); } diff --git a/target/arm/cpu.h b/target/arm/cpu.h index cc1e2fb..19f005d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -931,6 +931,16 @@ void pmu_op_finish(CPUARMState *env, uint64_t prev_cyc= les); void pmu_pre_el_change(ARMCPU *cpu, void *ignored); void pmu_post_el_change(ARMCPU *cpu, void *ignored); =20 +/* + * get_pmceid + * @env: CPUARMState + * + * Return the PMCEID[01] register values corresponding to the counters whi= ch + * are supported given the current configuration (0 is low 32, 1 is high 32 + * bits) + */ +uint64_t get_pmceid(CPUARMState *env); + /* SCTLR bit meanings. Several bits have been reused in newer * versions of the architecture; in that case we define constants * for both old and new bit meanings. Code which tests against those diff --git a/target/arm/helper.c b/target/arm/helper.c index 2073d56..6a4f900 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -925,6 +925,43 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { /* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */ #define PMU_COUNTER_MASK(env) ((1 << 31) | ((1 << PMU_NUM_COUNTERS(env)) -= 1)) =20 +typedef struct pm_event { + uint16_t number; /* PMEVTYPER.evtCount is 10 bits wide */ + /* If the event is supported on this CPU (used to generate PMCEID[01])= */ + bool (*supported)(CPUARMState *); + /* Retrieve the current count of the underlying event. The programmed + * counters hold a difference from the return value from this function= */ + uint64_t (*get_count)(CPUARMState *); +} pm_event; + +#define SUPPORTED_EVENT_SENTINEL UINT16_MAX +static const pm_event pm_events[] =3D { + { .number =3D SUPPORTED_EVENT_SENTINEL } +}; +static uint16_t supported_event_map[0x3f]; + +/* + * Called upon initialization to build PMCEID0 (low 32 bits) and PMCEID1 (= high + * 32). We also use it to build a map of ARM event numbers to indices in + * our pm_events array. + */ +uint64_t get_pmceid(CPUARMState *env) +{ + uint64_t pmceid =3D 0; + unsigned int i =3D 0; + while (pm_events[i].number !=3D SUPPORTED_EVENT_SENTINEL) { + const pm_event *cnt =3D &pm_events[i]; + if (cnt->number < 0x3f && cnt->supported(env)) { + pmceid |=3D (1 << cnt->number); + supported_event_map[cnt->number] =3D i; + } else { + supported_event_map[cnt->number] =3D SUPPORTED_EVENT_SENTINEL; + } + i++; + } + return pmceid; +} + static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *r= i, bool isread) { --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. From nobody Sat Oct 25 02:27:18 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521233399265144.62986954143423; Fri, 16 Mar 2018 13:49:59 -0700 (PDT) Received: from localhost ([::1]:59551 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewwIY-0003rr-F4 for importer@patchew.org; Fri, 16 Mar 2018 16:49:58 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44793) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eww1r-0006Gb-CR for qemu-devel@nongnu.org; Fri, 16 Mar 2018 16:32:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eww1p-0003sC-Dk for qemu-devel@nongnu.org; Fri, 16 Mar 2018 16:32:43 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:56880) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eww1i-0003ip-Vl; Fri, 16 Mar 2018 16:32:35 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id D064F60F6E; Fri, 16 Mar 2018 20:32:23 +0000 (UTC) Received: from mossypile.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: alindsay@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 1BBE960FAA; Fri, 16 Mar 2018 20:32:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521232354; bh=bDOC/lX/98tdhEA9hw6VJ3HJJAPQSysJ6XMIwyMzcho=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=L7W9+iEGiLXeZupZLyTiWyjiQ94mQdTLkGBj9A6ghpa3HmONzwswC6KiG8CnsLVeI BrrwyCCp7oEuGpfjCvsdu/5u3mAy8aYy4/SjKkPus2qFQcT8C9D/Sfs6YnQmtM1sUP w9GTs7ocG6UQEH1pq+hi6Yn72xN98Fyjf18yWKaU= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521232342; bh=bDOC/lX/98tdhEA9hw6VJ3HJJAPQSysJ6XMIwyMzcho=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RFtqw9F76pedz7J2PivrVNuJ7M+qswcZBgGbc7j5GZX+WMOgAaX8frqZ8TgE0mVW6 HwtLybUaCkU9Xw7Cn62YaW6KnEnjZl3FS5UbXPrLjfhRveoDfyI3S2J/XmMsr+Bi/T sVxKva2vQqI5zEg4nv751DlakKec3mWzG1ha1jdw= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 1BBE960FAA Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alindsay@codeaurora.org From: Aaron Lindsay To: qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Wei Huang , Peter Crosthwaite Date: Fri, 16 Mar 2018 16:31:17 -0400 Message-Id: <1521232280-13089-20-git-send-email-alindsay@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> References: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.96 Subject: [Qemu-devel] [PATCH v3 19/22] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Spradling , qemu-devel@nongnu.org, Digant Desai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add arrays to hold the registers, the definitions themselves, access functions, and add logic to reset counters when PMCR.P is set. Signed-off-by: Aaron Lindsay --- target/arm/cpu.h | 7 +- target/arm/helper.c | 219 ++++++++++++++++++++++++++++++++++++++++++++++++= ---- 2 files changed, 207 insertions(+), 19 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 19f005d..7a74966 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -454,8 +454,9 @@ typedef struct CPUARMState { uint64_t oslsr_el1; /* OS Lock Status */ uint64_t mdcr_el2; uint64_t mdcr_el3; - /* If the counter is enabled, this stores the last time the counter - * was reset. Otherwise it stores the counter value + /* If the pmccntr and pmevcntr counters are enabled, they store the + * offset the last time the counter was reset. Otherwise they stor= e the + * counter value. */ uint64_t c15_ccnt; /* ccnt_cached_cycles is used to hold the last cycle count when @@ -463,6 +464,8 @@ typedef struct CPUARMState { * PMU operations which require this. */ uint64_t ccnt_cached_cycles; + uint64_t c14_pmevcntr[31]; + uint64_t c14_pmevtyper[31]; uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ uint64_t vpidr_el2; /* Virtualization Processor ID Register */ uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register = */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 6a4f900..2fa8308 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -906,6 +906,7 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { #define PMCRN_SHIFT 11 #define PMCRD 0x8 #define PMCRC 0x4 +#define PMCRP 0x2 #define PMCRE 0x1 =20 #define PMXEVTYPER_P 0x80000000 @@ -931,7 +932,7 @@ typedef struct pm_event { bool (*supported)(CPUARMState *); /* Retrieve the current count of the underlying event. The programmed * counters hold a difference from the return value from this function= */ - uint64_t (*get_count)(CPUARMState *); + uint64_t (*get_count)(CPUARMState *, uint64_t cycles); } pm_event; =20 #define SUPPORTED_EVENT_SENTINEL UINT16_MAX @@ -1054,6 +1055,21 @@ static inline bool pmu_counter_enabled(CPUARMState *= env, uint8_t counter) return false; } =20 + if (counter !=3D 31) { + /* If not checking PMCCNTR, ensure the counter is setup to an even= t we + * support */ + uint16_t event =3D env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_E= VTCOUNT; + if (event > 0x3f) { + return false; /* We only support common architectural and + microarchitectural events */ + } + + uint16_t event_idx =3D supported_event_map[event]; + if (event_idx =3D=3D SUPPORTED_EVENT_SENTINEL) { + return false; + } + } + return true; } =20 @@ -1149,14 +1165,37 @@ void pmccntr_op_finish(CPUARMState *env, uint64_t p= rev_cycles) } } =20 +static void pmu_sync_counter(CPUARMState *env, uint8_t counter, uint64_t c= ycles) +{ + if (pmu_counter_enabled(env, counter) && + !pmu_counter_filtered(env, env->cp15.c14_pmevtyper[counter])) { + + uint16_t event =3D env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_E= VTCOUNT; + uint16_t event_idx =3D supported_event_map[event]; + + uint64_t count =3D pm_events[event_idx].get_count(env, cycles); + env->cp15.c14_pmevcntr[counter] =3D + count - env->cp15.c14_pmevcntr[counter]; + } +} + uint64_t pmu_op_start(CPUARMState *env) { - return pmccntr_op_start(env); + uint64_t saved_cycles =3D pmccntr_op_start(env); + unsigned int i; + for (i =3D 0; i < PMU_NUM_COUNTERS(env); i++) { + pmu_sync_counter(env, i, saved_cycles); + } + return saved_cycles; } =20 void pmu_op_finish(CPUARMState *env, uint64_t prev_cycles) { pmccntr_op_finish(env, prev_cycles); + unsigned int i; + for (i =3D 0; i < PMU_NUM_COUNTERS(env); i++) { + pmu_sync_counter(env, i, prev_cycles); + } } =20 void pmu_pre_el_change(ARMCPU *cpu, void *ignored) @@ -1179,6 +1218,13 @@ static void pmcr_write(CPUARMState *env, const ARMCP= RegInfo *ri, env->cp15.c15_ccnt =3D 0; } =20 + if (value & PMCRP) { + unsigned int i; + for (i =3D 0; i < PMU_NUM_COUNTERS(env); i++) { + env->cp15.c14_pmevcntr[i] =3D 0; + } + } + /* only the DP, X, D and E bits are writable */ env->cp15.c9_pmcr &=3D ~0x39; env->cp15.c9_pmcr |=3D (value & 0x39); @@ -1294,30 +1340,127 @@ static void pmovsset_write(CPUARMState *env, const= ARMCPRegInfo *ri, env->cp15.c9_pmovsr |=3D value; } =20 -static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) +static void pmevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value, const uint8_t counter) { + if (counter =3D=3D 0x1f) { + pmccfiltr_write(env, ri, value); + } else if (counter < PMU_NUM_COUNTERS(env)) { + uint64_t cycles =3D 0; +#ifndef CONFIG_USER_ONLY + cycles =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); +#endif + pmu_sync_counter(env, counter, cycles); + env->cp15.c14_pmevtyper[counter] =3D value & 0xfe0003ff; + pmu_sync_counter(env, counter, cycles); + } /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when * PMSELR value is equal to or greater than the number of implemented * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI. */ - if (env->cp15.c9_pmselr =3D=3D 0x1f) { - pmccfiltr_write(env, ri, value); +} + +static uint64_t pmevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri, + const uint8_t counter) +{ + if (counter =3D=3D 0x1f) { + return env->cp15.pmccfiltr_el0; + } else if (counter < PMU_NUM_COUNTERS(env)) { + return env->cp15.c14_pmevtyper[counter]; + } else { + /* We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER + * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write(). + */ + return 0; } } =20 +static void pmevtyper_writefn(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); + pmevtyper_write(env, ri, value, counter); +} + +static uint64_t pmevtyper_readfn(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); + return pmevtyper_read(env, ri, counter); +} + +static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + pmevtyper_write(env, ri, value, env->cp15.c9_pmselr & 31); +} + static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri) { - /* We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER - * are CONSTRAINED UNPREDICTABLE. See comments in pmxevtyper_write(). - */ - if (env->cp15.c9_pmselr =3D=3D 0x1f) { - return env->cp15.pmccfiltr_el0; + return pmevtyper_read(env, ri, env->cp15.c9_pmselr & 31); +} + +static void pmevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value, uint8_t counter) +{ + if (counter < PMU_NUM_COUNTERS(env)) { + uint64_t cycles =3D 0; +#ifndef CONFIG_USER_ONLY + cycles =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); +#endif + env->cp15.c14_pmevcntr[counter] =3D value; + pmu_sync_counter(env, counter, cycles); + } + /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR + * are CONSTRAINED UNPREDICTABLE. */ +} + +static uint64_t pmevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri, + uint8_t counter) +{ + if (counter < PMU_NUM_COUNTERS(env)) { + uint64_t ret; + uint64_t cycles =3D 0; +#ifndef CONFIG_USER_ONLY + cycles =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); +#endif + pmu_sync_counter(env, counter, cycles); + ret =3D env->cp15.c14_pmevcntr[counter]; + pmu_sync_counter(env, counter, cycles); + return ret; } else { + /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR + * are CONSTRAINED UNPREDICTABLE. */ return 0; } } =20 +static void pmevcntr_writefn(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); + pmevcntr_write(env, ri, value, counter); +} + +static uint64_t pmevcntr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); + return pmevcntr_read(env, ri, counter); +} + +static void pmxevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + pmevcntr_write(env, ri, value, env->cp15.c9_pmselr & 31); +} + +static uint64_t pmxevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return pmevcntr_read(env, ri, env->cp15.c9_pmselr & 31); +} + static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -1504,16 +1647,23 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.pmccfiltr_el0), .resetvalue =3D 0, }, { .name =3D "PMXEVTYPER", .cp =3D 15, .crn =3D 9, .crm =3D 13, .opc1 = =3D 0, .opc2 =3D 1, - .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW, .accessfn =3D pmreg_acc= ess, + .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, + .accessfn =3D pmreg_access, .writefn =3D pmxevtyper_write, .readfn =3D pmxevtyper_read }, { .name =3D "PMXEVTYPER_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 13, .opc2 =3D 1, - .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW, .accessfn =3D pmreg_acc= ess, + .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, + .accessfn =3D pmreg_access, .writefn =3D pmxevtyper_write, .readfn =3D pmxevtyper_read }, - /* Unimplemented, RAZ/WI. */ { .name =3D "PMXEVCNTR", .cp =3D 15, .crn =3D 9, .crm =3D 13, .opc1 = =3D 0, .opc2 =3D 2, - .access =3D PL0_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0, - .accessfn =3D pmreg_access_xevcntr }, + .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, + .accessfn =3D pmreg_access_xevcntr, + .writefn =3D pmxevcntr_write, .readfn =3D pmxevcntr_read }, + { .name =3D "PMXEVCNTR_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 13, .opc2 =3D 2, + .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, + .accessfn =3D pmreg_access_xevcntr, + .writefn =3D pmxevcntr_write, .readfn =3D pmxevcntr_read }, { .name =3D "PMUSERENR", .cp =3D 15, .crn =3D 9, .crm =3D 14, .opc1 = =3D 0, .opc2 =3D 0, .access =3D PL0_R | PL1_RW, .accessfn =3D access_tpm, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmuserenr), @@ -4204,7 +4354,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { #endif /* The only field of MDCR_EL2 that has a defined architectural reset v= alue * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but= we - * don't impelment any PMU event counters, so using zero as a reset + * don't implement any PMU event counters, so using zero as a reset * value for MDCR_EL2 is okay */ { .name =3D "MDCR_EL2", .state =3D ARM_CP_STATE_BOTH, @@ -5016,6 +5166,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, v7ve_cp_reginfo); } if (arm_feature(env, ARM_FEATURE_V7)) { + unsigned int i; /* v7 performance monitor control register: same implementor * field as main ID register, and we implement only the cycle * count register. @@ -5040,6 +5191,40 @@ void register_cp_regs_for_features(ARMCPU *cpu) }; define_one_arm_cp_reg(cpu, &pmcr); define_one_arm_cp_reg(cpu, &pmcr64); + for (i =3D 0; i < 31; i++) { + char *pmevcntr_name =3D g_strdup_printf("PMEVCNTR%d", i); + char *pmevcntr_el0_name =3D g_strdup_printf("PMEVCNTR%d_EL0", = i); + char *pmevtyper_name =3D g_strdup_printf("PMEVTYPER%d", i); + char *pmevtyper_el0_name =3D g_strdup_printf("PMEVTYPER%d_EL0"= , i); + ARMCPRegInfo pmev_regs[] =3D { + { .name =3D pmevcntr_name, .cp =3D 15, .crn =3D 15, + .crm =3D 8 | (3 & (i >> 3)), .opc1 =3D 0, .opc2 =3D i & = 7, + .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, + .readfn =3D pmevcntr_readfn, .writefn =3D pmevcntr_write= fn, + .accessfn =3D pmreg_access }, + { .name =3D pmevcntr_el0_name, .state =3D ARM_CP_STATE_AA6= 4, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 15, .crm =3D 8 | (3 &= (i >> 3)), + .opc2 =3D i & 7, .access =3D PL0_RW, .accessfn =3D pmreg= _access, + .type =3D ARM_CP_NO_RAW | ARM_CP_IO, + .readfn =3D pmevcntr_readfn, .writefn =3D pmevcntr_write= fn }, + { .name =3D pmevtyper_name, .cp =3D 15, .crn =3D 15, + .crm =3D 12 | (3 & (i >> 3)), .opc1 =3D 0, .opc2 =3D i &= 7, + .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, + .readfn =3D pmevtyper_readfn, .writefn =3D pmevtyper_wri= tefn, + .accessfn =3D pmreg_access }, + { .name =3D pmevtyper_el0_name, .state =3D ARM_CP_STATE_AA= 64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 15, .crm =3D 12 | (3 = & (i >> 3)), + .opc2 =3D i & 7, .access =3D PL0_RW, .accessfn =3D pmreg= _access, + .type =3D ARM_CP_NO_RAW | ARM_CP_IO, + .readfn =3D pmevtyper_readfn, .writefn =3D pmevtyper_wri= tefn }, + REGINFO_SENTINEL + }; + define_arm_cp_regs(cpu, pmev_regs); + g_free(pmevcntr_name); + g_free(pmevcntr_el0_name); + g_free(pmevtyper_name); + g_free(pmevtyper_el0_name); + } #endif ARMCPRegInfo clidr =3D { .name =3D "CLIDR", .state =3D ARM_CP_STATE_BOTH, --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. From nobody Sat Oct 25 02:27:18 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521233727863216.68439786672172; Fri, 16 Mar 2018 13:55:27 -0700 (PDT) Received: from localhost ([::1]:59590 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewwNq-0007gy-N4 for importer@patchew.org; Fri, 16 Mar 2018 16:55:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44694) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eww1l-0006Bw-R3 for qemu-devel@nongnu.org; Fri, 16 Mar 2018 16:32:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eww1k-0003mC-Ai for qemu-devel@nongnu.org; Fri, 16 Mar 2018 16:32:37 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:56804) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eww1g-0003fs-R4; Fri, 16 Mar 2018 16:32:33 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 6976860C66; Fri, 16 Mar 2018 20:32:24 +0000 (UTC) Received: from mossypile.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: alindsay@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 6C64860FED; Fri, 16 Mar 2018 20:32:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521232351; bh=hD2JAL+smX2M7pgyuu36QrwMtC3z+hPAeONI/PxEw7U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=M/YJFfkRizn++NBZA7mxxf84TXHc7CJ97rkfiEGovO540TvcI5SNb27P8/BYEh8nL 1V16q6nmGXQCyMt3VeQJr7nC375+uqSXuiECUrPq6O46oXIUVNEWdsL+ybDi2w08Vk p/xR1LDAUdOqt6W3BfZeSh91EDcAyYxXHL7HI7go= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521232343; bh=hD2JAL+smX2M7pgyuu36QrwMtC3z+hPAeONI/PxEw7U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TqgqGHkxlsiPquEdHzQyN6aexi9IARSqFzGzgDPJXZavnz/g/EpKOK0rgdywGXlLb 5RyhvDLz0YuF13MHfvt+wkahGOcro1GdfuvCU8Cr2hhThsykvW/u5k8rElX0Rst7MV OK4pa/+HScmtNuPaIZtPFcCmYL50c25MUWHjPnSo= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 6C64860FED Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alindsay@codeaurora.org From: Aaron Lindsay To: qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Wei Huang , Peter Crosthwaite Date: Fri, 16 Mar 2018 16:31:18 -0400 Message-Id: <1521232280-13089-21-git-send-email-alindsay@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> References: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.96 Subject: [Qemu-devel] [PATCH v3 20/22] target/arm: PMU: Add instruction and cycle events X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Spradling , qemu-devel@nongnu.org, Digant Desai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The instruction event is only enabled when icount is used, cycles are always supported. Always defining get_cycle_count (but altering its behavior depending on CONFIG_USER_ONLY) allows us to remove some CONFIG_USER_ONLY #defines throughout the rest of the code. Signed-off-by: Aaron Lindsay Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/helper.c | 99 ++++++++++++++++++++++++++++---------------------= ---- 1 file changed, 52 insertions(+), 47 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 2fa8308..679897a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -15,6 +15,7 @@ #include "arm_ldst.h" #include /* For crc32 */ #include "exec/semihost.h" +#include "sysemu/cpus.h" #include "sysemu/kvm.h" #include "fpu/softfloat.h" =20 @@ -935,8 +936,54 @@ typedef struct pm_event { uint64_t (*get_count)(CPUARMState *, uint64_t cycles); } pm_event; =20 +/* + * Return the underlying cycle count for the PMU cycle counters. If we're = in + * usermode, simply return 0. + */ +static uint64_t get_cycle_count(CPUARMState *env) +{ +#ifndef CONFIG_USER_ONLY + return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); +#else + return 0; +#endif +} + +static bool event_always_supported(CPUARMState *env) +{ + return true; +} + +#ifndef CONFIG_USER_ONLY +static uint64_t cycles_get_count(CPUARMState *env, uint64_t cycles) +{ + return cycles; +} + +static bool instructions_supported(CPUARMState *env) +{ + return use_icount =3D=3D 1 /* Precise instruction counting */; +} + +static uint64_t instructions_get_count(CPUARMState *env, uint64_t cycles) +{ + return (uint64_t)cpu_get_icount_raw(); +} +#endif + #define SUPPORTED_EVENT_SENTINEL UINT16_MAX static const pm_event pm_events[] =3D { +#ifndef CONFIG_USER_ONLY + { .number =3D 0x008, /* INST_RETIRED */ + .supported =3D instructions_supported, + .get_count =3D instructions_get_count + }, + { .number =3D 0x011, /* CPU_CYCLES */ + .supported =3D event_always_supported, + .get_count =3D cycles_get_count + }, +#endif { .number =3D SUPPORTED_EVENT_SENTINEL } }; static uint16_t supported_event_map[0x3f]; @@ -1016,8 +1063,6 @@ static CPAccessResult pmreg_access_swinc(CPUARMState = *env, return pmreg_access(env, ri, isread); } =20 -#ifndef CONFIG_USER_ONLY - static CPAccessResult pmreg_access_selr(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) @@ -1126,11 +1171,7 @@ static inline bool pmu_counter_filtered(CPUARMState = *env, uint64_t pmxevtyper) */ uint64_t pmccntr_op_start(CPUARMState *env) { - uint64_t cycles =3D 0; -#ifndef CONFIG_USER_ONLY - cycles =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), - ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); -#endif + uint64_t cycles =3D get_cycle_count(env); =20 if (arm_ccnt_enabled(env) && !pmu_counter_filtered(env, env->cp15.pmccfiltr_el0)) { @@ -1268,26 +1309,6 @@ static void pmccntr_write32(CPUARMState *env, const = ARMCPRegInfo *ri, pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value)); } =20 -#else /* CONFIG_USER_ONLY */ - -uint64_t pmccntr_op_start(CPUARMState *env) -{ -} - -void pmccntr_op_finish(CPUARMState *env, uint64_t prev_cycles) -{ -} - -uint64_t pmu_op_start(CPUARMState *env) -{ -} - -void pmu_op_finish(CPUARMState *env, uint64_t prev_cycles) -{ -} - -#endif - static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -1346,11 +1367,7 @@ static void pmevtyper_write(CPUARMState *env, const = ARMCPRegInfo *ri, if (counter =3D=3D 0x1f) { pmccfiltr_write(env, ri, value); } else if (counter < PMU_NUM_COUNTERS(env)) { - uint64_t cycles =3D 0; -#ifndef CONFIG_USER_ONLY - cycles =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), - ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); -#endif + uint64_t cycles =3D get_cycle_count(env); pmu_sync_counter(env, counter, cycles); env->cp15.c14_pmevtyper[counter] =3D value & 0xfe0003ff; pmu_sync_counter(env, counter, cycles); @@ -1404,11 +1421,7 @@ static void pmevcntr_write(CPUARMState *env, const A= RMCPRegInfo *ri, uint64_t value, uint8_t counter) { if (counter < PMU_NUM_COUNTERS(env)) { - uint64_t cycles =3D 0; -#ifndef CONFIG_USER_ONLY - cycles =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), - ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); -#endif + uint64_t cycles =3D get_cycle_count(env); env->cp15.c14_pmevcntr[counter] =3D value; pmu_sync_counter(env, counter, cycles); } @@ -1420,12 +1433,8 @@ static uint64_t pmevcntr_read(CPUARMState *env, cons= t ARMCPRegInfo *ri, uint8_t counter) { if (counter < PMU_NUM_COUNTERS(env)) { - uint64_t ret; - uint64_t cycles =3D 0; -#ifndef CONFIG_USER_ONLY - cycles =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), - ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); -#endif + uint64_t ret, cycles; + cycles =3D get_cycle_count(env); pmu_sync_counter(env, counter, cycles); ret =3D env->cp15.c14_pmevcntr[counter]; pmu_sync_counter(env, counter, cycles); @@ -1613,7 +1622,6 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { /* Unimplemented so WI. */ { .name =3D "PMSWINC", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D = 0, .opc2 =3D 4, .access =3D PL0_W, .accessfn =3D pmreg_access_swinc, .type =3D ARM_C= P_NOP }, -#ifndef CONFIG_USER_ONLY { .name =3D "PMSELR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 5, .access =3D PL0_RW, .type =3D ARM_CP_ALIAS, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmselr), @@ -1633,7 +1641,6 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .access =3D PL0_RW, .accessfn =3D pmreg_access_ccntr, .type =3D ARM_CP_IO, .readfn =3D pmccntr_read, .writefn =3D pmccntr_write, }, -#endif { .name =3D "PMCCFILTR", .cp =3D 15, .opc1 =3D 0, .crn =3D 14, .crm = =3D 15, .opc2 =3D 7, .writefn =3D pmccfiltr_write_a32, .readfn =3D pmccfiltr_read_a32, .access =3D PL0_RW, .accessfn =3D pmreg_access, @@ -5171,7 +5178,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) * field as main ID register, and we implement only the cycle * count register. */ -#ifndef CONFIG_USER_ONLY ARMCPRegInfo pmcr =3D { .name =3D "PMCR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 = =3D 0, .opc2 =3D 0, .access =3D PL0_RW, @@ -5225,7 +5231,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) g_free(pmevtyper_name); g_free(pmevtyper_el0_name); } -#endif ARMCPRegInfo clidr =3D { .name =3D "CLIDR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 1, .opc2 =3D 1, --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. From nobody Sat Oct 25 02:27:18 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521233329475730.9489080114048; Fri, 16 Mar 2018 13:48:49 -0700 (PDT) Received: from localhost ([::1]:59541 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewwHH-0002nc-Jo for importer@patchew.org; Fri, 16 Mar 2018 16:48:39 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44677) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eww1l-0006BB-Cw for qemu-devel@nongnu.org; Fri, 16 Mar 2018 16:32:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eww1k-0003mW-IP for qemu-devel@nongnu.org; Fri, 16 Mar 2018 16:32:37 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:56852) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eww1i-0003hn-6m; Fri, 16 Mar 2018 16:32:34 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 0DCDF60C54; Fri, 16 Mar 2018 20:32:26 +0000 (UTC) Received: from mossypile.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: alindsay@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 0122660FB1; Fri, 16 Mar 2018 20:32:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521232353; bh=MU0rboX1g0yXQDqkflH/sfVouCJZviPyuhiDzS9Sde8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GelHzmf8CCSBtDEpJUGC925+kMpbPVJOrgqi+DpLhkSm1OSg0ueJTIF5pAgBA5oWe Hprf0zn9HufnGpl7O18PSAsIOENoAbuSruqNEeVkAEZAELS07ARDn4GjrHZ1tbhSK+ 44G3hjdybpRXtOQaBK8AyMUET8AVLw0b5HEvyusE= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521232345; bh=MU0rboX1g0yXQDqkflH/sfVouCJZviPyuhiDzS9Sde8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PLofwU59XexJuPQ8TLd0TWPOs0Lmjlu8C/0L1uDehxQKHifJsIpJ3WbouDHHownrT reHuj3PRwMYmWsYncLXea1p4vofS++EI6UNI6s9tvVxBKrxWXr6nVrPcUOgVJwazpb Q2rVIn08UmjHJtEpdqIZUacvRA4+8Ipx2r7Wvc/w= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 0122660FB1 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alindsay@codeaurora.org From: Aaron Lindsay To: qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Wei Huang , Peter Crosthwaite Date: Fri, 16 Mar 2018 16:31:19 -0400 Message-Id: <1521232280-13089-22-git-send-email-alindsay@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> References: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.96 Subject: [Qemu-devel] [PATCH v3 21/22] target/arm: PMU: Set PMCR.N to 4 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Spradling , qemu-devel@nongnu.org, Digant Desai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This both advertises that we support four counters and adds them to the implementation because the PMU_NUM_COUNTERS macro reads this value from the PMCR. Signed-off-by: Aaron Lindsay --- target/arm/helper.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 679897a..06e2e2c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1575,7 +1575,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .access =3D PL1_W, .type =3D ARM_CP_NOP }, /* Performance monitors are implementation defined in v7, * but with an ARM recommended set of registers, which we - * follow (although we don't actually implement any counters) + * follow. * * Performance registers fall into three categories: * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR) @@ -5192,7 +5192,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL0_RW, .accessfn =3D pmreg_access, .type =3D ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcr), - .resetvalue =3D cpu->midr & 0xff000000, + /* 4 counters enabled */ + .resetvalue =3D (cpu->midr & 0xff000000) | (0x4 << PMCRN_SHIFT= ), .writefn =3D pmcr_write, .raw_writefn =3D raw_write, }; define_one_arm_cp_reg(cpu, &pmcr); --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. 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charset="utf-8" Signed-off-by: Aaron Lindsay --- target/arm/helper.c | 44 ++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 42 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 06e2e2c..4f8d11c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -955,6 +955,15 @@ static bool event_always_supported(CPUARMState *env) return true; } =20 +static uint64_t swinc_get_count(CPUARMState *env, uint64_t cycles) +{ + /* + * SW_INCR events are written directly to the pmevcntr's by writes to + * PMSWINC, so there is no underlying count maintained by the PMU itse= lf + */ + return 0; +} + #ifndef CONFIG_USER_ONLY static uint64_t cycles_get_count(CPUARMState *env, uint64_t cycles) { @@ -974,6 +983,10 @@ static uint64_t instructions_get_count(CPUARMState *en= v, uint64_t cycles) =20 #define SUPPORTED_EVENT_SENTINEL UINT16_MAX static const pm_event pm_events[] =3D { + { .number =3D 0x000, /* SW_INCR */ + .supported =3D event_always_supported, + .get_count =3D swinc_get_count + }, #ifndef CONFIG_USER_ONLY { .number =3D 0x008, /* INST_RETIRED */ .supported =3D instructions_supported, @@ -1273,6 +1286,29 @@ static void pmcr_write(CPUARMState *env, const ARMCP= RegInfo *ri, pmu_op_finish(env, saved_cycles); } =20 +static void pmswinc_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + unsigned int i; + for (i =3D 0; i < PMU_NUM_COUNTERS(env); i++) { + /* Increment a counter's count iff: */ + if ((value & (1 << i)) && /* counter's bit is set */ + /* counter is enabled and not filtered */ + pmu_counter_enabled(env, i) && + !pmu_counter_filtered(env, env->cp15.c14_pmevtyper[i]) && + /* counter is SW_INCR */ + (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) =3D=3D = 0x0) { + uint64_t cycles =3D 0; +#ifndef CONFIG_USER_ONLY + cycles =3D get_cycle_count(env); +#endif + pmu_sync_counter(env, i, cycles); + env->cp15.c14_pmevcntr[i]++; + pmu_sync_counter(env, i, cycles); + } + } +} + static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) { uint64_t ret; @@ -1619,9 +1655,13 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmovsr), .writefn =3D pmovsr_write, .raw_writefn =3D raw_write }, - /* Unimplemented so WI. */ { .name =3D "PMSWINC", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D = 0, .opc2 =3D 4, - .access =3D PL0_W, .accessfn =3D pmreg_access_swinc, .type =3D ARM_C= P_NOP }, + .access =3D PL0_W, .accessfn =3D pmreg_access_swinc, .type =3D ARM_C= P_NO_RAW, + .writefn =3D pmswinc_write }, + { .name =3D "PMSWINC_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 4, + .access =3D PL0_W, .accessfn =3D pmreg_access_swinc, .type =3D ARM_C= P_NO_RAW, + .writefn =3D pmswinc_write }, { .name =3D "PMSELR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 5, .access =3D PL0_RW, .type =3D ARM_CP_ALIAS, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmselr), --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. From nobody Sat Oct 25 02:27:18 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1523553571348316.9174794856; Thu, 12 Apr 2018 10:19:31 -0700 (PDT) Received: from localhost ([::1]:56307 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f6fsg-00071G-HE for importer@patchew.org; Thu, 12 Apr 2018 13:19:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60436) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f6fqx-00065q-BS for qemu-devel@nongnu.org; Thu, 12 Apr 2018 13:17:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f6fqv-00019r-FD for qemu-devel@nongnu.org; Thu, 12 Apr 2018 13:17:43 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:50788) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1f6fqo-00013m-3n; Thu, 12 Apr 2018 13:17:34 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 0F5D360A00; Thu, 12 Apr 2018 17:17:33 +0000 (UTC) Received: from codeaurora.org (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: alindsay@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 9951F6072E; Thu, 12 Apr 2018 17:17:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1523553453; bh=ptRBGHgpJ4kBnxQy6lkP46myJe0a9kvLLPAZfIddep0=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=UfOz2/1lJ8kIRPtHVmBtUPhmDphp62oPmz87Oc1KpNreb5S+oslQexlZgynix1A5d UU7Zthmrw/UE72k/tHVIJldHM+IjOWwgd8PNDf0nqfnJ5Kf1dSwZ6V+boEsBhEBlkK PoAj92ZI7iEwPGLnsSQSht1AFTVNiGc9amjfJON0= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1523553451; bh=ptRBGHgpJ4kBnxQy6lkP46myJe0a9kvLLPAZfIddep0=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=MWvd1PwL2gap7QhmdjojoPj9GdsUOYUlxAS/MF1tsw7EroVVlij7XFwD0cJrkWUZ3 TXTFAKp5RsXIWMD6hD8JRO9DmqXAZIMc8EP8JHtxgo2okHobuS72GC/js4QPGv+e9y 3C9cNpHz76T5JQieFhQdRqGmQwCJ6Z1fXt8iBEsk= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 9951F6072E Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alindsay@codeaurora.org Date: Thu, 12 Apr 2018 13:17:28 -0400 From: Aaron Lindsay To: qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Wei Huang , Peter Crosthwaite Message-ID: <20180412171728.GJ24561@codeaurora.org> References: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> User-Agent: Mutt/1.5.23 (2014-03-12) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.96 Subject: [Qemu-devel] [PATCH v3] RFC: target/arm: Send interrupts on PMU counter overflow X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Spradling , qemu-devel@nongnu.org, Digant Desai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On Mar 16 16:30, Aaron Lindsay wrote: > I aim to eventually add raising interrupts on counter overflow, but that = is not > covered by this patchset. I think I have a reasonable grasp of the mechan= ics of > *how* to raise them, but am curious if anyone has thoughts on how to dete= rmine > *when* to raise them - we don't want to call into PMU code every time an > instruction is executed to check if any instruction counters have overflo= wed, > etc. The main candidate I've seen for doing this so far would be to set u= p a > QEMUTimer, but I haven't fully explored it. Does that seem plausible? Any > other/better ideas? I'm planning to post a full v4 of this patchset soon, pending a few review fixes, but I figured I'd throw out an early version of a patch to add interrupts on overflow in case it obviously has major issues that will need to be addressed. This patch sets up a QEMUTimer to get a callback when we expect counters to next overflow and triggers an interrupt at that time. Signed-off-by: Aaron Lindsay --- target/arm/cpu.c | 11 +++++ target/arm/cpu.h | 7 +++ target/arm/helper.c | 129 ++++++++++++++++++++++++++++++++++++++++++++++++= ---- 3 files changed, 138 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index df27188..9108c6b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -740,6 +740,12 @@ static void arm_cpu_finalizefn(Object *obj) QLIST_REMOVE(hook, node); g_free(hook); } +#ifndef CONFIG_USER_ONLY + if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { + timer_deinit(cpu->pmu_timer); + timer_free(cpu->pmu_timer); + } +#endif } =20 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) @@ -907,6 +913,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Error = **errp) =20 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); + +#ifndef CONFIG_USER_ONLY + cpu->pmu_timer =3D timer_new(QEMU_CLOCK_VIRTUAL, 1, arm_pmu_timer_= cb, + cpu); +#endif } else { cpu->pmceid0 =3D 0x00000000; cpu->pmceid1 =3D 0x00000000; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 5e6bbd3..bc0867f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -703,6 +703,8 @@ struct ARMCPU { =20 /* Timers used by the generic (architected) timer */ QEMUTimer *gt_timer[NUM_GTIMERS]; + /* Timer used by the PMU */ + QEMUTimer *pmu_timer; /* GPIO outputs for generic timer */ qemu_irq gt_timer_outputs[NUM_GTIMERS]; /* GPIO output for GICv3 maintenance interrupt signal */ @@ -934,6 +936,11 @@ void pmu_op_start(CPUARMState *env); void pmu_op_finish(CPUARMState *env); =20 /** + * Called when a PMU counter is due to overflow + */ +void arm_pmu_timer_cb(void *opaque); + +/** * Functions to register as EL change hooks for PMU mode filtering */ void pmu_pre_el_change(ARMCPU *cpu, void *ignored); diff --git a/target/arm/helper.c b/target/arm/helper.c index 2147678..abe24dc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -905,6 +905,7 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { /* Definitions for the PMU registers */ #define PMCRN_MASK 0xf800 #define PMCRN_SHIFT 11 +#define PMCRLC 0x40 #define PMCRD 0x8 #define PMCRC 0x4 #define PMCRP 0x2 @@ -919,6 +920,8 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { #define PMXEVTYPER_MT 0x02000000 #define PMXEVTYPER_EVTCOUNT 0x000003ff =20 +#define PMEVCNTR_OVERFLOW_MASK ((uint64_t)1 << 31) + #define PMCCFILTR 0xf8000000 #define PMCCFILTR_M PMXEVTYPER_M #define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M) @@ -934,6 +937,11 @@ typedef struct pm_event { /* Retrieve the current count of the underlying event. The programmed * counters hold a difference from the return value from this function= */ uint64_t (*get_count)(CPUARMState *); + /* Return how many nanoseconds it will take (at a minimum) for count e= vents + * to occur. A negative value indicates the counter will never overflo= w, or + * that the counter has otherwise arranged for the overflow bit to be = set + * and the PMU interrupt to be raised on overflow. */ + int64_t (*ns_per_count)(uint64_t); } pm_event; =20 static bool event_always_supported(CPUARMState *env) @@ -950,6 +958,11 @@ static uint64_t swinc_get_count(CPUARMState *env) return 0; } =20 +static int64_t swinc_ns_per(uint64_t ignored) +{ + return -1; +} + /* * Return the underlying cycle count for the PMU cycle counters. If we're = in * usermode, simply return 0. @@ -965,6 +978,11 @@ static uint64_t cycles_get_count(CPUARMState *env) } =20 #ifndef CONFIG_USER_ONLY +static int64_t cycles_ns_per(uint64_t cycles) +{ + return ARM_CPU_FREQ/NANOSECONDS_PER_SECOND; +} + static bool instructions_supported(CPUARMState *env) { return use_icount =3D=3D 1 /* Precise instruction counting */; @@ -974,22 +992,30 @@ static uint64_t instructions_get_count(CPUARMState *e= nv) { return (uint64_t)cpu_get_icount_raw(); } + +static int64_t instructions_ns_per(uint64_t icount) +{ + return cpu_icount_to_ns((int64_t)icount); +} #endif =20 #define SUPPORTED_EVENT_SENTINEL UINT16_MAX static const pm_event pm_events[] =3D { { .number =3D 0x000, /* SW_INCR */ .supported =3D event_always_supported, - .get_count =3D swinc_get_count + .get_count =3D swinc_get_count, + .ns_per_count =3D swinc_ns_per }, #ifndef CONFIG_USER_ONLY { .number =3D 0x008, /* INST_RETIRED, Instruction architecturally exec= uted */ .supported =3D instructions_supported, - .get_count =3D instructions_get_count + .get_count =3D instructions_get_count, + .ns_per_count =3D instructions_ns_per }, { .number =3D 0x011, /* CPU_CYCLES, Cycle */ .supported =3D event_always_supported, - .get_count =3D cycles_get_count + .get_count =3D cycles_get_count, + .ns_per_count =3D cycles_ns_per }, #endif { .number =3D SUPPORTED_EVENT_SENTINEL } @@ -1168,6 +1194,13 @@ static inline bool pmu_counter_filtered(CPUARMState = *env, uint64_t pmxevtyper) return false; } =20 +static void pmu_update_irq(CPUARMState *env) +{ + ARMCPU *cpu =3D arm_env_get_cpu(env); + qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) && + (env->cp15.c9_pminten & env->cp15.c9_pmovsr)); +} + /* * Ensure c15_ccnt is the guest-visible count so that operations such as * enabling/disabling the counter or filtering, modifying the count itself, @@ -1186,7 +1219,18 @@ void pmccntr_op_start(CPUARMState *env) eff_cycles /=3D 64; } =20 - env->cp15.c15_ccnt =3D eff_cycles - env->cp15.c15_ccnt_delta; + uint64_t new_pmccntr =3D eff_cycles - env->cp15.c15_ccnt_delta; + + unsigned int overflow_bit =3D (env->cp15.c9_pmcr & PMCRLC) ? 63 : = 31; + uint64_t overflow_mask =3D (uint64_t)1 << overflow_bit; + if (!(new_pmccntr & overflow_mask) && + (env->cp15.c15_ccnt & overflow_mask)) { + env->cp15.c9_pmovsr |=3D (1 << 31); + new_pmccntr &=3D ~overflow_mask; + pmu_update_irq(env); + } + + env->cp15.c15_ccnt =3D new_pmccntr; } env->cp15.c15_ccnt_delta =3D cycles; } @@ -1200,13 +1244,25 @@ void pmccntr_op_finish(CPUARMState *env) { if (arm_ccnt_enabled(env) && !pmu_counter_filtered(env, env->cp15.pmccfiltr_el0)) { - uint64_t prev_cycles =3D env->cp15.c15_ccnt_delta; +#ifndef CONFIG_USER_ONLY + uint64_t delta =3D ((env->cp15.c9_pmcr & PMCRLC) ? + UINT64_MAX : UINT32_MAX) - (uint32_t)env->cp15.c15_ccnt; + int64_t overflow_in =3D cycles_ns_per(delta); =20 + if (overflow_in >=3D 0) + { + int64_t overflow_at =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + + overflow_in; + ARMCPU *cpu =3D arm_env_get_cpu(env); + timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); + } +#endif + + uint64_t prev_cycles =3D env->cp15.c15_ccnt_delta; if (env->cp15.c9_pmcr & PMCRD) { /* Increment once every 64 processor clock cycles */ prev_cycles /=3D 64; } - env->cp15.c15_ccnt_delta =3D prev_cycles - env->cp15.c15_ccnt; } } @@ -1220,8 +1276,16 @@ static void pmevcntr_op_start(CPUARMState *env, uint= 8_t counter) =20 if (pmu_counter_enabled(env, counter) && !pmu_counter_filtered(env, env->cp15.c14_pmevtyper[counter])) { - env->cp15.c14_pmevcntr[counter] =3D - count - env->cp15.c14_pmevcntr_delta[counter]; + + uint64_t new_pmevcntr =3D count - env->cp15.c14_pmevcntr_delta[cou= nter]; + + if (!(new_pmevcntr & PMEVCNTR_OVERFLOW_MASK) && + (env->cp15.c14_pmevcntr[counter] & PMEVCNTR_OVERFLOW_MASK)= ) { + env->cp15.c9_pmovsr |=3D (1 << counter); + new_pmevcntr &=3D ~PMEVCNTR_OVERFLOW_MASK; + pmu_update_irq(env); + } + env->cp15.c14_pmevcntr[counter] =3D new_pmevcntr; } env->cp15.c14_pmevcntr_delta[counter] =3D count; } @@ -1230,6 +1294,21 @@ static void pmevcntr_op_finish(CPUARMState *env, uin= t8_t counter) { if (pmu_counter_enabled(env, counter) && !pmu_counter_filtered(env, env->cp15.c14_pmevtyper[counter])) { +#ifndef CONFIG_USER_ONLY + uint16_t event =3D env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_E= VTCOUNT; + uint16_t event_idx =3D supported_event_map[event]; + uint64_t delta =3D UINT32_MAX - (uint32_t)env->cp15.c14_pmevcntr[c= ounter]; + int64_t overflow_in =3D pm_events[event_idx].ns_per_count(delta); + + if (overflow_in >=3D 0) + { + int64_t overflow_at =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + + overflow_in; + ARMCPU *cpu =3D arm_env_get_cpu(env); + timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); + } +#endif + env->cp15.c14_pmevcntr_delta[counter] -=3D env->cp15.c14_pmevcntr[counter]; } @@ -1263,6 +1342,18 @@ void pmu_post_el_change(ARMCPU *cpu, void *ignored) pmu_op_finish(&cpu->env); } =20 +void arm_pmu_timer_cb(void *opaque) { + ARMCPU *cpu =3D opaque; + + /* Update all the counter values based on the current underlying count= s, + * triggering interrupts to be raised, if necessary. pmu_op_finish() a= lso + * has the effect of setting the cpu->pmu_timer to the next earliest t= ime a + * counter may expire. + */ + pmu_op_start(&cpu->env); + pmu_op_finish(&cpu->env); +} + static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -1300,7 +1391,21 @@ static void pmswinc_write(CPUARMState *env, const AR= MCPRegInfo *ri, /* counter is SW_INCR */ (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) =3D=3D = 0x0) { pmevcntr_op_start(env, i); - env->cp15.c14_pmevcntr[i]++; + + /* Detect if this write causes an overflow since we can't pred= ict + * PMSWINC overflows like we can for other events + */ + uint64_t new_pmswinc =3D env->cp15.c14_pmevcntr[i] + 1; + + if (!(new_pmswinc & PMEVCNTR_OVERFLOW_MASK) && + (env->cp15.c14_pmevcntr[i] & PMEVCNTR_OVERFLOW_MASK)) { + env->cp15.c9_pmovsr |=3D (1 << i); + new_pmswinc &=3D ~PMEVCNTR_OVERFLOW_MASK; + pmu_update_irq(env); + } + + env->cp15.c14_pmevcntr[i] =3D new_pmswinc; + pmevcntr_op_finish(env, i); } } @@ -1371,6 +1476,7 @@ static void pmcntenset_write(CPUARMState *env, const = ARMCPRegInfo *ri, { value &=3D PMU_COUNTER_MASK(env); env->cp15.c9_pmcnten |=3D value; + pmu_update_irq(env); } =20 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -1378,6 +1484,7 @@ static void pmcntenclr_write(CPUARMState *env, const = ARMCPRegInfo *ri, { value &=3D PMU_COUNTER_MASK(env); env->cp15.c9_pmcnten &=3D ~value; + pmu_update_irq(env); } =20 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -1385,6 +1492,7 @@ static void pmovsr_write(CPUARMState *env, const ARMC= PRegInfo *ri, { value &=3D PMU_COUNTER_MASK(env); env->cp15.c9_pmovsr &=3D ~value; + pmu_update_irq(env); } =20 static void pmovsset_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -1392,6 +1500,7 @@ static void pmovsset_write(CPUARMState *env, const AR= MCPRegInfo *ri, { value &=3D PMU_COUNTER_MASK(env); env->cp15.c9_pmovsr |=3D value; + pmu_update_irq(env); } =20 static void pmevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -1517,6 +1626,7 @@ static void pmintenset_write(CPUARMState *env, const = ARMCPRegInfo *ri, /* We have no event counters so only the C bit can be changed */ value &=3D PMU_COUNTER_MASK(env); env->cp15.c9_pminten |=3D value; + pmu_update_irq(env); } =20 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -1524,6 +1634,7 @@ static void pmintenclr_write(CPUARMState *env, const = ARMCPRegInfo *ri, { value &=3D PMU_COUNTER_MASK(env); env->cp15.c9_pminten &=3D ~value; + pmu_update_irq(env); } =20 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. 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