From nobody Sat Oct 25 11:05:05 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521229639428984.6821870024455; Fri, 16 Mar 2018 12:47:19 -0700 (PDT) Received: from localhost ([::1]:59218 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvJu-0002hO-0w for importer@patchew.org; Fri, 16 Mar 2018 15:47:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40192) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvF7-0007Jd-4Y for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ewvF3-0003go-Q4 for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:21 -0400 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:39335) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ewvF3-0003gW-JX for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:17 -0400 Received: by mail-pg0-x242.google.com with SMTP id e3so4461653pga.6 for ; Fri, 16 Mar 2018 12:42:17 -0700 (PDT) Received: from monty.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id k24sm13780469pff.77.2018.03.16.12.42.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 16 Mar 2018 12:42:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bAnmiNe0Jq/bKPe/yscQG8mYo4LaV7stvbgTiCOkIvc=; b=SKqskxgeU1LsHjtpSLNu6IQEB8pNwSMRJmyeSV37OUp8GMtihkirVixySc+9+P5GxO G/KpbS2ikS59qHuzqM2Rm/v2dJk/CqCNI5SpT0h/kBmH3u+No1P1uDCslN+VxRhd2H3e He5YYmxZF6y4u8bSWpQHYJYvlXJZz+yTUJ9qmshU2L+2Gcy//lFlxOmJXwAOp/1KlnN9 DJgcfmeOHHGHditqLP+vXCudIntBpVHdWKNhxIUGsSN1TaBv67bBdjY9mtrXjYB4s9lL y9Pcb1yJVqUneQeznhmrC1xR2CosBWV5P1xjMnZqmjGJvx5a/ld1jwOU7C/GQfH9W3Os 99kg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bAnmiNe0Jq/bKPe/yscQG8mYo4LaV7stvbgTiCOkIvc=; b=jD9RckDogQclL51lwdGEy1Ph8Pc3uT7L/+IsYgr2AJ3pKuoJP+ZzDJ4znTHqksCzyP Ocf0zmkqFzxGCJfQ6c1mdu4rVO1nyUtMvtsZv9qiPyb6794n2lcHgW4meg8Y7f8nkObx lOipqlzt9/3rQ4cHbYes/aCgzqZlxQQ43d6lQFkVQSPjA2C9fo0rvcJ0GFLNwMNnDzHH EKuIS8yDEgWLJ5WWPa5sFQtwoWpbzmYT5HmVt+azbswKOIzWnb8yIaeSzX0dFTix6Ghb cMp+zjO+6nMtTi/z8aVpk/iwuvvp37/sALv6t6C+Dvx3Ns6QNSBxBLpFiMQvql43EvJ+ SL3Q== X-Gm-Message-State: AElRT7Ga1v4nrDxu6Vvmcx90a/CR2R5lVjeZe8KhBA+OCVw3grfrtcMk SkZNqy3PYP9xnur2+cERP/4/Me4oRLU= X-Google-Smtp-Source: AG47ELt+rAHm/qc+/2ZfMLjPwbG4kVKjvPnNpOG0+46NAUiItKytC4qMe/F/TkdluMsmmKkD5pFIlw== X-Received: by 10.101.82.198 with SMTP id z6mr2372618pgp.41.1521229336478; Fri, 16 Mar 2018 12:42:16 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Fri, 16 Mar 2018 12:40:58 -0700 Message-Id: <1521229281-73637-2-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1521229281-73637-1-git-send-email-mjc@sifive.com> References: <1521229281-73637-1-git-send-email-mjc@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v3 01/24] RISC-V: Make virt create_fdt interface consistent X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 create_fdt sets the fdt variable on RISCVVirtState and this is used to access the fdt. This reverts a change introduced in https://github.com/riscv/riscv-qemu/pull/109 which introduced a redundant return value, overlooking the RISCVVirtState structure member that made create_fdt inconsistent with the other RISC-V machines. The other alternative is to change the other boards to return the fdt. Note: the RISCVVirtState also contains fdt_size. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/virt.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index e2c214e..37968d2 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -108,7 +108,7 @@ static hwaddr load_initrd(const char *filename, uint64_= t mem_size, return *start + size; } =20 -static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memma= p, +static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, uint64_t mem_size, const char *cmdline) { void *fdt; @@ -264,8 +264,6 @@ static void *create_fdt(RISCVVirtState *s, const struct= MemmapEntry *memmap, qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); g_free(nodename); - - return fdt; } =20 static void riscv_virt_board_init(MachineState *machine) @@ -279,7 +277,6 @@ static void riscv_virt_board_init(MachineState *machine) char *plic_hart_config; size_t plic_hart_config_len; int i; - void *fdt; =20 /* Initialize SOC */ object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY); @@ -299,7 +296,7 @@ static void riscv_virt_board_init(MachineState *machine) main_mem); =20 /* create device tree */ - fdt =3D create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdli= ne); + create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); =20 /* boot rom */ memory_region_init_ram(boot_rom, NULL, "riscv_virt_board.bootrom", @@ -314,9 +311,9 @@ static void riscv_virt_board_init(MachineState *machine) hwaddr end =3D load_initrd(machine->initrd_filename, machine->ram_size, kernel_entry, &start); - qemu_fdt_setprop_cell(fdt, "/chosen", - "linux,initrd-start", start); - qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", + qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-start", + start); + qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", end); } } --=20 2.7.0 From nobody Sat Oct 25 11:05:05 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521229491387561.4720991505441; Fri, 16 Mar 2018 12:44:51 -0700 (PDT) Received: from localhost ([::1]:59202 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvH3-0000EG-4a for importer@patchew.org; Fri, 16 Mar 2018 15:44:21 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40193) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvF7-0007Je-4k for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ewvF5-0003he-PS for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:21 -0400 Received: from mail-pf0-x243.google.com ([2607:f8b0:400e:c00::243]:45951) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ewvF5-0003hJ-Gi for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:19 -0400 Received: by mail-pf0-x243.google.com with SMTP id l27so19353pfk.12 for ; Fri, 16 Mar 2018 12:42:19 -0700 (PDT) Received: from monty.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id k24sm13780469pff.77.2018.03.16.12.42.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 16 Mar 2018 12:42:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QPBz7Fnm8zCTZxjDgsY9fojmmXnmGLqeFGCqpRAlGF4=; b=EotL4XZMerrZ3Uw9J8VhMC+5cidMO5ZdiK7v8s7A70r2021mKPLyBAdjS0+u/XkpP0 kdSYudH/lqCo7SgVLYieOPjJJYClecnYV7Va6zknGQUJWSqINUWPBuIUikBDUQy0kL0m ez8RWva+QeSRRxA0FEWpPjIyX+dAkVApWzJIXnuJluRF2P4KbbDUIwnYzFas+vEriqnE QDnZ7HTTHwTLOc4HaoSnh0AUz3OVgvbtW5wNgAHn9EHPcoCXFiDt+b+kqPWdYFovUa5W Q8C227pQik8Zd73vH/GUOEBh28sOOL7WFZUjySM7J7+P0FXqAcRmQbq4Q7aa/A6aBpWl SCUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QPBz7Fnm8zCTZxjDgsY9fojmmXnmGLqeFGCqpRAlGF4=; b=cdHEM5w5g7vmUerfoN+yBggOxGzj8qLCpGlQXwgg85Iv8u1aBNJKGxX0oTeerQxO3p PY7SbAtFNYlQJ0ODZ/8P4F+LPLfXX3Z/Npw+YffthcalZGgZ+A/P6VzzCIni/+pJZEmo xVOW6wP4A3RM8Pzil/UBzF2qKQxrRhE/LZaFGvZwNQPqjLLy1e0tHwe90Kudmfv9xKWi 4127/WR8RTlo+ZdEnuTkCF3iGffq2G6NvTJr3G2aYUJLBxNRoqJ1bNNyw1zJKaUMCUIB rmGx2MXb3gcReRx6d0g5oW5kJ/puJpkT90ft0DFWgHClphygyPo5TulinPeWaxPvM3xD Ev9A== X-Gm-Message-State: AElRT7GYfdKeM660mZW5iCN6vhmCQI3UoPfGaYgeqNheGcvmSWJqCty0 0SBgJj/2dfi8tLBRKxvlYr109dyh0jI= X-Google-Smtp-Source: AG47ELuWoiAW0Lbz+IpYSChuHvBlxGjGfvfZKe3rWMR/jtseF5b2PHyHrFWopEXqZpgzbrCVhD89gw== X-Received: by 10.99.64.3 with SMTP id n3mr2448253pga.316.1521229337519; Fri, 16 Mar 2018 12:42:17 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Fri, 16 Mar 2018 12:40:59 -0700 Message-Id: <1521229281-73637-3-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1521229281-73637-1-git-send-email-mjc@sifive.com> References: <1521229281-73637-1-git-send-email-mjc@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH v3 02/24] RISC-V: Replace hardcoded constants with enum values X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 The RISC-V device-tree code has a number of hard-coded constants and this change moves them into header enums. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/sifive_clint.c | 9 +++------ hw/riscv/sifive_u.c | 6 ++++-- hw/riscv/spike.c | 6 ++++-- hw/riscv/virt.c | 6 ++++-- include/hw/riscv/sifive_clint.h | 4 ++++ include/hw/riscv/sifive_u.h | 4 ++++ include/hw/riscv/spike.h | 4 ++++ include/hw/riscv/virt.h | 4 ++++ 8 files changed, 31 insertions(+), 12 deletions(-) diff --git a/hw/riscv/sifive_clint.c b/hw/riscv/sifive_clint.c index 4893453..7cc606e 100644 --- a/hw/riscv/sifive_clint.c +++ b/hw/riscv/sifive_clint.c @@ -26,13 +26,10 @@ #include "hw/riscv/sifive_clint.h" #include "qemu/timer.h" =20 -/* See: riscv-pk/machine/sbi_entry.S and arch/riscv/kernel/time.c */ -#define TIMER_FREQ (10 * 1000 * 1000) - static uint64_t cpu_riscv_read_rtc(void) { - return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), TIMER_FREQ, - NANOSECONDS_PER_SECOND); + return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + SIFIVE_CLINT_TIMEBASE_FREQ, NANOSECONDS_PER_SECOND); } =20 /* @@ -59,7 +56,7 @@ static void sifive_clint_write_timecmp(RISCVCPU *cpu, uin= t64_t value) diff =3D cpu->env.timecmp - rtc_r; /* back to ns (note args switched in muldiv64) */ next =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + - muldiv64(diff, NANOSECONDS_PER_SECOND, TIMER_FREQ); + muldiv64(diff, NANOSECONDS_PER_SECOND, SIFIVE_CLINT_TIMEBASE_FREQ); timer_mod(cpu->env.timer, next); } =20 diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 1c2deef..f3f7615 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -122,7 +122,8 @@ static void create_fdt(SiFiveUState *s, const struct Me= mmapEntry *memmap, g_free(nodename); =20 qemu_fdt_add_subnode(fdt, "/cpus"); - qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 10000000); + qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", + SIFIVE_CLINT_TIMEBASE_FREQ); qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); =20 @@ -131,7 +132,8 @@ static void create_fdt(SiFiveUState *s, const struct Me= mmapEntry *memmap, char *intc =3D g_strdup_printf("/cpus/cpu@%d/interrupt-controller"= , cpu); char *isa =3D riscv_isa_string(&s->soc.harts[cpu]); qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 1000000000= ); + qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", + SIFIVE_U_CLOCK_FREQ); qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 2d1f114..4c233ec 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -115,7 +115,8 @@ static void create_fdt(SpikeState *s, const struct Memm= apEntry *memmap, g_free(nodename); =20 qemu_fdt_add_subnode(fdt, "/cpus"); - qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 10000000); + qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", + SIFIVE_CLINT_TIMEBASE_FREQ); qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); =20 @@ -124,7 +125,8 @@ static void create_fdt(SpikeState *s, const struct Memm= apEntry *memmap, char *intc =3D g_strdup_printf("/cpus/cpu@%d/interrupt-controller"= , cpu); char *isa =3D riscv_isa_string(&s->soc.harts[cpu]); qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 1000000000= ); + qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", + SPIKE_CLOCK_FREQ); qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 37968d2..a402856 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -145,7 +145,8 @@ static void create_fdt(RISCVVirtState *s, const struct = MemmapEntry *memmap, g_free(nodename); =20 qemu_fdt_add_subnode(fdt, "/cpus"); - qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 10000000); + qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", + SIFIVE_CLINT_TIMEBASE_FREQ); qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); =20 @@ -155,7 +156,8 @@ static void create_fdt(RISCVVirtState *s, const struct = MemmapEntry *memmap, char *intc =3D g_strdup_printf("/cpus/cpu@%d/interrupt-controller"= , cpu); char *isa =3D riscv_isa_string(&s->soc.harts[cpu]); qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 1000000000= ); + qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", + VIRT_CLOCK_FREQ); qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); diff --git a/include/hw/riscv/sifive_clint.h b/include/hw/riscv/sifive_clin= t.h index aaa2a58..e2865be 100644 --- a/include/hw/riscv/sifive_clint.h +++ b/include/hw/riscv/sifive_clint.h @@ -47,4 +47,8 @@ enum { SIFIVE_TIME_BASE =3D 0xBFF8 }; =20 +enum { + SIFIVE_CLINT_TIMEBASE_FREQ =3D 10000000 +}; + #endif diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 662e8a1..be38aa0 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -50,6 +50,10 @@ enum { SIFIVE_U_UART1_IRQ =3D 4 }; =20 +enum { + SIFIVE_U_CLOCK_FREQ =3D 1000000000 +}; + #define SIFIVE_U_PLIC_HART_CONFIG "MS" #define SIFIVE_U_PLIC_NUM_SOURCES 127 #define SIFIVE_U_PLIC_NUM_PRIORITIES 7 diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h index cb55a14..d85a64e 100644 --- a/include/hw/riscv/spike.h +++ b/include/hw/riscv/spike.h @@ -42,6 +42,10 @@ enum { SPIKE_DRAM }; =20 +enum { + SPIKE_CLOCK_FREQ =3D 1000000000 +}; + #if defined(TARGET_RISCV32) #define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV32GCSU_V1_09_1 #define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0 diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 7525647..2fbe808 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -55,6 +55,10 @@ enum { VIRTIO_NDEV =3D 10 }; =20 +enum { + VIRT_CLOCK_FREQ =3D 1000000000 +}; + #define VIRT_PLIC_HART_CONFIG "MS" #define VIRT_PLIC_NUM_SOURCES 127 #define VIRT_PLIC_NUM_PRIORITIES 7 --=20 2.7.0 From nobody Sat Oct 25 11:05:05 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15212294599381021.3129762601809; Fri, 16 Mar 2018 12:44:19 -0700 (PDT) Received: from localhost ([::1]:59200 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvH0-0000Ce-Ve for importer@patchew.org; Fri, 16 Mar 2018 15:44:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40195) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvF7-0007Jf-5L for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ewvF5-0003hW-ML for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:21 -0400 Received: from mail-pf0-x241.google.com ([2607:f8b0:400e:c00::241]:36312) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ewvF5-0003hI-GT for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:19 -0400 Received: by mail-pf0-x241.google.com with SMTP id 68so4549905pfx.3 for ; Fri, 16 Mar 2018 12:42:19 -0700 (PDT) Received: from monty.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id k24sm13780469pff.77.2018.03.16.12.42.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 16 Mar 2018 12:42:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2ODhQsu8bMdo4DGVv9mn+NU8m9MKD+QUrGsVGZgEKHo=; b=dE4lJapWtr9HTHk6X5COPl4yrjESalV4ZP5GuuhsJ5gLDgHo8T7t9f4xZ/fVGc+/za ntaFvCQeUOUn3UHc2umoGZnlJDhVY6sPAWH0mQqlhPZdFRmXw9tZMH2u05BXcFmvQnpn 6LAvA/YAsnM9d+yDGmYpVS0vDPAElywjoUpTaxGut+jvYH3zOAMzoxoWJC3bpK4EBQVP w+34ILKc4zgeohxhy4tKh+QM8UJ4lsa8YtHaLUpfM3G6EwiJE1CmwwsMobJaT9KOJ16h b/S1UD/7oQkqryp4I44rUlgQjw3j9N5QbDllkkWPaVJlpXqdbrzHR4AWHuEWIjj8eDsB Zd4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2ODhQsu8bMdo4DGVv9mn+NU8m9MKD+QUrGsVGZgEKHo=; b=tUc6tl2yTILXScXXZuWXk8vbl0NqXoYjm7Ko4T7C+DHPXA9lX4uaYv8F1qWNF81IkD jSq3pzKZPyr1rUU+5r4/DfSk1N90ECa4BIaAS+8oUthsh8amfztHpaXx+rgN3Ep86oYj tYox9+eSbwPQjoyjlHcQ6/csRF6NrHperhs+X/vo7dlYVuy0jiuaXfAbuAPa8NlLuquo n0g4FcPX11dtHGno+XL8B/u/1N3eA3zaHWJbq8c63u0tXqasVi3FbJISu5hpJ3ksNywy 5y/a6qwXA8cq4wyIINEcVD/TzxlTXgETNljfqGwk4XQyHkwlBIjzmMO23w4XehwlOWLA rhGw== X-Gm-Message-State: AElRT7FPHjYPpFTSEy0FCLIRPKF7gczxrDqWZ37xU7jgEzY+iZUWm36z kBvjslT+yrY8CoGwdikJjixZUHE4yqw= X-Google-Smtp-Source: AG47ELvgBKL65QYzuryAr+PQhS9AVa5Gii2FJ7HqU6Sd5Wmvw+4wNMGJlkYGoYH0MPLGH/TEQShKHQ== X-Received: by 10.99.152.10 with SMTP id q10mr2417448pgd.62.1521229338410; Fri, 16 Mar 2018 12:42:18 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Fri, 16 Mar 2018 12:41:00 -0700 Message-Id: <1521229281-73637-4-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1521229281-73637-1-git-send-email-mjc@sifive.com> References: <1521229281-73637-1-git-send-email-mjc@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v3 03/24] RISC-V: Make virt board description match spike X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 This makes 'qemu-system-riscv64 -machine help' output more tidy and consistent. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/virt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index a402856..0055439 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -404,7 +404,7 @@ static const TypeInfo riscv_virt_board_device =3D { =20 static void riscv_virt_board_machine_init(MachineClass *mc) { - mc->desc =3D "RISC-V VirtIO Board (Privileged spec v1.10)"; + mc->desc =3D "RISC-V VirtIO Board (Privileged ISA v1.10)"; mc->init =3D riscv_virt_board_init; mc->max_cpus =3D 8; /* hardcoded limit in BBL */ } --=20 2.7.0 From nobody Sat Oct 25 11:05:05 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521229491854253.6249110557883; Fri, 16 Mar 2018 12:44:51 -0700 (PDT) Received: from localhost ([::1]:59201 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvH2-0000DX-Je for importer@patchew.org; Fri, 16 Mar 2018 15:44:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40209) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvF7-0007Jm-N0 for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ewvF6-0003i3-Qf for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:21 -0400 Received: from mail-pl0-x241.google.com ([2607:f8b0:400e:c01::241]:33848) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ewvF6-0003hl-K5 for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:20 -0400 Received: by mail-pl0-x241.google.com with SMTP id u11-v6so2848567plq.1 for ; Fri, 16 Mar 2018 12:42:20 -0700 (PDT) Received: from monty.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id k24sm13780469pff.77.2018.03.16.12.42.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 16 Mar 2018 12:42:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=etZGfs2I6eIUVzklmG0XvLcDBBdWMcIvQq939Ceof5k=; b=i5acHagiFdgmwVHCgOwsDdB/2C80TWTkMesoHLnvpVHhxjAWxAfJEeUMyueNPNGfWg dRlzSG3aPhzv7yofpic4MuqfVTsmFjfUAdNWfAXSHY7DNjSNwzDPtT9pWE8QZunnDsD1 X4g3u3fN4wUVqo8srzid6wQ3Z8QEIxS9+OTnlI6d0256O4iw9XYWpj7fqf3tctodIaLs D9WpAYPsHqPxFXSqloOCe4UsYkyJIzAzD8ILqxan+Ex3DjXXKaAZIriNxz8QrMZJR8Tr pAvEF7ZnkzfS0+Zc5fBgZoK2bsWFauxv2JkC2daTWZg7Tx1g7i8clfIfkirRC+iVurz7 HUNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=etZGfs2I6eIUVzklmG0XvLcDBBdWMcIvQq939Ceof5k=; b=gTUcBIv8xYVs3ynsYy/ZzzzaU5/hOsn7f27xSqBc76x3B88GrukH+wjOa/TJz+PTC+ fAJWLXpNzV4ztn5fY0ahdyVvBzn+CYndgqMQnVeWJHpvCJUwfJfGFfho4Bt4ojBwexkK AB4Tnjz04LQDSEKSx1O4J2Cc6IxgRlScILpzyB0lo3A4pir9Xzppun/rJUf+XskmLZdg 984DLIEr85/9ij0Kx8rrqRkVSujbzFggzUgwcyoeQuaRhE0a+9kjJJswra5MnUvuJ/jF HBTVydCHNKR+pFWOZOHopMBXKzfesrI41RJK7KiUS556VbFzGEl+0qM0ddrtYXq5Hirt BnVw== X-Gm-Message-State: AElRT7HX6Xh/7haV8uhgy1CIOuBSujhtmZg9U5HOD1QcnC5Q5nxGHZjP QCugflOgjlo4iTx5DDOxlnU7i6a9XhM= X-Google-Smtp-Source: AG47ELvg9sI5ZwFTbfJEKB8tVCSkW64QI6Yn9v5Go6EjmoElJ8VKe515YNWAfVgZlNh4geQz6jPRVA== X-Received: by 2002:a17:902:c24:: with SMTP id 33-v6mr3423595pls.88.1521229339332; Fri, 16 Mar 2018 12:42:19 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Fri, 16 Mar 2018 12:41:01 -0700 Message-Id: <1521229281-73637-5-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1521229281-73637-1-git-send-email-mjc@sifive.com> References: <1521229281-73637-1-git-send-email-mjc@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::241 Subject: [Qemu-devel] [PATCH v3 04/24] RISC-V: Use ROM base address and size from memmap X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Another case of replacing hard coded constants, this time referring to the definition in the virt machine's memmap. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/virt.c | 4 ++-- include/hw/riscv/virt.h | 2 -- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 0055439..0d101fc 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -338,11 +338,11 @@ static void riscv_virt_board_init(MachineState *machi= ne) }; =20 /* copy in the reset vector */ - copy_le32_to_phys(ROM_BASE, reset_vec, sizeof(reset_vec)); + copy_le32_to_phys(memmap[VIRT_MROM].base, reset_vec, sizeof(reset_vec)= ); =20 /* copy in the device tree */ qemu_fdt_dumpdtb(s->fdt, s->fdt_size); - cpu_physical_memory_write(ROM_BASE + sizeof(reset_vec), + cpu_physical_memory_write(memmap[VIRT_MROM].base + sizeof(reset_vec), s->fdt, s->fdt_size); =20 /* create PLIC hart topology configuration string */ diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 2fbe808..655e85d 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -23,8 +23,6 @@ #define VIRT(obj) \ OBJECT_CHECK(RISCVVirtState, (obj), TYPE_RISCV_VIRT_BOARD) =20 -enum { ROM_BASE =3D 0x1000 }; - typedef struct { /*< private >*/ SysBusDevice parent_obj; --=20 2.7.0 From nobody Sat Oct 25 11:05:05 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521229831481669.320240795075; Fri, 16 Mar 2018 12:50:31 -0700 (PDT) Received: from localhost ([::1]:59232 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvMs-0005Ar-3w for importer@patchew.org; Fri, 16 Mar 2018 15:50:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40232) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvF8-0007KC-PG for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ewvF7-0003ih-Qn for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:22 -0400 Received: from mail-pl0-x242.google.com ([2607:f8b0:400e:c01::242]:35260) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ewvF7-0003iD-LF for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:21 -0400 Received: by mail-pl0-x242.google.com with SMTP id p9-v6so3963101pls.2 for ; Fri, 16 Mar 2018 12:42:21 -0700 (PDT) Received: from monty.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id k24sm13780469pff.77.2018.03.16.12.42.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 16 Mar 2018 12:42:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iQkLw7e7jDGRvqEWGlEj0fd4xyCWiis5BdoY3u6ygN0=; b=WqCApiFlSAiUPNlCdHew+uLPa1lVr/6mbN8E8QeZsv4MDrd3eNrFC4H6oB79uwnD7q KewL7Q1to4quL/RrHyuLz4X/E35xLc3IVi5jNH73yJFpji3jAf4o7JQun5hN1ywwkOr7 cqM/X+cExk/HN7n2C+sABD8K9lUK0/t26BV7ekWAtqHQEP5L4o6SqTlHJ1WKv2DN981f s+g/mOKUkKtI/98FeATrfBPp997QxCShHJkCRYY31JzP0NEUNpFYpM4CfJFGzMS/QBJI cye+Hkez7FNPyemRgKshcsqiF4S5Uxg+hLxRYpMt11+oF/zRF2OkHhZMs4AeuEvW85Um ONSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iQkLw7e7jDGRvqEWGlEj0fd4xyCWiis5BdoY3u6ygN0=; b=ZWvS3NUkJk+Mt1zMUzqtEv76OgZYHkSzvnnB6Qsxc5JjzSsuDxLfRxqzL9VwwHzj3E oSRtrweLuwfZysgM5OHTFeeYkT0CoNrcoNYwdilxW9CQLLKFKzt6z0KKh5x5zjIbJXmN IytjigIM+dK5veUfA8i9bnxieeepYjgjl0H3FxLiYvKfAQubclP+Cq4lDYJXuKt9ewq9 jiVZGayzMUik5roz1d/llBp113RYLCfnvoVxEc+DC9iwCd+Dk2OaUVJJ9DZ/pRo/ISls vAlZW46j7HSlwzoSMDA8Om6/QC7R5HTeA4lSn+iqTLLev8NuI1q7lkuMo3TCWsudcvZL hAIw== X-Gm-Message-State: AElRT7Eoat/lW7OjGHtemZYA1ex3V2Yye+Wk1teZjFaQJPMeF4MlhUIu ltaAOiLs1Y0ddWg4gYhj2ZnbI8PuFv4= X-Google-Smtp-Source: AG47ELvLgYxB+sZTzfLZOKOVy1kEblBPc3yaZ9a/wXZIHXFvLkEWAVtWaW5JaIWGqzpV4iLP+wbcOQ== X-Received: by 2002:a17:902:167:: with SMTP id 94-v6mr3389712plb.294.1521229340566; Fri, 16 Mar 2018 12:42:20 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Fri, 16 Mar 2018 12:41:02 -0700 Message-Id: <1521229281-73637-6-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1521229281-73637-1-git-send-email-mjc@sifive.com> References: <1521229281-73637-1-git-send-email-mjc@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH v3 05/24] RISC-V: Remove identity_translate from load_elf X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 When load_elf is called with NULL as an argument to the address translate callback, it does an identity translation. This commit removes the redundant identity_translate callback. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/sifive_e.c | 7 +------ hw/riscv/sifive_u.c | 7 +------ hw/riscv/spike.c | 7 +------ hw/riscv/virt.c | 7 +------ 4 files changed, 4 insertions(+), 24 deletions(-) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 19eca36..09c9d49 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -82,16 +82,11 @@ static void copy_le32_to_phys(hwaddr pa, uint32_t *rom,= size_t len) } } =20 -static uint64_t identity_translate(void *opaque, uint64_t addr) -{ - return addr; -} - static uint64_t load_kernel(const char *kernel_filename) { uint64_t kernel_entry, kernel_high; =20 - if (load_elf(kernel_filename, identity_translate, NULL, + if (load_elf(kernel_filename, NULL, NULL, &kernel_entry, NULL, &kernel_high, 0, ELF_MACHINE, 1, 0) < 0) { error_report("qemu: could not load kernel '%s'", kernel_filename); diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index f3f7615..6116c38 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -68,16 +68,11 @@ static void copy_le32_to_phys(hwaddr pa, uint32_t *rom,= size_t len) } } =20 -static uint64_t identity_translate(void *opaque, uint64_t addr) -{ - return addr; -} - static uint64_t load_kernel(const char *kernel_filename) { uint64_t kernel_entry, kernel_high; =20 - if (load_elf(kernel_filename, identity_translate, NULL, + if (load_elf(kernel_filename, NULL, NULL, &kernel_entry, NULL, &kernel_high, 0, ELF_MACHINE, 1, 0) < 0) { error_report("qemu: could not load kernel '%s'", kernel_filename); diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 4c233ec..7710333 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -59,16 +59,11 @@ static void copy_le32_to_phys(hwaddr pa, uint32_t *rom,= size_t len) } } =20 -static uint64_t identity_translate(void *opaque, uint64_t addr) -{ - return addr; -} - static uint64_t load_kernel(const char *kernel_filename) { uint64_t kernel_entry, kernel_high; =20 - if (load_elf_ram_sym(kernel_filename, identity_translate, NULL, + if (load_elf_ram_sym(kernel_filename, NULL, NULL, &kernel_entry, NULL, &kernel_high, 0, ELF_MACHINE, 1, 0, NULL, true, htif_symbol_callback) < 0) { error_report("qemu: could not load kernel '%s'", kernel_filename); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 0d101fc..f8c19b4 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -62,16 +62,11 @@ static void copy_le32_to_phys(hwaddr pa, uint32_t *rom,= size_t len) } } =20 -static uint64_t identity_translate(void *opaque, uint64_t addr) -{ - return addr; -} - static uint64_t load_kernel(const char *kernel_filename) { uint64_t kernel_entry, kernel_high; =20 - if (load_elf(kernel_filename, identity_translate, NULL, + if (load_elf(kernel_filename, NULL, NULL, &kernel_entry, NULL, &kernel_high, 0, ELF_MACHINE, 1, 0) < 0) { error_report("qemu: could not load kernel '%s'", kernel_filename); --=20 2.7.0 From nobody Sat Oct 25 11:05:05 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521229643346992.6486650718624; Fri, 16 Mar 2018 12:47:23 -0700 (PDT) Received: from localhost ([::1]:59220 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvJy-0002js-0l for importer@patchew.org; Fri, 16 Mar 2018 15:47:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40244) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvFA-0007LR-4W for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ewvF8-0003jB-Qi for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:24 -0400 Received: from mail-pl0-x242.google.com ([2607:f8b0:400e:c01::242]:33535) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ewvF8-0003iv-Ir for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:22 -0400 Received: by mail-pl0-x242.google.com with SMTP id c11-v6so6503425plo.0 for ; Fri, 16 Mar 2018 12:42:22 -0700 (PDT) Received: from monty.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id k24sm13780469pff.77.2018.03.16.12.42.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 16 Mar 2018 12:42:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KXs31ZQPDLR7Vw784vZDJ7FehxZMGqH0wnzWcDgDVRA=; b=WatYnqh8Aiv9rEanvO+6sDETTOBGIwbAmI9PRRHm2mY/ass3UzpOgxL/2qyZUxzR00 R6zLjESFMZIT8U98DxPqCmz0DxOwAfqzH+uA7Cs7n9AY0BKW1RPj7G02tdrxY1micKEA rkf4cXoEPmxIRs1XFYZueqAp1lRcvbUcbGLquw708qe8Ke5v5gwZ0OD7TCS6FQbwk3Ih Oa41RdOhgQwtOpynW8vFgcy9pBM7wgZRqunz6wIBnkj+K8VLPJyR0OYLQOnzTIOUgQkl JcjzhtILxckneqZJjXDOJjNkjyuUOXEpATID+08kQ7L5SX71g50Iinay7lJ1Yg0a7ME/ sw5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KXs31ZQPDLR7Vw784vZDJ7FehxZMGqH0wnzWcDgDVRA=; b=DYD7/D2vE+g5ui8WIH8i/NUEol89/cPHDhEBwXwGzSVvi3AbtJBJJ3HUV4Tca/xP2q 5ZNDW+GoZbQNbjv5kYbV+oQreK/VjdyvIX97vAy+hNFxfFzZHFCpcOSL/hwSng+zFxnk wed9scyNdXBLWq3gAy03nxH98bDJqhMRRkyotFoE3KtcrqiYWDdBSjqoWxm+j7PiQxY0 OciPxUPzz4W0BnXrGoYcUteBXtxWiW/bs0nd3Tfk5fqnkoOwWNXcUXrzT985VBvH8ZKX o950H3arDE6CxhCorlzWhzfb/RW5SDMM35Utgnp+Z2nN0NxEv3P9B8goq4a8DiuOfVyP hOvg== X-Gm-Message-State: AElRT7FOGjQI0FMwmHSBEteS6GtIAlo0uiS7qWBcYWznTxuhXvA148Gn h/PWCy14j07uoZzF27d4quiDHJBt/CA= X-Google-Smtp-Source: AG47ELssCccKoXr0bHcg1yFxeOiTlGubZBUY+3RneN00TrqBrjUgZz1myO754x9EYu5GJV8HBOPk6A== X-Received: by 2002:a17:902:5957:: with SMTP id e23-v6mr3265330plj.323.1521229341519; Fri, 16 Mar 2018 12:42:21 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Fri, 16 Mar 2018 12:41:03 -0700 Message-Id: <1521229281-73637-7-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1521229281-73637-1-git-send-email-mjc@sifive.com> References: <1521229281-73637-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH v3 06/24] RISC-V: Mark ROM read-only after copying in code X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The sifive_u machine already marks its ROM readonly. This fixes the remaining boards. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 9 +++++---- hw/riscv/spike.c | 18 ++++++++++-------- hw/riscv/virt.c | 7 ++++--- include/hw/riscv/spike.h | 8 -------- 4 files changed, 19 insertions(+), 23 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 6116c38..25df16c 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -223,7 +223,7 @@ static void riscv_sifive_u_init(MachineState *machine) SiFiveUState *s =3D g_new0(SiFiveUState, 1); MemoryRegion *sys_memory =3D get_system_memory(); MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); - MemoryRegion *boot_rom =3D g_new(MemoryRegion, 1); + MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); =20 /* Initialize SOC */ object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY); @@ -246,10 +246,10 @@ static void riscv_sifive_u_init(MachineState *machine) create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); =20 /* boot rom */ - memory_region_init_ram(boot_rom, NULL, "riscv.sifive.u.mrom", + memory_region_init_ram(mask_rom, NULL, "riscv.sifive.u.mrom", memmap[SIFIVE_U_MROM].base, &error_fatal); - memory_region_set_readonly(boot_rom, true); - memory_region_add_subregion(sys_memory, 0x0, boot_rom); + memory_region_set_readonly(mask_rom, true); + memory_region_add_subregion(sys_memory, 0x0, mask_rom); =20 if (machine->kernel_filename) { load_kernel(machine->kernel_filename); @@ -279,6 +279,7 @@ static void riscv_sifive_u_init(MachineState *machine) qemu_fdt_dumpdtb(s->fdt, s->fdt_size); cpu_physical_memory_write(memmap[SIFIVE_U_MROM].base + sizeof(reset_vec), s->fdt, s->fdt_size); + memory_region_set_readonly(mask_rom, true); =20 /* MMIO */ s->plic =3D sifive_plic_create(memmap[SIFIVE_U_PLIC].base, diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 7710333..74edf33 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -173,7 +173,7 @@ static void spike_v1_10_0_board_init(MachineState *mach= ine) SpikeState *s =3D g_new0(SpikeState, 1); MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); - MemoryRegion *boot_rom =3D g_new(MemoryRegion, 1); + MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); =20 /* Initialize SOC */ object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY); @@ -196,9 +196,9 @@ static void spike_v1_10_0_board_init(MachineState *mach= ine) create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); =20 /* boot rom */ - memory_region_init_ram(boot_rom, NULL, "riscv.spike.bootrom", + memory_region_init_ram(mask_rom, NULL, "riscv.spike.mrom", s->fdt_size + 0x2000, &error_fatal); - memory_region_add_subregion(system_memory, 0x0, boot_rom); + memory_region_add_subregion(system_memory, 0x0, mask_rom); =20 if (machine->kernel_filename) { load_kernel(machine->kernel_filename); @@ -228,9 +228,10 @@ static void spike_v1_10_0_board_init(MachineState *mac= hine) qemu_fdt_dumpdtb(s->fdt, s->fdt_size); cpu_physical_memory_write(memmap[SPIKE_MROM].base + sizeof(reset_vec), s->fdt, s->fdt_size); + memory_region_set_readonly(mask_rom, true); =20 /* initialize HTIF using symbols found in load_kernel */ - htif_mm_init(system_memory, boot_rom, &s->soc.harts[0].env, serial_hds= [0]); + htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hds= [0]); =20 /* Core Local Interruptor (timer and IPI) */ sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size, @@ -244,7 +245,7 @@ static void spike_v1_09_1_board_init(MachineState *mach= ine) SpikeState *s =3D g_new0(SpikeState, 1); MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); - MemoryRegion *boot_rom =3D g_new(MemoryRegion, 1); + MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); =20 /* Initialize SOC */ object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY); @@ -264,9 +265,9 @@ static void spike_v1_09_1_board_init(MachineState *mach= ine) main_mem); =20 /* boot rom */ - memory_region_init_ram(boot_rom, NULL, "riscv.spike.bootrom", + memory_region_init_ram(mask_rom, NULL, "riscv.spike.mrom", 0x40000, &error_fatal); - memory_region_add_subregion(system_memory, 0x0, boot_rom); + memory_region_add_subregion(system_memory, 0x0, mask_rom); =20 if (machine->kernel_filename) { load_kernel(machine->kernel_filename); @@ -325,9 +326,10 @@ static void spike_v1_09_1_board_init(MachineState *mac= hine) /* copy in the config string */ cpu_physical_memory_write(memmap[SPIKE_MROM].base + sizeof(reset_vec), config_string, config_string_len); + memory_region_set_readonly(mask_rom, true); =20 /* initialize HTIF using symbols found in load_kernel */ - htif_mm_init(system_memory, boot_rom, &s->soc.harts[0].env, serial_hds= [0]); + htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hds= [0]); =20 /* Core Local Interruptor (timer and IPI) */ sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size, diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index f8c19b4..f1e3641 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -270,7 +270,7 @@ static void riscv_virt_board_init(MachineState *machine) RISCVVirtState *s =3D g_new0(RISCVVirtState, 1); MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); - MemoryRegion *boot_rom =3D g_new(MemoryRegion, 1); + MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); char *plic_hart_config; size_t plic_hart_config_len; int i; @@ -296,9 +296,9 @@ static void riscv_virt_board_init(MachineState *machine) create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); =20 /* boot rom */ - memory_region_init_ram(boot_rom, NULL, "riscv_virt_board.bootrom", + memory_region_init_ram(mask_rom, NULL, "riscv_virt_board.mrom", s->fdt_size + 0x2000, &error_fatal); - memory_region_add_subregion(system_memory, 0x0, boot_rom); + memory_region_add_subregion(system_memory, 0x0, mask_rom); =20 if (machine->kernel_filename) { uint64_t kernel_entry =3D load_kernel(machine->kernel_filename); @@ -339,6 +339,7 @@ static void riscv_virt_board_init(MachineState *machine) qemu_fdt_dumpdtb(s->fdt, s->fdt_size); cpu_physical_memory_write(memmap[VIRT_MROM].base + sizeof(reset_vec), s->fdt, s->fdt_size); + memory_region_set_readonly(mask_rom, true); =20 /* create PLIC hart topology configuration string */ plic_hart_config_len =3D (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpu= s; diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h index d85a64e..179b6cf 100644 --- a/include/hw/riscv/spike.h +++ b/include/hw/riscv/spike.h @@ -22,20 +22,12 @@ #define TYPE_RISCV_SPIKE_V1_09_1_BOARD "riscv.spike_v1_9_1" #define TYPE_RISCV_SPIKE_V1_10_0_BOARD "riscv.spike_v1_10" =20 -#define SPIKE(obj) \ - OBJECT_CHECK(SpikeState, (obj), TYPE_RISCV_SPIKE_BOARD) - typedef struct { - /*< private >*/ - SysBusDevice parent_obj; - - /*< public >*/ RISCVHartArrayState soc; void *fdt; int fdt_size; } SpikeState; =20 - enum { SPIKE_MROM, SPIKE_CLINT, --=20 2.7.0 From nobody Sat Oct 25 11:05:05 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 152122964768388.65805783420421; Fri, 16 Mar 2018 12:47:27 -0700 (PDT) Received: from localhost ([::1]:59219 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvJv-0002hW-F1 for importer@patchew.org; Fri, 16 Mar 2018 15:47:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40261) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvFB-0007N5-D7 for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ewvF9-0003jX-Tw for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:25 -0400 Received: from mail-pl0-x241.google.com ([2607:f8b0:400e:c01::241]:39511) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ewvF9-0003jN-Lw for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:23 -0400 Received: by mail-pl0-x241.google.com with SMTP id k22-v6so5671363pls.6 for ; Fri, 16 Mar 2018 12:42:23 -0700 (PDT) Received: from monty.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id k24sm13780469pff.77.2018.03.16.12.42.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 16 Mar 2018 12:42:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=padGfaTjE2O1uLxXu2zV1PLt8Xu8ywDzhXT0Yc4WBlY=; b=bxyKdXbST7Fi+ZiNGxqyUZI+OgEKpTQlyMOjUxwOb6m3fLs0sOOrfo8spojzwlfJCo BpNYVJD4fm88VyLBUQW0xkSo1eTzaqw6/1QRs9i49YIWm6+n0lZ7VE1Ej/MvAARKPPUS jSlPBqtclCDOEt1jcFX+qDSpZevsZ8mQsaasqEsV719euuukUTgE3BL1C0tN/2gVafYf Sd3dGCxQIoJbGEUM4VJnwzEXd3oO60BeL9UuUitBgdn6hH4Y/6UfvQCpurCoiNEY9xBd QAM3peGKc/O9j1vsfpvriiO5CuChQW6a9fWZWQ/OhShRvMiLDefKEabyZm+pAt9ZT8zz pLzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=padGfaTjE2O1uLxXu2zV1PLt8Xu8ywDzhXT0Yc4WBlY=; b=sH3RPSFkf2lsHrUxHykftYRhPbEbPnMNrh2eCW3XzXYQAnq691IUVPRTnC/PwAuUjl qmii2on/18Ol3yxXXR1IASxjNBSn/GRpuNzfyM6oPWsbtYnv5Ki3uw78gXRxlhK1Tqnv wfsZGQa7GunyweBn5/Bq3xVERzVtRwswmf6Z+fqcT7MXmVhkmFyYza/GSa0wvM+MmDg9 p7tIKxwACePG8VNCofcd7pdVnPX7RlhTd2USyqJG9i0MW6f5eAeJPRybKm2rayVEHidL ib3cRDPmYu/o9dQdI+grT1ZYJIzGvRTey9RYwk5DGSdx+CYmmOx4DaRIfg21e5+D6M52 Z7wg== X-Gm-Message-State: AElRT7GYpO/e3jAnnTd/9UoI9UrwpO9ZeneENsLot5XPFcZIjJKHMZza SscjLIeLAt1Lof0B/KHsPNs4I/iEyt4= X-Google-Smtp-Source: AG47ELvdfal69wiiOdOR7Hqb0MbpeGfoGQtRvaNfrHQ2hQZpAiRYdgPAqpeuCdv/XU2uCmZCupV5aA== X-Received: by 2002:a17:902:464:: with SMTP id 91-v6mr3334385ple.126.1521229342587; Fri, 16 Mar 2018 12:42:22 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Fri, 16 Mar 2018 12:41:04 -0700 Message-Id: <1521229281-73637-8-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1521229281-73637-1-git-send-email-mjc@sifive.com> References: <1521229281-73637-1-git-send-email-mjc@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::241 Subject: [Qemu-devel] [PATCH v3 07/24] RISC-V: Remove unused class definitions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Removes a whole lot of unnecessary boilerplate code. Machines don't need to be objects. The expansion of the SOC object model for the RISC-V machines will happen in the future as SiFive plans to add their FE310 and FU540 SOCs to QEMU. However, it seems that this present boilerplate is complete unnecessary. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/riscv_hart.c | 6 ------ hw/riscv/sifive_e.c | 25 ------------------------- hw/riscv/sifive_u.c | 25 ------------------------- hw/riscv/spike.c | 20 -------------------- hw/riscv/virt.c | 25 ------------------------- include/hw/riscv/sifive_e.h | 5 ----- include/hw/riscv/sifive_u.h | 5 ----- include/hw/riscv/spike.h | 7 ++++--- include/hw/riscv/virt.h | 5 ----- 9 files changed, 4 insertions(+), 119 deletions(-) diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index 14e3c18..75ba7ed 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -68,16 +68,10 @@ static void riscv_harts_class_init(ObjectClass *klass, = void *data) dc->realize =3D riscv_harts_realize; } =20 -static void riscv_harts_init(Object *obj) -{ - /* RISCVHartArrayState *s =3D SIFIVE_COREPLEX(obj); */ -} - static const TypeInfo riscv_harts_info =3D { .name =3D TYPE_RISCV_HART_ARRAY, .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(RISCVHartArrayState), - .instance_init =3D riscv_harts_init, .class_init =3D riscv_harts_class_init, }; =20 diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 09c9d49..4872b68 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -194,24 +194,6 @@ static void riscv_sifive_e_init(MachineState *machine) } } =20 -static int riscv_sifive_e_sysbus_device_init(SysBusDevice *sysbusdev) -{ - return 0; -} - -static void riscv_sifive_e_class_init(ObjectClass *klass, void *data) -{ - SysBusDeviceClass *k =3D SYS_BUS_DEVICE_CLASS(klass); - k->init =3D riscv_sifive_e_sysbus_device_init; -} - -static const TypeInfo riscv_sifive_e_device =3D { - .name =3D TYPE_SIFIVE_E, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(SiFiveEState), - .class_init =3D riscv_sifive_e_class_init, -}; - static void riscv_sifive_e_machine_init(MachineClass *mc) { mc->desc =3D "RISC-V Board compatible with SiFive E SDK"; @@ -220,10 +202,3 @@ static void riscv_sifive_e_machine_init(MachineClass *= mc) } =20 DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init) - -static void riscv_sifive_e_register_types(void) -{ - type_register_static(&riscv_sifive_e_device); -} - -type_init(riscv_sifive_e_register_types); diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 25df16c..083043a 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -302,31 +302,6 @@ static void riscv_sifive_u_init(MachineState *machine) SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); } =20 -static int riscv_sifive_u_sysbus_device_init(SysBusDevice *sysbusdev) -{ - return 0; -} - -static void riscv_sifive_u_class_init(ObjectClass *klass, void *data) -{ - SysBusDeviceClass *k =3D SYS_BUS_DEVICE_CLASS(klass); - k->init =3D riscv_sifive_u_sysbus_device_init; -} - -static const TypeInfo riscv_sifive_u_device =3D { - .name =3D TYPE_SIFIVE_U, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(SiFiveUState), - .class_init =3D riscv_sifive_u_class_init, -}; - -static void riscv_sifive_u_register_types(void) -{ - type_register_static(&riscv_sifive_u_device); -} - -type_init(riscv_sifive_u_register_types); - static void riscv_sifive_u_machine_init(MachineClass *mc) { mc->desc =3D "RISC-V Board compatible with SiFive U SDK"; diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 74edf33..64e585e 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -336,18 +336,6 @@ static void spike_v1_09_1_board_init(MachineState *mac= hine) smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); } =20 -static const TypeInfo spike_v_1_09_1_device =3D { - .name =3D TYPE_RISCV_SPIKE_V1_09_1_BOARD, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(SpikeState), -}; - -static const TypeInfo spike_v_1_10_0_device =3D { - .name =3D TYPE_RISCV_SPIKE_V1_10_0_BOARD, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(SpikeState), -}; - static void spike_v1_09_1_machine_init(MachineClass *mc) { mc->desc =3D "RISC-V Spike Board (Privileged ISA v1.9.1)"; @@ -365,11 +353,3 @@ static void spike_v1_10_0_machine_init(MachineClass *m= c) =20 DEFINE_MACHINE("spike_v1.9.1", spike_v1_09_1_machine_init) DEFINE_MACHINE("spike_v1.10", spike_v1_10_0_machine_init) - -static void riscv_spike_board_register_types(void) -{ - type_register_static(&spike_v_1_09_1_device); - type_register_static(&spike_v_1_10_0_device); -} - -type_init(riscv_spike_board_register_types); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index f1e3641..5913100 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -380,24 +380,6 @@ static void riscv_virt_board_init(MachineState *machin= e) serial_hds[0], DEVICE_LITTLE_ENDIAN); } =20 -static int riscv_virt_board_sysbus_device_init(SysBusDevice *sysbusdev) -{ - return 0; -} - -static void riscv_virt_board_class_init(ObjectClass *klass, void *data) -{ - SysBusDeviceClass *k =3D SYS_BUS_DEVICE_CLASS(klass); - k->init =3D riscv_virt_board_sysbus_device_init; -} - -static const TypeInfo riscv_virt_board_device =3D { - .name =3D TYPE_RISCV_VIRT_BOARD, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(RISCVVirtState), - .class_init =3D riscv_virt_board_class_init, -}; - static void riscv_virt_board_machine_init(MachineClass *mc) { mc->desc =3D "RISC-V VirtIO Board (Privileged ISA v1.10)"; @@ -406,10 +388,3 @@ static void riscv_virt_board_machine_init(MachineClass= *mc) } =20 DEFINE_MACHINE("virt", riscv_virt_board_machine_init) - -static void riscv_virt_board_register_types(void) -{ - type_register_static(&riscv_virt_board_device); -} - -type_init(riscv_virt_board_register_types); diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h index 0aebc57..12ad6d2 100644 --- a/include/hw/riscv/sifive_e.h +++ b/include/hw/riscv/sifive_e.h @@ -19,11 +19,6 @@ #ifndef HW_SIFIVE_E_H #define HW_SIFIVE_E_H =20 -#define TYPE_SIFIVE_E "riscv.sifive_e" - -#define SIFIVE_E(obj) \ - OBJECT_CHECK(SiFiveEState, (obj), TYPE_SIFIVE_E) - typedef struct SiFiveEState { /*< private >*/ SysBusDevice parent_obj; diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index be38aa0..94a3905 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -19,11 +19,6 @@ #ifndef HW_SIFIVE_U_H #define HW_SIFIVE_U_H =20 -#define TYPE_SIFIVE_U "riscv.sifive_u" - -#define SIFIVE_U(obj) \ - OBJECT_CHECK(SiFiveUState, (obj), TYPE_SIFIVE_U) - typedef struct SiFiveUState { /*< private >*/ SysBusDevice parent_obj; diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h index 179b6cf..8410430 100644 --- a/include/hw/riscv/spike.h +++ b/include/hw/riscv/spike.h @@ -19,10 +19,11 @@ #ifndef HW_SPIKE_H #define HW_SPIKE_H =20 -#define TYPE_RISCV_SPIKE_V1_09_1_BOARD "riscv.spike_v1_9_1" -#define TYPE_RISCV_SPIKE_V1_10_0_BOARD "riscv.spike_v1_10" - typedef struct { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ RISCVHartArrayState soc; void *fdt; int fdt_size; diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 655e85d..b91a412 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -19,10 +19,6 @@ #ifndef HW_VIRT_H #define HW_VIRT_H =20 -#define TYPE_RISCV_VIRT_BOARD "riscv.virt" -#define VIRT(obj) \ - OBJECT_CHECK(RISCVVirtState, (obj), TYPE_RISCV_VIRT_BOARD) - typedef struct { /*< private >*/ SysBusDevice parent_obj; @@ -45,7 +41,6 @@ enum { VIRT_DRAM }; =20 - enum { UART0_IRQ =3D 10, VIRTIO_IRQ =3D 1, /* 1 to 8 */ --=20 2.7.0 From nobody Sat Oct 25 11:05:05 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521229644186539.5300950468028; Fri, 16 Mar 2018 12:47:24 -0700 (PDT) Received: from localhost ([::1]:59221 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvJy-0002ko-Va for importer@patchew.org; Fri, 16 Mar 2018 15:47:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40272) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvFC-0007OO-Hn for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ewvFB-0003kC-5e for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:26 -0400 Received: from mail-pl0-x243.google.com ([2607:f8b0:400e:c01::243]:33536) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ewvFA-0003jo-UF for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:25 -0400 Received: by mail-pl0-x243.google.com with SMTP id c11-v6so6503487plo.0 for ; Fri, 16 Mar 2018 12:42:24 -0700 (PDT) Received: from monty.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id k24sm13780469pff.77.2018.03.16.12.42.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 16 Mar 2018 12:42:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0WUlW31X3LYFA5HCImPfRKE4VNH6Gy9yyTrhlUghh28=; b=Y679QcZUzMZMw2NEI9IND/xhuyhUwEWpDmKrh3RqsytetorxwOHi4S9CpD2W9xapNv gqW45o2PvmPvRW6UCCjDcCBPPZwrr0aoweAeDWyg3XlGzGLXENzHzfbh2EkTd89KNjgR M03TYhrQXDanmi/9WkK/sMLC2+GeWUCL/Ug6nmfH2GI0V+Jww3FPlcMG3Gsn5qHbb7/j DML8N53jQD7P7lkPw1WwU+uBynp3+ppXu9v6XXnAarycs2kDIou44jFi/6RGBtgAUlrT qTb6Wv8IKVJaB3ZBFruEI1SByxDXkwVEkAUdjLntaDwlatMpzGKY2B4gvSInlE+Rcz+l vQJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0WUlW31X3LYFA5HCImPfRKE4VNH6Gy9yyTrhlUghh28=; b=GkfbyHOT18GZJTNo1RNK5qe/1I2fRrrRUWJX+Ehr+SZHbVtWJtDaNmRUWco2xFwdxj rseVeYJIIHguoAP/Ab2LA5cjqu1NcfcOLf0wKWM7I6sBkzBNnZzI1mveyFoLB8BFdT3T dLcl8SAZk7Os+fP0H1BspEolAqL+uyhoGt1qmgcBvCJ6Z+21xVMa9PrscSLCRnEwOSBD ktxK8mSYbRTkCKLE9iN7fwrRTIIeAMN1WXkIqadN1xgL2fmpF6aMAw4WTSR6hLS1gQgn CyvaX7o8Nel9/mVhcu6L6toGfQaQ3D021Hifi37U6naoDFGf+qrHCA2+xxjk6QP1rVfg eUEw== X-Gm-Message-State: AElRT7FsO3jP0oRbhrsK7cQKC9Ozufhk/DeCORMoGnBt1aMmGCnNBI8v dRoU5LaWZEPr8CkqYXRKoIxCx3utd8c= X-Google-Smtp-Source: AG47ELsYb9vMGz2U+AFT/CoeWzCP+j5H2YQ/cjk6xSWgcBs3H/sP4WoQX8SLTkCWe2FxRAmTsEH51g== X-Received: by 2002:a17:902:5785:: with SMTP id l5-v6mr3317603pli.386.1521229343682; Fri, 16 Mar 2018 12:42:23 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Fri, 16 Mar 2018 12:41:05 -0700 Message-Id: <1521229281-73637-9-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1521229281-73637-1-git-send-email-mjc@sifive.com> References: <1521229281-73637-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PATCH v3 08/24] RISC-V: Make sure rom has space for fdt X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Remove a potential buffer overflow (not seen in practice). Perhaps cpu_physical_memory_write already has bound checks. This change however makes space for the maximum device tree size and adds an explicit bounds check and error message. It doesn't trigger, but it may help in the future if the device-tree size is exceeded. e.g. large bootargs. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 20 ++++++++++++-------- hw/riscv/spike.c | 16 +++++++++++----- hw/riscv/virt.c | 13 +++++++++---- 3 files changed, 32 insertions(+), 17 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 083043a..57b4f4f 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -52,7 +52,7 @@ static const struct MemmapEntry { hwaddr size; } sifive_u_memmap[] =3D { [SIFIVE_U_DEBUG] =3D { 0x0, 0x100 }, - [SIFIVE_U_MROM] =3D { 0x1000, 0x2000 }, + [SIFIVE_U_MROM] =3D { 0x1000, 0x11000 }, [SIFIVE_U_CLINT] =3D { 0x2000000, 0x10000 }, [SIFIVE_U_PLIC] =3D { 0xc000000, 0x4000000 }, [SIFIVE_U_UART0] =3D { 0x10013000, 0x1000 }, @@ -221,7 +221,7 @@ static void riscv_sifive_u_init(MachineState *machine) const struct MemmapEntry *memmap =3D sifive_u_memmap; =20 SiFiveUState *s =3D g_new0(SiFiveUState, 1); - MemoryRegion *sys_memory =3D get_system_memory(); + MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); =20 @@ -239,7 +239,7 @@ static void riscv_sifive_u_init(MachineState *machine) /* register RAM */ memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram", machine->ram_size, &error_fatal); - memory_region_add_subregion(sys_memory, memmap[SIFIVE_U_DRAM].base, + memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base, main_mem); =20 /* create device tree */ @@ -247,9 +247,9 @@ static void riscv_sifive_u_init(MachineState *machine) =20 /* boot rom */ memory_region_init_ram(mask_rom, NULL, "riscv.sifive.u.mrom", - memmap[SIFIVE_U_MROM].base, &error_fatal); - memory_region_set_readonly(mask_rom, true); - memory_region_add_subregion(sys_memory, 0x0, mask_rom); + memmap[SIFIVE_U_MROM].size, &error_fatal); + memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base, + mask_rom); =20 if (machine->kernel_filename) { load_kernel(machine->kernel_filename); @@ -276,6 +276,10 @@ static void riscv_sifive_u_init(MachineState *machine) copy_le32_to_phys(memmap[SIFIVE_U_MROM].base, reset_vec, sizeof(reset_= vec)); =20 /* copy in the device tree */ + if (s->fdt_size >=3D memmap[SIFIVE_U_MROM].size - sizeof(reset_vec)) { + error_report("qemu: not enough space to store device-tree"); + exit(1); + } qemu_fdt_dumpdtb(s->fdt, s->fdt_size); cpu_physical_memory_write(memmap[SIFIVE_U_MROM].base + sizeof(reset_vec), s->fdt, s->fdt_size); @@ -293,9 +297,9 @@ static void riscv_sifive_u_init(MachineState *machine) SIFIVE_U_PLIC_CONTEXT_BASE, SIFIVE_U_PLIC_CONTEXT_STRIDE, memmap[SIFIVE_U_PLIC].size); - sifive_uart_create(sys_memory, memmap[SIFIVE_U_UART0].base, + sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base, serial_hds[0], SIFIVE_PLIC(s->plic)->irqs[SIFIVE_U_UART0_IRQ]); - /* sifive_uart_create(sys_memory, memmap[SIFIVE_U_UART1].base, + /* sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base, serial_hds[1], SIFIVE_PLIC(s->plic)->irqs[SIFIVE_U_UART1_IRQ]); */ sifive_clint_create(memmap[SIFIVE_U_CLINT].base, memmap[SIFIVE_U_CLINT].size, smp_cpus, diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 64e585e..c7d937b 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -46,7 +46,7 @@ static const struct MemmapEntry { hwaddr base; hwaddr size; } spike_memmap[] =3D { - [SPIKE_MROM] =3D { 0x1000, 0x2000 }, + [SPIKE_MROM] =3D { 0x1000, 0x11000 }, [SPIKE_CLINT] =3D { 0x2000000, 0x10000 }, [SPIKE_DRAM] =3D { 0x80000000, 0x0 }, }; @@ -197,8 +197,9 @@ static void spike_v1_10_0_board_init(MachineState *mach= ine) =20 /* boot rom */ memory_region_init_ram(mask_rom, NULL, "riscv.spike.mrom", - s->fdt_size + 0x2000, &error_fatal); - memory_region_add_subregion(system_memory, 0x0, mask_rom); + memmap[SPIKE_MROM].size, &error_fatal); + memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base, + mask_rom); =20 if (machine->kernel_filename) { load_kernel(machine->kernel_filename); @@ -225,6 +226,10 @@ static void spike_v1_10_0_board_init(MachineState *mac= hine) copy_le32_to_phys(memmap[SPIKE_MROM].base, reset_vec, sizeof(reset_vec= )); =20 /* copy in the device tree */ + if (s->fdt_size >=3D memmap[SPIKE_MROM].size - sizeof(reset_vec)) { + error_report("qemu: not enough space to store device-tree"); + exit(1); + } qemu_fdt_dumpdtb(s->fdt, s->fdt_size); cpu_physical_memory_write(memmap[SPIKE_MROM].base + sizeof(reset_vec), s->fdt, s->fdt_size); @@ -266,8 +271,9 @@ static void spike_v1_09_1_board_init(MachineState *mach= ine) =20 /* boot rom */ memory_region_init_ram(mask_rom, NULL, "riscv.spike.mrom", - 0x40000, &error_fatal); - memory_region_add_subregion(system_memory, 0x0, mask_rom); + memmap[SPIKE_MROM].size, &error_fatal); + memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base, + mask_rom); =20 if (machine->kernel_filename) { load_kernel(machine->kernel_filename); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 5913100..d680cbd 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -45,8 +45,8 @@ static const struct MemmapEntry { hwaddr size; } virt_memmap[] =3D { [VIRT_DEBUG] =3D { 0x0, 0x100 }, - [VIRT_MROM] =3D { 0x1000, 0x2000 }, - [VIRT_TEST] =3D { 0x4000, 0x1000 }, + [VIRT_MROM] =3D { 0x1000, 0x11000 }, + [VIRT_TEST] =3D { 0x100000, 0x1000 }, [VIRT_CLINT] =3D { 0x2000000, 0x10000 }, [VIRT_PLIC] =3D { 0xc000000, 0x4000000 }, [VIRT_UART0] =3D { 0x10000000, 0x100 }, @@ -297,8 +297,9 @@ static void riscv_virt_board_init(MachineState *machine) =20 /* boot rom */ memory_region_init_ram(mask_rom, NULL, "riscv_virt_board.mrom", - s->fdt_size + 0x2000, &error_fatal); - memory_region_add_subregion(system_memory, 0x0, mask_rom); + memmap[VIRT_MROM].size, &error_fatal); + memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, + mask_rom); =20 if (machine->kernel_filename) { uint64_t kernel_entry =3D load_kernel(machine->kernel_filename); @@ -336,6 +337,10 @@ static void riscv_virt_board_init(MachineState *machin= e) copy_le32_to_phys(memmap[VIRT_MROM].base, reset_vec, sizeof(reset_vec)= ); =20 /* copy in the device tree */ + if (s->fdt_size >=3D memmap[VIRT_MROM].size - sizeof(reset_vec)) { + error_report("qemu: not enough space to store device-tree"); + exit(1); + } qemu_fdt_dumpdtb(s->fdt, s->fdt_size); cpu_physical_memory_write(memmap[VIRT_MROM].base + sizeof(reset_vec), s->fdt, s->fdt_size); --=20 2.7.0 From nobody Sat Oct 25 11:05:05 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521229830773544.7493220030591; Fri, 16 Mar 2018 12:50:30 -0700 (PDT) Received: from localhost ([::1]:59233 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvMt-0005Ct-JL for importer@patchew.org; Fri, 16 Mar 2018 15:50:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40283) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvFD-0007PD-73 for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ewvFC-0003kd-7E for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:27 -0400 Received: from mail-pl0-x244.google.com ([2607:f8b0:400e:c01::244]:44989) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ewvFC-0003kJ-0u for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:26 -0400 Received: by mail-pl0-x244.google.com with SMTP id 9-v6so6503784ple.11 for ; Fri, 16 Mar 2018 12:42:25 -0700 (PDT) Received: from monty.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id k24sm13780469pff.77.2018.03.16.12.42.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 16 Mar 2018 12:42:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7CfZNEeH8cK/kvjsiUVLVgvJ07eCOI0ZWWcN6NTeFP4=; b=gm6LX102yVJ5D6WUBXFQ/+BvyBg7PRafi9xtelu/9D0E/SSb67PVa8ZtIYUXX2Kbzs IUzGTAI3liUeZb6qoYVlOpbnvhV6+baiiinIqYpU1npcNgRckRPVetOobuBLJL20poPs Ym08EvKQMJ+RmDOHQElXWkKAdGXpQnZmfQ8lVFWwQuuRiYssf6IrlFrNBcgMnInSCbgN UZpaEHxexM5nx1gfHVqP8TuqPlIX/PATyz5kXhCrTYlLVDdzAW9+futfsyg4MZ/fRpjx 9Q1Lc6UFpiTtxAJvy0zkaSuaN5JKAP4mUWb9DaYvLKSe56DfJaXEoLTwAfI+KJet9IhJ 4+pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7CfZNEeH8cK/kvjsiUVLVgvJ07eCOI0ZWWcN6NTeFP4=; b=EDwt6tEwSW7PLsUwetk7PRNftNYEGNwE0Kja7xcOKpZh65jFjIld7ILU+EAO4ogoi9 PP/XymO+XfwtUtYDJaNwfecgfL1ylXekoLhBKu3MXssX57i+gacN04Cl871YFQiL7MFX UQMyV2wHflhfFvu/nS6I4hLppS8VVb5KmKFTRg8R0gzDgy5bS/4Jx2n6mlUyWmiTbL6h W66IUtzAHIltiePUDy3VhhApIX2W95+lcXdv4F5yQIAj7KSu0V0OBD/w9e09Ngf/Ehj/ JKYLYZkEvIu8y2VyxCqI98OQe8iNsc0otHoqeOB7aBgErXmlyXvZENdYG2RvdLnBFCtw QOHQ== X-Gm-Message-State: AElRT7Gmplte2SYcWsigp4BZ3cKTB6R/DIqfcUQYcpRSsj9GclgvvMVK kCZiZkikRwvif/kELQkqukPkauUg7/A= X-Google-Smtp-Source: AG47ELvTl96lUOvsBHBVuAEc/Oa5bu/Y4QPzMzdVacxDXfwzE92sjIxdZBCCabfgJP97LaSQA3E1gw== X-Received: by 2002:a17:902:5609:: with SMTP id h9-v6mr3323521pli.121.1521229344899; Fri, 16 Mar 2018 12:42:24 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Fri, 16 Mar 2018 12:41:06 -0700 Message-Id: <1521229281-73637-10-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1521229281-73637-1-git-send-email-mjc@sifive.com> References: <1521229281-73637-1-git-send-email-mjc@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PATCH v3 09/24] RISC-V: Include intruction hex in disassembly X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 This was added to help debug issues using -d in_asm. It is useful to see the instruction bytes, as one can detect if one is trying to execute ASCII or device-tree magic. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- disas/riscv.c | 39 ++++++++++++++++++++------------------- 1 file changed, 20 insertions(+), 19 deletions(-) diff --git a/disas/riscv.c b/disas/riscv.c index 3c17501..4580308 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -2769,25 +2769,6 @@ static void format_inst(char *buf, size_t buflen, si= ze_t tab, rv_decode *dec) char tmp[64]; const char *fmt; =20 - if (dec->op =3D=3D rv_op_illegal) { - size_t len =3D inst_length(dec->inst); - switch (len) { - case 2: - snprintf(buf, buflen, "(0x%04" PRIx64 ")", dec->inst); - break; - case 4: - snprintf(buf, buflen, "(0x%08" PRIx64 ")", dec->inst); - break; - case 6: - snprintf(buf, buflen, "(0x%012" PRIx64 ")", dec->inst); - break; - default: - snprintf(buf, buflen, "(0x%016" PRIx64 ")", dec->inst); - break; - } - return; - } - fmt =3D opcode_data[dec->op].format; while (*fmt) { switch (*fmt) { @@ -3004,6 +2985,11 @@ disasm_inst(char *buf, size_t buflen, rv_isa isa, ui= nt64_t pc, rv_inst inst) format_inst(buf, buflen, 16, &dec); } =20 +#define INST_FMT_2 "%04" PRIx64 " " +#define INST_FMT_4 "%08" PRIx64 " " +#define INST_FMT_6 "%012" PRIx64 " " +#define INST_FMT_8 "%016" PRIx64 " " + static int print_insn_riscv(bfd_vma memaddr, struct disassemble_info *info, rv_isa is= a) { @@ -3031,6 +3017,21 @@ print_insn_riscv(bfd_vma memaddr, struct disassemble= _info *info, rv_isa isa) } } =20 + switch (len) { + case 2: + (*info->fprintf_func)(info->stream, INST_FMT_2, inst); + break; + case 4: + (*info->fprintf_func)(info->stream, INST_FMT_4, inst); + break; + case 6: + (*info->fprintf_func)(info->stream, INST_FMT_6, inst); + break; + default: + (*info->fprintf_func)(info->stream, INST_FMT_8, inst); + break; + } + disasm_inst(buf, sizeof(buf), isa, memaddr, inst); (*info->fprintf_func)(info->stream, "%s", buf); =20 --=20 2.7.0 From nobody Sat Oct 25 11:05:05 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 152122989513932.998665628755134; Fri, 16 Mar 2018 12:51:35 -0700 (PDT) Received: from localhost ([::1]:59240 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvO1-0006CW-U6 for importer@patchew.org; Fri, 16 Mar 2018 15:51:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40325) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvFH-0007Th-5M for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ewvFD-0003l5-2Z for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:31 -0400 Received: from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:37687) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ewvFC-0003ki-SW for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:26 -0400 Received: by mail-pf0-x242.google.com with SMTP id h11so4548144pfn.4 for ; Fri, 16 Mar 2018 12:42:26 -0700 (PDT) Received: from monty.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id k24sm13780469pff.77.2018.03.16.12.42.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 16 Mar 2018 12:42:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Loi43iu8ZbpA0eJCNpzVAU/Pkr/kAUWZZsWzzFf6NpA=; b=JlYeCZGMlhPrc8j2ouHoG44ui8Ad89HUZ41hk3AR+LKUpzX5lC5eZgEZJDLGgNvDsk +fKLxS6VXwc3o3BOgz+ebR8yYvhX5mFsiWRCsvaGbu5PXfQoZOBH9r2AeMqa+c5P9PSB wtrd67FLBNreAWbZOoSYPAIqAbP6J88eSiSMulGHPgX4JG5kWa+jfGT8wizBttubAzdQ tbaCFuR8vvl9vLvoe7fZRCC6EhMQoZOVE0VuyUvsUgKMEmYbZAGIK00OgtRHCZ3FsqjY y2myt2Q2E+nDe13EuPCqa9Cp5k8GmcfsaeGsnvk/gfP49g7vdf5gH7nf6W82FpeCLUwh /VPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Loi43iu8ZbpA0eJCNpzVAU/Pkr/kAUWZZsWzzFf6NpA=; b=lOmP+P4RyuQJqCyYjDG87DfoOU098cwVv7gyfsptpG2H6HxGxFNhRUFcCGxHGMSP4g WRGGXVzUytfR/D4703t5FGUjxszpVRcn9sSx0AQ5PTY8MVUHUhzPBsu0rIAap0TY/JZh 5xULoI9mhnaxKfBi2qjFpo1faKurS+khlu1xlDamB44Tx41YzZghPpRot3Du/8EfwdbE 0Y/e29fbpsyyM2Kf3AvQk8koWOvZfvCvN5xVQtqZeP6GMSY3Ww+CayBK6GqkhXRY68BG eruADUiM+q3sdSqXxe+mxM4DBze70lGUGqR9WiVYPOfQWCJNqGwqwMjzEw4UZZeO+OW3 gtsQ== X-Gm-Message-State: AElRT7EXsD5vZM0zokIEH7C0d5coludfGKWluofN/LDZBvw7cuvbwBsz MFuTiF0yUEaO388ChijebSyXTFiVljY= X-Google-Smtp-Source: AG47ELuuix078tay+vCQkSZcGHU33jZ2df/biChnu5rOHkn4GsDdl7DLld9fBHRuSqhOSCLAKic/PA== X-Received: by 10.99.42.83 with SMTP id q80mr2415996pgq.115.1521229345824; Fri, 16 Mar 2018 12:42:25 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Fri, 16 Mar 2018 12:41:07 -0700 Message-Id: <1521229281-73637-11-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1521229281-73637-1-git-send-email-mjc@sifive.com> References: <1521229281-73637-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH v3 10/24] RISC-V: Hold rcu_read_lock when accessing memory X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From reading other code that accesses memory regions directly, it appears that the rcu_read_lock needs to be held. Note: the original code for accessing RAM directly was added because there is no other way to use atomic_cmpxchg on guest physical address space. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt --- target/riscv/helper.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/target/riscv/helper.c b/target/riscv/helper.c index 02cbcea..e71633a 100644 --- a/target/riscv/helper.c +++ b/target/riscv/helper.c @@ -209,6 +209,9 @@ restart: as the PTE is no longer valid */ MemoryRegion *mr; hwaddr l =3D sizeof(target_ulong), addr1; + enum { success, translate_fail, restart_walk} action =3D s= uccess; + + rcu_read_lock(); mr =3D address_space_translate(cs->as, pte_addr, &addr1, &l, false); if (memory_access_is_direct(mr, true)) { @@ -222,7 +225,7 @@ restart: target_ulong old_pte =3D atomic_cmpxchg(pte_pa, pte, updated_pte); if (old_pte !=3D pte) { - goto restart; + action =3D restart_walk; } else { pte =3D updated_pte; } @@ -230,7 +233,14 @@ restart: } else { /* misconfigured PTE in ROM (AD bits are not preset) or * PTE is in IO space and can't be updated atomically = */ - return TRANSLATE_FAIL; + action =3D translate_fail; + } + rcu_read_unlock(); + + switch (action) { + case success: break; + case translate_fail: return TRANSLATE_FAIL; + case restart_walk: goto restart; } } =20 --=20 2.7.0 From nobody Sat Oct 25 11:05:05 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521229835632980.1834513918503; Fri, 16 Mar 2018 12:50:35 -0700 (PDT) Received: from localhost ([::1]:59234 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvMz-0005F2-BW for importer@patchew.org; Fri, 16 Mar 2018 15:50:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40326) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvFH-0007Tj-5X for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ewvFE-0003ll-7x for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:31 -0400 Received: from mail-pl0-x242.google.com ([2607:f8b0:400e:c01::242]:44988) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ewvFD-0003lV-Vu for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:28 -0400 Received: by mail-pl0-x242.google.com with SMTP id 9-v6so6503826ple.11 for ; Fri, 16 Mar 2018 12:42:27 -0700 (PDT) Received: from monty.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id k24sm13780469pff.77.2018.03.16.12.42.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 16 Mar 2018 12:42:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8UQ+uSIzoZngR0+Oi4ohUDvu7FmGbnMTnM4v6VLcH4Q=; b=GZhPtMe4xEMVzZwzYPO+WWdJ2L2czb/88EhKsRlADA0JkJQPn4up8mVS3+lnshtU25 B7/YmA2+38Dv/6ml2NoGnpQtH5VxN9UqAvB3depfKk/vJFqrUSI27A9HFz6UeEAawJYC 5KWRM0GhhFJj9o4/Z/q2jr3XdFLDjzoDyQ4JmJs8lenAv22XeehgEBSbmwwdT0tZOuAT msSK0K65YLdTbqRwUDfRLvmJjcIVB16n1kjXV+zZ4slwO7ePdf9odxPmXHRAhx+fsvxE wimcrLhtoaL/3xgOlTzSWIjX36ffqLDRPkncCcRJSum6CdCI0fuD29pIxZ0NiBjw/PsV g/Nw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8UQ+uSIzoZngR0+Oi4ohUDvu7FmGbnMTnM4v6VLcH4Q=; b=QRlXK4/4PaD55AG0VBa24I7vaSN9pZ8NZx5bOdcV2uxUd6yeMboZagIymHyW50q0l6 m1JEMhzpwKqkPXi434VnrYsiBGBXHBKsRhvCTbX8a1P8jHvWQAfaV1wcbMDw0uOcgEC8 BuJ3I3yeJM0GNykEEw6B//2m+T2mYrEilnsr+6ETwb2VPFjUkiaZyCgP3Qql92qA1fQK 2rBhmU0alWlaKBR0hX1GQwBFBp/fjgpdjPCgBfhKe5T2LhcBU3T1I4VOSgbWkmMi4qLV o1xc40mslqAxovQ5aPtGxnbtNvrqpI93b7fZECaxCVbLhUREKEe349S7ablPbTxne3Ah nNVA== X-Gm-Message-State: AElRT7FRKKaaLDdMxLmvAAUrt31+ph6EuJapC+6wlUkXtZHHAq8JwLi2 IQay5D3Oo21AKgZHA6THYdRYjIxGRco= X-Google-Smtp-Source: AG47ELuJFnjBvwFY77/2uYzh+jlEe7xrMjpOjCZeRherwBt5Ct7Tz9b4U2gKssqtPqYaQI2NPlAklw== X-Received: by 2002:a17:902:9a0a:: with SMTP id v10-v6mr3373444plp.35.1521229346917; Fri, 16 Mar 2018 12:42:26 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Fri, 16 Mar 2018 12:41:08 -0700 Message-Id: <1521229281-73637-12-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1521229281-73637-1-git-send-email-mjc@sifive.com> References: <1521229281-73637-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH v3 11/24] RISC-V: Improve page table walker spec compliance X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" - Inline PTE_TABLE check for better readability - Improve readibility of User page U mode and SUM test - Disallow non U mode from fetching from User pages - Add reserved PTE flag check: W or W|X - Add misaligned PPN check - Set READ flag for PTE X flag if mstatus.mxr is in effect - Change access checks from ternary operator to if statements - Improves page walker comments - No measurable performance impact on dd test Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt --- target/riscv/cpu_bits.h | 2 -- target/riscv/helper.c | 59 ++++++++++++++++++++++++++++++++++-----------= ---- 2 files changed, 41 insertions(+), 20 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 64aa097..12b4757 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -407,5 +407,3 @@ #define PTE_SOFT 0x300 /* Reserved for Software */ =20 #define PTE_PPN_SHIFT 10 - -#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) =3D=3D P= TE_V) diff --git a/target/riscv/helper.c b/target/riscv/helper.c index e71633a..523a275 100644 --- a/target/riscv/helper.c +++ b/target/riscv/helper.c @@ -185,16 +185,36 @@ restart: #endif target_ulong ppn =3D pte >> PTE_PPN_SHIFT; =20 - if (PTE_TABLE(pte)) { /* next level of page table */ + if (!(pte & PTE_V)) { + /* Invalid PTE */ + return TRANSLATE_FAIL; + } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { + /* Inner PTE, continue walking */ base =3D ppn << PGSHIFT; - } else if ((pte & PTE_U) ? (mode =3D=3D PRV_S) && !sum : !(mode = =3D=3D PRV_S)) { - break; - } else if (!(pte & PTE_V) || (!(pte & PTE_R) && (pte & PTE_W))) { - break; - } else if (access_type =3D=3D MMU_INST_FETCH ? !(pte & PTE_X) : - access_type =3D=3D MMU_DATA_LOAD ? !(pte & PTE_R) && - !(mxr && (pte & PTE_X)) : !((pte & PTE_R) && (pte & PTE_= W))) { - break; + } else if ((pte & (PTE_R | PTE_W | PTE_X)) =3D=3D PTE_W) { + /* Reserved leaf PTE flags: PTE_W */ + return TRANSLATE_FAIL; + } else if ((pte & (PTE_R | PTE_W | PTE_X)) =3D=3D (PTE_W | PTE_X))= { + /* Reserved leaf PTE flags: PTE_W + PTE_X */ + return TRANSLATE_FAIL; + } else if ((pte & PTE_U) && ((mode !=3D PRV_U) && + (!sum || access_type =3D=3D MMU_INST_FETCH))) { + /* User PTE flags when not U mode and mstatus.SUM is not set, + or the access type is an instruction fetch */ + return TRANSLATE_FAIL; + } else if (ppn & ((1ULL << ptshift) - 1)) { + /* Misasligned PPN */ + return TRANSLATE_FAIL; + } else if (access_type =3D=3D MMU_DATA_LOAD && !((pte & PTE_R) || + ((pte & PTE_X) && mxr))) { + /* Read access check failed */ + return TRANSLATE_FAIL; + } else if (access_type =3D=3D MMU_DATA_STORE && !(pte & PTE_W)) { + /* Write access check failed */ + return TRANSLATE_FAIL; + } else if (access_type =3D=3D MMU_INST_FETCH && !(pte & PTE_X)) { + /* Fetch access check failed */ + return TRANSLATE_FAIL; } else { /* if necessary, set accessed and dirty bits. */ target_ulong updated_pte =3D pte | PTE_A | @@ -202,11 +222,14 @@ restart: =20 /* Page table updates need to be atomic with MTTCG enabled */ if (updated_pte !=3D pte) { - /* if accessed or dirty bits need updating, and the PTE is - * in RAM, then we do so atomically with a compare and swa= p. - * if the PTE is in IO space, then it can't be updated. - * if the PTE changed, then we must re-walk the page table - as the PTE is no longer valid */ + /* + * - if accessed or dirty bits need updating, and the PTE = is + * in RAM, then we do so atomically with a compare and s= wap. + * - if the PTE is in IO space or ROM, then it can't be up= dated + * and we return TRANSLATE_FAIL. + * - if the PTE changed by the time we went to update it, = then + * it is no longer valid and we must re-walk the page ta= ble. + */ MemoryRegion *mr; hwaddr l =3D sizeof(target_ulong), addr1; enum { success, translate_fail, restart_walk} action =3D s= uccess; @@ -249,15 +272,15 @@ restart: target_ulong vpn =3D addr >> PGSHIFT; *physical =3D (ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT; =20 - if ((pte & PTE_R)) { + /* set permissions on the TLB entry */ + if ((pte & PTE_R) || (mode !=3D PRV_U && (pte & PTE_X) && mxr)= ) { *prot |=3D PAGE_READ; } if ((pte & PTE_X)) { *prot |=3D PAGE_EXEC; } - /* only add write permission on stores or if the page - is already dirty, so that we don't miss further - page table walks to update the dirty bit */ + /* add write permission on stores or if the page is already di= rty, + so that we TLB miss on later writes to update the dirty bit= */ if ((pte & PTE_W) && (access_type =3D=3D MMU_DATA_STORE || (pte & PTE_D))) { *prot |=3D PAGE_WRITE; --=20 2.7.0 From nobody Sat Oct 25 11:05:05 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521230006973509.1336706068083; Fri, 16 Mar 2018 12:53:26 -0700 (PDT) Received: from localhost ([::1]:59249 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvPk-0007gi-Mq for importer@patchew.org; Fri, 16 Mar 2018 15:53:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40328) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvFH-0007Tm-6E for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ewvFF-0003mC-49 for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:31 -0400 Received: from mail-pf0-x241.google.com ([2607:f8b0:400e:c00::241]:38196) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ewvFE-0003lt-U8 for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:29 -0400 Received: by mail-pf0-x241.google.com with SMTP id d26so4547801pfn.5 for ; Fri, 16 Mar 2018 12:42:28 -0700 (PDT) Received: from monty.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id k24sm13780469pff.77.2018.03.16.12.42.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 16 Mar 2018 12:42:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=j4IsCu0Ogw4C4VGML3xebQtkhhgEZnHvVT7BhbcJNGc=; b=YNGGAPugIx1UnmMfvIu2f/viNLeUcM3yybV3L4uW8DqPQcOk8zaAzoiMaD70OFXnFl r56gwwYlolTeugVjfgpsuS+aw9NZtSDDHko2qoaL6LFjuXUwT58dPC4Lsb6DlhcvvQJG Fb2aWsXk/UDiv4F3YL8tO73fXXF0+/Z1UbiSetK4y4prwrzzFqXu+uE5T4fO243OopRN 5oW3l0RM1uvij9gq+/gcyBtJtk9tsLwZkL4hDeSCqAONs3TmpSk6+Y4AUD73aIzUOy4T IQtLAU9wbdBNzP1hRF3HPt7Nc26YbukcuC6FSBvrVDTY24OkYk3qxAtHhCG/U8IAfYx3 yGQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=j4IsCu0Ogw4C4VGML3xebQtkhhgEZnHvVT7BhbcJNGc=; b=llZrDQ3jQOWoODM2PZNgZi56i0RyO+qecq6q+4E9oEQC+OI81T/PZcJhPAIlrxQWu2 Q5sBeBxrY4F2ypSwp3rYOuiMpCVq/jYjeGF+2y0RjBXaQmpDOooCPA5EJTLLjpNs5Pqn xvzoPwfc6uqNdFMVEoly09h5ZWTp87Jp6j9Juv85xAkAXq8FUDmTUXXITyqWGYpCqdEF K0sjiddjefGqNynDHADk6S47NqxlTIXcb1/tx2VayonHbAxWh/DBXA2Vo+BMO1WhcWKa V0C7rmD7B1Lc3GuU7csgucO2UtKWF6SpivVYsGzsikaezxhA+OZeKabyLgaO18Ktat1M 9g5g== X-Gm-Message-State: AElRT7GGC4hx5eirISwQhzTZFwbHnE4xJDIASkKFjQax7FAFzhO6NEP7 pvHWC8uTfp0ANXm4FzwXoqpvC8WYbfU= X-Google-Smtp-Source: AG47ELvsEYgE6IR1DbpoIuDypo96efMVubs8g2BDwTMYlWHr0I5aY5sGoDF9fe4Rp/sxGBDA19R6kg== X-Received: by 10.99.126.26 with SMTP id z26mr2406018pgc.132.1521229347950; Fri, 16 Mar 2018 12:42:27 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Fri, 16 Mar 2018 12:41:09 -0700 Message-Id: <1521229281-73637-13-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1521229281-73637-1-git-send-email-mjc@sifive.com> References: <1521229281-73637-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v3 12/24] RISC-V: Update E order and I extension order X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Section 22.8 Subset Naming Convention of the RISC-V ISA Specification defines the canonical order for extensions in the ISA string. It is silent on the position of the E extension however E is a substitute for I so it must come early in the extension list order. A comment is added to state E and I are mutually exclusive, as the E extension will be added to the RISC-V port in the future. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4851890..d2ae56a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -26,7 +26,7 @@ =20 /* RISC-V CPU definitions */ =20 -static const char riscv_exts[26] =3D "IMAFDQECLBJTPVNSUHKORWXYZG"; +static const char riscv_exts[26] =3D "IEMAFDQCLBJTPVNSUHKORWXYZG"; =20 const char * const riscv_int_regnames[] =3D { "zero", "ra ", "sp ", "gp ", "tp ", "t0 ", "t1 ", "t2 ", diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index cff02a2..3a0ca2f 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -71,6 +71,7 @@ #define RV(x) ((target_ulong)1 << (x - 'A')) =20 #define RVI RV('I') +#define RVE RV('E') /* E and I are mutually exclusive */ #define RVM RV('M') #define RVA RV('A') #define RVF RV('F') --=20 2.7.0 From nobody Sat Oct 25 11:05:05 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521230165103369.7169537959851; Fri, 16 Mar 2018 12:56:05 -0700 (PDT) Received: from localhost ([::1]:59270 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvSH-0001iG-T5 for importer@patchew.org; Fri, 16 Mar 2018 15:55:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40331) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvFH-0007Tq-7A for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ewvFG-0003mY-0O for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:31 -0400 Received: from mail-pl0-x244.google.com ([2607:f8b0:400e:c01::244]:46819) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ewvFF-0003mL-Qb for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:29 -0400 Received: by mail-pl0-x244.google.com with SMTP id f5-v6so6484927plj.13 for ; Fri, 16 Mar 2018 12:42:29 -0700 (PDT) Received: from monty.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id k24sm13780469pff.77.2018.03.16.12.42.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 16 Mar 2018 12:42:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BzoWDjqOkLr1gXTgXEqkRe19OYL1d4M1Ffyez2Cfl2s=; b=BZtjWlDwCK9EpjacFJccgVS7vuoNVRrNflVOIKsJaV3jUGtd/n+9Ccg76U6j0SuqpN zFS3fifK7W6xKwhuooLzeIaNxqBmtTyp5kP2a4uVVHa9WwA2RLPKhtHmM6zamiaJYx9c Cwr3VSguXMyPhAYOKOGN7u0cEcDmlciFQAbSN+ITwNPN0k6zwX3wwUD7v8/6y0SqVa1p rkJUf9dbdZf4CUB5Prm/aKsbyU6AYzWYCte8w2J17fe+mAJ3hk1/pCDOzFrSSrF9rcgl u/7BGjf/ryuMwOkwJJaOZFOVtREb8ERAWGntcXKhwukLUY3vMvNN45XeAniUunvZw4b/ K4wA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BzoWDjqOkLr1gXTgXEqkRe19OYL1d4M1Ffyez2Cfl2s=; b=beqhAQV1d0YMdrTqODBkTfZ2uLcPiVOL4m+4LuhhwLlAV5hYPo7iW7kuj/pkLJMQe0 SYqg+koiRi/1jHrWW4U1+zZ5UFuxvfGBo/+DoyZcztSdZmRW/kgx3CRewkxkZcKfw8we Xh+/aJzLJLc8fm7TE5af+fm6j1qmn3hYJEfs6H5ARc0J7WT3pAfEK6ZvpDOFXzvJyFVP Hu1+YZG65YeMam2ERK30Z7NrKJP2z5qVIn9P8lVop9ZecQOWLHdn4leCtLYLTQgNSWeu glHSENvgVDEOEyMRgsP4UveAsm3gGrA2msYcA9CPsdNXVeNnZk4cOj7bZmEkZGP13Ii1 xq1A== X-Gm-Message-State: AElRT7EGJoTAHLV3tkKzhpo8WuIM40/ugVdll/NuxblK26gFHkCHF874 ebCVwJahfe1x5XJWP64aiL0YJBrPe5I= X-Google-Smtp-Source: AG47ELtJbnWK1TYwTQnkiSBDG99/BVNgZzdKqSNsG5mUWCT5426O0/+uKves266fqFaaWzapticVGw== X-Received: by 2002:a17:902:bb8a:: with SMTP id m10-v6mr3322907pls.357.1521229348836; Fri, 16 Mar 2018 12:42:28 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Fri, 16 Mar 2018 12:41:10 -0700 Message-Id: <1521229281-73637-14-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1521229281-73637-1-git-send-email-mjc@sifive.com> References: <1521229281-73637-1-git-send-email-mjc@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PATCH v3 13/24] RISC-V: Make some header guards more specific X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/riscv/spike.h | 4 ++-- include/hw/riscv/virt.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h index 8410430..641b70d 100644 --- a/include/hw/riscv/spike.h +++ b/include/hw/riscv/spike.h @@ -16,8 +16,8 @@ * this program. If not, see . */ =20 -#ifndef HW_SPIKE_H -#define HW_SPIKE_H +#ifndef HW_RISCV_SPIKE_H +#define HW_RISCV_SPIKE_H =20 typedef struct { /*< private >*/ diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index b91a412..3a4f23e 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -16,8 +16,8 @@ * this program. If not, see . */ =20 -#ifndef HW_VIRT_H -#define HW_VIRT_H +#ifndef HW_RISCV_VIRT_H +#define HW_RISCV_VIRT_H =20 typedef struct { /*< private >*/ --=20 2.7.0 From nobody Sat Oct 25 11:05:05 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521230265545118.49865520394042; Fri, 16 Mar 2018 12:57:45 -0700 (PDT) Received: from localhost ([::1]:59279 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvU0-000389-CJ for importer@patchew.org; Fri, 16 Mar 2018 15:57:44 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40335) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvFH-0007UG-Kv for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ewvFG-0003mt-Tr for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:31 -0400 Received: from mail-pl0-x244.google.com ([2607:f8b0:400e:c01::244]:33537) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ewvFG-0003mi-Nu for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:30 -0400 Received: by mail-pl0-x244.google.com with SMTP id c11-v6so6503613plo.0 for ; Fri, 16 Mar 2018 12:42:30 -0700 (PDT) Received: from monty.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id k24sm13780469pff.77.2018.03.16.12.42.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 16 Mar 2018 12:42:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TFCFcsCRDnpWhlR6rxqM+6PUN3Eyxuzs8Kg/VUBrDgg=; b=g2jT+2QAqJFkReOr9fZDgjURvoOp7amqs+jmygln7+pGMBDTM+7HfYkxKMt4EIW/xQ dHtNfW9p4zI3W+2+n6JHl+1PR12/L0iavEiMAoEifdRAQcdDBwEilWPf8acu5YTYpqQZ auXGWywot7YMD9X9aszIsKneRl6PZk4mrtgMkUNxEBcfIOAX7tfY4UnYSfuIjb3RrpRi nJS/nHMWeYx20cnSBp4iTVXA2NQf8bUCb8LqSfpmTLB1kyGGKFpxemcDFq4T607nA0zP meQ5C25SfIHHSYS1OUHzRSZt6hRfGfWRgXbz/VCxyUMv7SnSGNbKN1tRKkOgjdGqCSuH 2GZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TFCFcsCRDnpWhlR6rxqM+6PUN3Eyxuzs8Kg/VUBrDgg=; b=kbRVDCA7VEbKTy0gapp02Xg+AUu1EyZaBPhzBbT6x87RiOzgq5xGSm6ZOy27VBYsW+ tR4JnkKxRzuH0uLGOTBhzMfENgsBnWPSJ13C7pXKO6+8OiefVmpOhBlHHXUtk1vBX0TV wdLlqWhdGCnxoS1me8zyIaaKrTk1yQRl6h/2WuW6+O6mgOGyaDkku4ykWsTTXpwRTT7c I2iz+PYlr0oT550vH9hxa4TJYSPGTzgiN/Bqfsy17GVH6YnMWThj7VB/9KqJAEEE5XEs +HWkOw+2FEt8NT0nHLQEJbQRjdOT761LdcToTIovHnSPOrPDc6G6OceDh2HrwGRk7T2Z A85w== X-Gm-Message-State: AElRT7ErtuRHTRT0Bs2vGFAGAbkVIfXMou1NO+AD+38ZPj4crrD6ce7P pBloiiFKY9RZ0xqZAwXyiWbgnT8gUBc= X-Google-Smtp-Source: AG47ELuZ3/x51iFrLck/fM5VWBica4Fcb1xTOwwLNgpMDfLq636r8qCYpJKE6s3sGjONyO8xuV46bQ== X-Received: by 2002:a17:902:bd8e:: with SMTP id q14-v6mr3364642pls.19.1521229349733; Fri, 16 Mar 2018 12:42:29 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Fri, 16 Mar 2018 12:41:11 -0700 Message-Id: <1521229281-73637-15-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1521229281-73637-1-git-send-email-mjc@sifive.com> References: <1521229281-73637-1-git-send-email-mjc@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PATCH v3 14/24] RISC-V: Make virt header comment title consistent X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/riscv/virt.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 3a4f23e..91163d6 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -1,5 +1,5 @@ /* - * SiFive VirtIO Board + * QEMU RISC-V VirtIO machine interface * * Copyright (c) 2017 SiFive, Inc. * --=20 2.7.0 From nobody Sat Oct 25 11:05:05 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521230373614651.412936088454; Fri, 16 Mar 2018 12:59:33 -0700 (PDT) Received: from localhost ([::1]:59287 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvVf-0004T9-Cn for importer@patchew.org; Fri, 16 Mar 2018 15:59:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40365) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvFI-0007Vj-SS for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ewvFH-0003nh-VM for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:32 -0400 Received: from mail-pf0-x241.google.com ([2607:f8b0:400e:c00::241]:45950) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ewvFH-0003nF-PI for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:31 -0400 Received: by mail-pf0-x241.google.com with SMTP id l27so19580pfk.12 for ; Fri, 16 Mar 2018 12:42:31 -0700 (PDT) Received: from monty.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id k24sm13780469pff.77.2018.03.16.12.42.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 16 Mar 2018 12:42:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=G2UMs8P9dA6Upr72L0xeE/uCH2mdeHNiCiDn7eHqgjA=; b=EfM/xt3VlAsa9tS73pfonCscsX4mKTWmNODu7bU+x/zWGHTn4pSN/9/IR5m4PLFKgv TU+wyJt9SH3VOebVLNhzHXLI+5KKgVRlS5YUiIMjOl+qWJgDpVKHduvtiDzXp7KtPcX7 gCV9RCTvUZ668y7mSrfEVWT65iVSeHSnPHwAPy0GWcknV1x7uUQGGrYvzPvDCAvpqs79 /oJEs+gZtllBXuAmAGdYfEEp/gq9aKJNWBzxB6LxYRl4aCiNLjI9L8NPnIrivvHXVqkQ nKCU8iByCpi3ToZCz3YiPvqA9+4NKNtZzGq3+YHDYDUNYrclWqd51HYJN8Z03DMiDoIZ 1RwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=G2UMs8P9dA6Upr72L0xeE/uCH2mdeHNiCiDn7eHqgjA=; b=tj96ZN91Epn2fUqwLYyXbdX2guT6K2KBHWFjDF7okMqlU1Q+vvBNzAoBlH4dr37G4n k4fI59JbMScnArX0nXVbbSn2xmYZh6hjOIz863y0QnfQ15SC7waXD5luDG3o4JCCqQ9y 4jRW3GVoGDbyh8gmLRcQ3QCYjwXrune2e9KCTY6IQRo4k04zw62yJkKy09mP9OXmGokh mj2YZqQjb4Xc1GU7GP4/FNtRHpnoJTaudydftw7fAoRqph+4V+dn79Zv7VRk3/+7Qwhl iZC6ytRZa3dz4DKYA3nHnDMXpSsJVlTIzrhkrQ6ylglApMCO2vTjBB5mSRIOYG89Ldda XAPg== X-Gm-Message-State: AElRT7EkW9Qo9v1hMC+ivKJYzz+/an7XyjAxF0ZohfOhizZvJlslo/i9 ZWtLlD+oC4M0kppllkipH2iWWLyBJNU= X-Google-Smtp-Source: AG47ELudcF10i1IHYxy18Xy91Jwx5esnTuS6j43N+ybfS75EV0+yFd1yFjEou2eEn0u5g1LHnNKLTg== X-Received: by 10.98.0.4 with SMTP id 4mr2556738pfa.160.1521229350743; Fri, 16 Mar 2018 12:42:30 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Fri, 16 Mar 2018 12:41:12 -0700 Message-Id: <1521229281-73637-16-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1521229281-73637-1-git-send-email-mjc@sifive.com> References: <1521229281-73637-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v3 15/24] RISC-V: Use memory_region_is_ram in pte update X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" After reading cpu_physical_memory_write and friends, it seems that memory_region_is_ram is a more appropriate interface, and matches the intent of the code that is calling it. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt --- target/riscv/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/helper.c b/target/riscv/helper.c index 523a275..c430e95 100644 --- a/target/riscv/helper.c +++ b/target/riscv/helper.c @@ -237,7 +237,7 @@ restart: rcu_read_lock(); mr =3D address_space_translate(cs->as, pte_addr, &addr1, &l, false); - if (memory_access_is_direct(mr, true)) { + if (memory_region_is_ram(mr)) { target_ulong *pte_pa =3D qemu_map_ram_ptr(mr->ram_block, addr1); #if TCG_OVERSIZED_GUEST --=20 2.7.0 From nobody Sat Oct 25 11:05:05 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521230484108942.2894816086932; Fri, 16 Mar 2018 13:01:24 -0700 (PDT) Received: from localhost ([::1]:59305 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvXR-0005ts-Rp for importer@patchew.org; Fri, 16 Mar 2018 16:01:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40377) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvFJ-0007Wp-SJ for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ewvFI-0003oB-SX for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:33 -0400 Received: from mail-pl0-x241.google.com ([2607:f8b0:400e:c01::241]:38496) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ewvFI-0003ns-MP for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:32 -0400 Received: by mail-pl0-x241.google.com with SMTP id m22-v6so6505552pls.5 for ; Fri, 16 Mar 2018 12:42:32 -0700 (PDT) Received: from monty.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id k24sm13780469pff.77.2018.03.16.12.42.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 16 Mar 2018 12:42:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JjGyplqqVlE4UQ9tNmqboa5lGCOAOgUeBOIRDmEp87s=; b=UdS1d2xLuB5HshQDBWd3C1uIoMGJdB+J1H/hHD8yCNF6LCHTnBx0SAvmMkrejPybvS vsnBALqI0rgYyfOexOZUltFUWrHG8n+8hIONmlnjPlMzUBLAI0JZFoiYf48Pz31vZI2t sObKHUE2mak5z5j2WjWtIiVBN5yt1RrMTJ2A6CJPs61SfAEp8PteCg+N25hgXANrpO3g +Gs6WsugQrcDBJZdFes/lTKYz9I5bQxlaUqtd7ZEFaJYnQilye3wuvO3C/Yetg8Do5Tt foRtYnl5Xy8qI47EZDMwOtIQmQSJtyEqPn2wE5sGVoP1db0yiCOFHfMJPM68Otp230Jr CVEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JjGyplqqVlE4UQ9tNmqboa5lGCOAOgUeBOIRDmEp87s=; b=cB4fLGIUEHhPEioWsVKGlUWL4srVNxxvyRQOiKVFkq+vIr7nY2xdGGujEuXzEJ7C/N URLQd5qBJUtlGFdIob0lK/3S/MV6avY2IsWx1O96BSGWKue5yo8bH1ZJ+R2FHGQqkHFZ rUkeyuMTl6yB+xZKg71auqxLLTgSRIBiXWa3JjG+MbZ/GJmqNwWbbNPvMZzIkkzUpr4h lPEkvwPg0eMm3mx0DlTDMMQ7jpiseQotBe2+ctpo2xdThM4wrWHhz2MnUoMU75oNeEtO cJyfpIHVjuZPtdZOlV8MFKQpsfkylrFth3WpdNmPxYdXddYO5NMgOHifIuaWUcLKDmxJ HlRw== X-Gm-Message-State: AElRT7HSWJwxYT++RSGfikoomHieW9w3ARqjlhJkdBln23N9F/D0MeVD VzLQeZX5EkpL4Xz7ZzW/19Ho99OohvQ= X-Google-Smtp-Source: AG47ELu9NQ1bdBvl86x1/54bHL/UCBNlnr6CAA+FC6Lp8lahQLAm1v4Aj7RjW3MohR8uzU1XcgzkiA== X-Received: by 2002:a17:902:8d87:: with SMTP id v7-v6mr3374123plo.146.1521229351680; Fri, 16 Mar 2018 12:42:31 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Fri, 16 Mar 2018 12:41:13 -0700 Message-Id: <1521229281-73637-17-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1521229281-73637-1-git-send-email-mjc@sifive.com> References: <1521229281-73637-1-git-send-email-mjc@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::241 Subject: [Qemu-devel] [PATCH v3 16/24] RISC-V: Remove EM_RISCV ELF_MACHINE indirection X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Pointless indirection. Other ports use EM_ constants directly. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/sifive_e.c | 2 +- hw/riscv/sifive_u.c | 2 +- hw/riscv/spike.c | 2 +- hw/riscv/virt.c | 2 +- target/riscv/cpu.h | 1 - 5 files changed, 4 insertions(+), 5 deletions(-) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 4872b68..39e4cb4 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -88,7 +88,7 @@ static uint64_t load_kernel(const char *kernel_filename) =20 if (load_elf(kernel_filename, NULL, NULL, &kernel_entry, NULL, &kernel_high, - 0, ELF_MACHINE, 1, 0) < 0) { + 0, EM_RISCV, 1, 0) < 0) { error_report("qemu: could not load kernel '%s'", kernel_filename); exit(1); } diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 57b4f4f..0e633a0 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -74,7 +74,7 @@ static uint64_t load_kernel(const char *kernel_filename) =20 if (load_elf(kernel_filename, NULL, NULL, &kernel_entry, NULL, &kernel_high, - 0, ELF_MACHINE, 1, 0) < 0) { + 0, EM_RISCV, 1, 0) < 0) { error_report("qemu: could not load kernel '%s'", kernel_filename); exit(1); } diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index c7d937b..70e697c 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -64,7 +64,7 @@ static uint64_t load_kernel(const char *kernel_filename) uint64_t kernel_entry, kernel_high; =20 if (load_elf_ram_sym(kernel_filename, NULL, NULL, - &kernel_entry, NULL, &kernel_high, 0, ELF_MACHINE, 1, 0, + &kernel_entry, NULL, &kernel_high, 0, EM_RISCV, 1, 0, NULL, true, htif_symbol_callback) < 0) { error_report("qemu: could not load kernel '%s'", kernel_filename); exit(1); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index d680cbd..e3f8bb7 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -68,7 +68,7 @@ static uint64_t load_kernel(const char *kernel_filename) =20 if (load_elf(kernel_filename, NULL, NULL, &kernel_entry, NULL, &kernel_high, - 0, ELF_MACHINE, 1, 0) < 0) { + 0, EM_RISCV, 1, 0) < 0) { error_report("qemu: could not load kernel '%s'", kernel_filename); exit(1); } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 3a0ca2f..7c4482b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -34,7 +34,6 @@ =20 #define TCG_GUEST_DEFAULT_MO 0 =20 -#define ELF_MACHINE EM_RISCV #define CPUArchState struct CPURISCVState =20 #include "qemu-common.h" --=20 2.7.0 From nobody Sat Oct 25 11:05:05 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521230065564479.2895996451159; Fri, 16 Mar 2018 12:54:25 -0700 (PDT) Received: from localhost ([::1]:59252 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvQm-0000Bt-AB for importer@patchew.org; Fri, 16 Mar 2018 15:54:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40395) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvFK-0007Xy-Sb for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ewvFJ-0003of-VP for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:34 -0400 Received: from mail-pl0-x242.google.com ([2607:f8b0:400e:c01::242]:44989) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ewvFJ-0003oO-Pt for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:33 -0400 Received: by mail-pl0-x242.google.com with SMTP id 9-v6so6503940ple.11 for ; Fri, 16 Mar 2018 12:42:33 -0700 (PDT) Received: from monty.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id k24sm13780469pff.77.2018.03.16.12.42.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 16 Mar 2018 12:42:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=skhNLehqLx7INkCfB7WkgTioVOYa2VI4KQLj/TiEtYM=; b=OX7z2qKu7yM8MHIBFprKTJVZv6HgM5QWReXZTY9oWEv3j8yBGajjUDne0T/lC1+Zcl jUPBMG6lqa2yWVHCva1tbj51+m9TwK/UgzUjUlUn+Ax0Dq/3A0bhFdmL2Va9X93DOLDZ LsPCW+Ic6wDsVI+24XEJFGmvWeQvZFd70ku0F39o6zhMZ0RPsHgW/jIsafDGEJm1x0Uf ZlOlTzPgXJJtcwmKe05jcSObpqAjvC7DrgGwQ+5oiRfsUBevMueuwOefyOTSStv3ZWrf oUAOTrzrcZCEnbxpNccQulApMj6awvLESVbz9SoX+Xki4FCs/jtV4XjfD9/PtF5vHE9N QxOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=skhNLehqLx7INkCfB7WkgTioVOYa2VI4KQLj/TiEtYM=; b=qKk0GRN015sbS38zOPy4PWm71xK3SYOZXJuFXnOE7DK/+S4BNPorRd+0EYJROSt8Cf X+SYQyC+m+0QrBDSkcdl3FM1aEI4e078dCbGj4vEXceg5W3BqwDD0b3qE2Nj3jpb2/kC H91oz3Saz0tj5S8hzQB+p7rmJ3VxaLUA1D+B6KLmdnUhDlytrBAaGMDuYSPVSpef5ZvG 6v5pHMZTFEnTgGhsWBjEPo5klFl1bcTwblrG5pSgQjeuxspmecCvD3O3Sgnf66VsIlea OEZY/nuVQvxoUmik0kQYfHie78kdNffATcfaZgLR0Zy6La1NdF1YMBQMbx3eTNzqyiFN vqlQ== X-Gm-Message-State: AElRT7GqnNza6cCr+BydbP06JoIJrgOBmjJWtFNeyxRArJPIzHc4fKv2 JrvlW6xCbedzjIHrUN7BnnkzTljZEFM= X-Google-Smtp-Source: AG47ELvGRr5MEflDIgvEpL9ywlvSmeAenlDn4rmnaAfxB4LN6kP5kzpEb8QoL4mNshypXg41NnjrRw== X-Received: by 2002:a17:902:b10c:: with SMTP id q12-v6mr3426918plr.197.1521229352553; Fri, 16 Mar 2018 12:42:32 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Fri, 16 Mar 2018 12:41:14 -0700 Message-Id: <1521229281-73637-18-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1521229281-73637-1-git-send-email-mjc@sifive.com> References: <1521229281-73637-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH v3 17/24] RISC-V: Hardwire satp to 0 for no-mmu case X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" satp is WARL so it should not trap on illegal writes, rather it can be hardwired to zero and silently ignore illegal writes. It seems the RISC-V WARL behaviour is preferred to having to trap overhead versus simply reading back the value and checking if the write took (saves hundreds of cycles and more complex trap handling code). Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt --- target/riscv/op_helper.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index e34715d..dd3e417 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -242,7 +242,7 @@ void csr_write_helper(CPURISCVState *env, target_ulong = val_to_write, } case CSR_SATP: /* CSR_SPTBR */ { if (!riscv_feature(env, RISCV_FEATURE_MMU)) { - goto do_illegal; + break; } if (env->priv_ver <=3D PRIV_VERSION_1_09_1 && (val_to_write ^ env-= >sptbr)) { @@ -452,7 +452,10 @@ target_ulong csr_read_helper(CPURISCVState *env, targe= t_ulong csrno) return env->scounteren; case CSR_SCAUSE: return env->scause; - case CSR_SPTBR: + case CSR_SATP: /* CSR_SPTBR */ + if (!riscv_feature(env, RISCV_FEATURE_MMU)) { + return 0; + } if (env->priv_ver >=3D PRIV_VERSION_1_10_0) { return env->satp; } else { --=20 2.7.0 From nobody Sat Oct 25 11:05:05 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521230005559650.5795827035486; Fri, 16 Mar 2018 12:53:25 -0700 (PDT) Received: from localhost ([::1]:59250 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvPm-0007ho-HN for importer@patchew.org; Fri, 16 Mar 2018 15:53:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40408) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvFL-0007Yc-EG for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ewvFK-0003pA-Ku for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:35 -0400 Received: from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:38197) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ewvFK-0003oo-FM for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:34 -0400 Received: by mail-pf0-x242.google.com with SMTP id d26so4547904pfn.5 for ; Fri, 16 Mar 2018 12:42:34 -0700 (PDT) Received: from monty.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id k24sm13780469pff.77.2018.03.16.12.42.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 16 Mar 2018 12:42:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UtDHM0IFsJP/nABkeJHaAyxMd9mnBAmwGcugxkD3tLA=; b=BDRc/ZIghAwgO5qMI1Bx0T3Tzy4rrQaIMW9kiayjfQxYFT/Z8xJ5zusUMJHB61jyJF S4VgtwmiFaEEmmIHPdH0Hphvt3q2fTLuqTHIRO1wI2M//VdL3LDN0DBd2gHZ9KbqVSal 14N9O95Re+asdUL89wtE3vGNkx5RhBKNmMFxxfHkAH7uDIwgG7c7WPHlkprAep+x0YTA dcfcTZJEu0cMGyw1YilXVlQPFDRLLc9O6mOnuaVQyHulcKw0xMf1D2YlG6/UZxEXsrwQ a+MfR5waFMtRqZh8u/XOfFDtpuhSDkJaaD5Vo7zmrzZOEWe2aZnXgWSxKK6E2SMWQ+ve dZwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UtDHM0IFsJP/nABkeJHaAyxMd9mnBAmwGcugxkD3tLA=; b=aoBK2k2HuuZNOSC/rOG7+xLu0/npC3dEUEbKOfSdxvqt2VjHj9hiuHLVyuAnAFsTW4 X6vZ2IhsvEiqn/2Mv0k/pgOPsKlV9wPqOt4fmww05eGJGAdD9r2bnzCYrEyL0DmVkt7o qLLTqVZXs4RGTrAjA6ffyR0F79sJFpMqflj1po+XwHklJXJ5l/9nf203yik+2K3sUgNR YqcAHslr4LUpTLrngqWQzfAbv9cCPqHf4yzuqzqOxIKmOe7M5CmTQmkZlEicXOLmtVDI 8sr/s81L9okw8YQ+cqxrjE0IOdKewSBt1r8x62wYZevl70f4rWlz1HnSpec5ppGCzqIN 1upA== X-Gm-Message-State: AElRT7GQe1vba28pgFS/utv8hEOv3pOo33bFER54YnP7PvrD7/8nbGSY /JLiabeJMFpKnrI/wcI81uO0Nd8uRzs= X-Google-Smtp-Source: AG47ELsJj1T3HOP2N9qYOqt8U0kukWTWxmNbEgA0+Ha2wKyj5YarPKXJjWjAOu3zCP7IuRWFmJihPw== X-Received: by 10.98.222.65 with SMTP id h62mr2607695pfg.134.1521229353509; Fri, 16 Mar 2018 12:42:33 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Fri, 16 Mar 2018 12:41:15 -0700 Message-Id: <1521229281-73637-19-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1521229281-73637-1-git-send-email-mjc@sifive.com> References: <1521229281-73637-1-git-send-email-mjc@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH v3 18/24] RISC-V: Remove braces from satp case statement X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/op_helper.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index dd3e417..f79716a 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -240,7 +240,7 @@ void csr_write_helper(CPURISCVState *env, target_ulong = val_to_write, csr_write_helper(env, next_mie, CSR_MIE); break; } - case CSR_SATP: /* CSR_SPTBR */ { + case CSR_SATP: /* CSR_SPTBR */ if (!riscv_feature(env, RISCV_FEATURE_MMU)) { break; } @@ -258,7 +258,6 @@ void csr_write_helper(CPURISCVState *env, target_ulong = val_to_write, env->satp =3D val_to_write; } break; - } case CSR_SEPC: env->sepc =3D val_to_write; break; --=20 2.7.0 From nobody Sat Oct 25 11:05:05 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521230554234503.8163987663323; Fri, 16 Mar 2018 13:02:34 -0700 (PDT) Received: from localhost ([::1]:59312 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvYb-0006i5-HD for importer@patchew.org; Fri, 16 Mar 2018 16:02:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40425) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvFM-0007a6-QN for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ewvFL-0003po-Kv for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:36 -0400 Received: from mail-pl0-x243.google.com ([2607:f8b0:400e:c01::243]:37635) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ewvFL-0003pU-EY for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:35 -0400 Received: by mail-pl0-x243.google.com with SMTP id w12-v6so6510973plp.4 for ; Fri, 16 Mar 2018 12:42:35 -0700 (PDT) Received: from monty.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id k24sm13780469pff.77.2018.03.16.12.42.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 16 Mar 2018 12:42:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5wkGofJ2JvTExfEREXPeUuFavSJnHyXXkYmuyPtGFLE=; b=T2+H1Kk6u8yBW5n1OXzoLoF+bAzcdIK3nlcOnWRm7ONMn1bznf0ktI3RUOW1+FuPtm qb7/QNxQMgBnwEKTAwjrb6gBnItnvuZM89jKfGQI2I3d3lwpTcLercK1CBzhIgl9xAbx zUDmZHbeouRaOT5amc0WoOLUtwx3CIULZbffOnhc5b0kMGMPw0sPcncesfSTwQQ5Xyy1 6jxxR9ez1cS6lqWysCaoEVJICpBFOcJU4VFFwk8c0eckZpRRq0kNiak3TomlWltm1UT8 i9qrfsMdXV0kHSLYHp2T2FfmwCPWujGuccccGlgzByreWNOkLJga/IFflGseP2jr6s+q DqHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5wkGofJ2JvTExfEREXPeUuFavSJnHyXXkYmuyPtGFLE=; b=q51Y38PXuGqylFpuTyolrrfwqSZqneRvw8KwFuZz0bAUPM+x8srrVuNhHB3g0pcVQ1 D3wl5zUtIruBwrxm8Li5WgMs0Xntgs1MJnu7MU1o6XnkKD0/1kIoKEGfm1i3llGpiXKh gB/47mo569zzN4Nu44lkK6n8jM6bc2H5HOWWJGl25tLTfDDil9D1Gwa9v39O7+ktmEww b5UThnS3DwhBm/CkMG2PIVAsNANJubZRInDVIrkcLr2XQUFMpmQUFDlyQZbUT3ObuBh+ iz98hL30PjwRaUESAXM5D9hTZl60ggvfYvR/JMBNNkVci6Kv5b4Tf52hFkAo1i6gkTpE f0YA== X-Gm-Message-State: AElRT7GLdguH3DyT8YRQxWlpz+gxKIy+ul/+U2burB32BIXdY1nizs/Z o1zwl+7WfbjXWhwXQhufciam2QpFxCA= X-Google-Smtp-Source: AG47ELuj2XWwPTJgaew9R4/kUYemKekGSprIB/BgkvNxDDpKxN9BGwmuas/3L90oI1h5bBnmC3QJFw== X-Received: by 2002:a17:902:8697:: with SMTP id g23-v6mr3419244plo.393.1521229354495; Fri, 16 Mar 2018 12:42:34 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Fri, 16 Mar 2018 12:41:16 -0700 Message-Id: <1521229281-73637-20-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1521229281-73637-1-git-send-email-mjc@sifive.com> References: <1521229281-73637-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PATCH v3 19/24] RISC-V: riscv-qemu port supports sv39 and sv48 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7c4482b..f47fc9c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -24,8 +24,8 @@ #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */ #if defined(TARGET_RISCV64) #define TARGET_LONG_BITS 64 -#define TARGET_PHYS_ADDR_SPACE_BITS 50 -#define TARGET_VIRT_ADDR_SPACE_BITS 39 +#define TARGET_PHYS_ADDR_SPACE_BITS 52 +#define TARGET_VIRT_ADDR_SPACE_BITS 48 #elif defined(TARGET_RISCV32) #define TARGET_LONG_BITS 32 #define TARGET_PHYS_ADDR_SPACE_BITS 34 --=20 2.7.0 From nobody Sat Oct 25 11:05:05 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521230164331969.1289932935981; Fri, 16 Mar 2018 12:56:04 -0700 (PDT) Received: from localhost ([::1]:59269 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvSI-0001i3-4k for importer@patchew.org; Fri, 16 Mar 2018 15:55:58 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40465) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvFR-0007ek-2b for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ewvFM-0003qL-VG for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:41 -0400 Received: from mail-pl0-x244.google.com ([2607:f8b0:400e:c01::244]:43231) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ewvFM-0003px-Ht for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:36 -0400 Received: by mail-pl0-x244.google.com with SMTP id f23-v6so6498942plr.10 for ; Fri, 16 Mar 2018 12:42:36 -0700 (PDT) Received: from monty.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id k24sm13780469pff.77.2018.03.16.12.42.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 16 Mar 2018 12:42:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bt2M/AHC9Y7szQPwhX3hgmhil+uRswKhQTDlPUwKQgg=; b=UVBIWTRJMg5/0kVkYdwwyLXgb5gX0RQIapfZXOvr+dW+SRUYCICW+9p7eXQE8FM+Au aYunBPiQ/WeHzzlHUvtsP+mgPzIpIOoNvO/FWHAp/m5gOOCJ2AyKZTB88QAqOxOKmVf5 KTafZT7kjcO1CNzcDXw1ATjDG+C46Oz75+oQtI3jMgd8jP3ze8fZkLLkF4ssQxtE/V5B Boh41FbISHMYQuU/g1K4pWR7aIqRA8fppSpvuYi8ddE/R0XEpRnFHaxcIPE0LRTyA5T3 SCU5/kB6LMubckR91lityx99Qq5r0nIlew3eYnPc2zJrFfDgC5E9wtcPeJOaRTMYCHie t7Cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bt2M/AHC9Y7szQPwhX3hgmhil+uRswKhQTDlPUwKQgg=; b=lbMrizMuFcdVikYRgMiUd+4NYktKpfozGEZIhDHWC7xIKHz6rWUacSB1tXFy7hvLg5 NVoF0qE6y50fT9/6pUmbORSij259hdljk1hscdkY8QJe5j8FRhz8iOOaalxQ5VRg8SO2 k8agynp2U/eIAsv5rogDNFHwkXX17q3JfKCWcVxCzdNdUl6/ewWdlSxDrmxa1VJTwE3S cLCInNGtRiPotuUqmvvj8nc9PNIalp+TAKSr1oXbCBB8ZJi6fqt1D6klyBG9Cvn1hQZL +za9ztLUaDeRG5mq63ZQuxj2ao18bx3FmoAC7fIoh+SyOWFpe1UXi9Z9ezlQPga9dI6+ u+eQ== X-Gm-Message-State: AElRT7H0jiA4iWVnAHbdHFylt1aWfQv+M1zauuHnxV/HZgpyKNf0R5S7 C3sLaSmRtw7oKQklpGJjUKAuDcLvTiM= X-Google-Smtp-Source: AG47ELsdLqmBv3K4EZn09u1cd23kYc9LS5GQwa7A0nxzdbcZDc30oS6ItcQOHTMLohFkkndfnqcBOw== X-Received: by 2002:a17:902:82c2:: with SMTP id u2-v6mr3252117plz.401.1521229355545; Fri, 16 Mar 2018 12:42:35 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Fri, 16 Mar 2018 12:41:17 -0700 Message-Id: <1521229281-73637-21-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1521229281-73637-1-git-send-email-mjc@sifive.com> References: <1521229281-73637-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PATCH v3 20/24] RISC-V: vectored traps are optional X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Vectored traps for asynchrounous interrupts are optional. The mtvec/stvec mode field is WARL and hence does not trap if an illegal value is written. Illegal values are ignored. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt --- target/riscv/op_helper.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index f79716a..aa101cc 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -262,11 +262,10 @@ void csr_write_helper(CPURISCVState *env, target_ulon= g val_to_write, env->sepc =3D val_to_write; break; case CSR_STVEC: - if (val_to_write & 1) { - qemu_log_mask(LOG_UNIMP, "CSR_STVEC: vectored traps not suppor= ted"); - goto do_illegal; + /* we do not support vectored traps for asynchrounous interrupts *= /=20 + if ((val_to_write & 3) =3D=3D 0) { + env->stvec =3D val_to_write >> 2 << 2; } - env->stvec =3D val_to_write >> 2 << 2; break; case CSR_SCOUNTEREN: env->scounteren =3D val_to_write; @@ -284,11 +283,10 @@ void csr_write_helper(CPURISCVState *env, target_ulon= g val_to_write, env->mepc =3D val_to_write; break; case CSR_MTVEC: - if (val_to_write & 1) { - qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: vectored traps not suppor= ted"); - goto do_illegal; + /* we do not support vectored traps for asynchrounous interrupts *= /=20 + if ((val_to_write & 3) =3D=3D 0) { + env->mtvec =3D val_to_write >> 2 << 2; } - env->mtvec =3D val_to_write >> 2 << 2; break; case CSR_MCOUNTEREN: env->mcounteren =3D val_to_write; --=20 2.7.0 From nobody Sat Oct 25 11:05:05 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521230374418165.14076064045935; Fri, 16 Mar 2018 12:59:34 -0700 (PDT) Received: from localhost ([::1]:59288 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvVf-0004TT-Vl for importer@patchew.org; Fri, 16 Mar 2018 15:59:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40467) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvFR-0007en-3C for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ewvFN-0003qe-MD for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:41 -0400 Received: from mail-pl0-x242.google.com ([2607:f8b0:400e:c01::242]:33536) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ewvFN-0003qP-Fh for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:37 -0400 Received: by mail-pl0-x242.google.com with SMTP id c11-v6so6503753plo.0 for ; Fri, 16 Mar 2018 12:42:37 -0700 (PDT) Received: from monty.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id k24sm13780469pff.77.2018.03.16.12.42.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 16 Mar 2018 12:42:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=elXEjrujeHBejLZefg5SAzL2dxTnnLrXWqzO68PGJuU=; b=e4wIcFgNiOLilC80AR3vgrg+tpSs56OxbCPxVR0homSm/0yxSKNChvRKMHxgIoiSKU wOOGtxNOy7bzPk8KgqRR0aC1j8EBFAMyYAHUp7OZDkO86T6EG7NN2eNt6LWLIuanD14w y5Ms9tuldqKr0m4jN20zAa57ik2EHpmrGbiaPKqMdFtZPEp3vBvq1YjT+pmlzN7BaCjU p232indweK4dwO3FZz0USFHJ7L3jdOWyxtimEDQX16GpL9JLkxRhdsp6OQvLs2KBR4lN EiZC9hw+6IAVbjs0qbbDfXuYKL1yI5tZhU7pnZfX8mm0jr1VN8gkiCxJZoRbwh+5Xk1q rzrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=elXEjrujeHBejLZefg5SAzL2dxTnnLrXWqzO68PGJuU=; b=nV7EaPIsQXIK80F0P5fyF+j+OQBG8fBIIeOtAE4RcPwM/lugLqXsDojgKV5gm35gfQ Q9lZFrJV133DbnoZ1t6pFwebVZTQTt4nAJ+zu9feEZXE1uXlnCG3KnvmrfrSxGzDjNWg VzcwYE3Upit+wMQnh1YrNDOpAjHyjSbRvDEA4LKhHTU7uUSXddwiZF6SezWs9jaGnouM SR5FGSMHfXuuivqJbzO5ALBZcQ5UPQxSO2awO0L86CB7bmlDDriusUMStU3x58fMXxkR tpowB0OT97mEhcAih64dvCJfUaFCaKjMEsdkKw0rhv99sHQ59YKbNDyb86yv+1IYUwD+ uszQ== X-Gm-Message-State: AElRT7Hl8g/uuPWXaF6j5BPnSmbVUItERDqBSmW3Fm4wV0E08GUoZlVV Mt/rgemvBm4iBTgjGz7AZPffo7wffuo= X-Google-Smtp-Source: AG47ELu7DuGrdKAor8d521RbFZ8zFSTJ0shCC1zODIVIKaV05hJfwIADvi9KfgdQ5n90CDdCk12giw== X-Received: by 2002:a17:902:167:: with SMTP id 94-v6mr3390292plb.294.1521229356484; Fri, 16 Mar 2018 12:42:36 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Fri, 16 Mar 2018 12:41:18 -0700 Message-Id: <1521229281-73637-22-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1521229281-73637-1-git-send-email-mjc@sifive.com> References: <1521229281-73637-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH v3 21/24] RISC-V: No traps on writes to misa, minstret, mcycle X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" These fields are marked WARL in the specification so illegal writes are silently dropped. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt --- target/riscv/op_helper.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index aa101cc..f8595a6 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -200,17 +200,19 @@ void csr_write_helper(CPURISCVState *env, target_ulon= g val_to_write, break; } case CSR_MINSTRET: - qemu_log_mask(LOG_UNIMP, "CSR_MINSTRET: write not implemented"); - goto do_illegal; + /* minstret is WARL so unsupported writes are ignored */ + break; case CSR_MCYCLE: - qemu_log_mask(LOG_UNIMP, "CSR_MCYCLE: write not implemented"); - goto do_illegal; + /* mcycle is WARL so unsupported writes are ignored */ + break; +#if defined(TARGET_RISCV32) case CSR_MINSTRETH: - qemu_log_mask(LOG_UNIMP, "CSR_MINSTRETH: write not implemented"); - goto do_illegal; + /* minstreth is WARL so unsupported writes are ignored */ + break; case CSR_MCYCLEH: - qemu_log_mask(LOG_UNIMP, "CSR_MCYCLEH: write not implemented"); - goto do_illegal; + /* mcycleh is WARL so unsupported writes are ignored */ + break; +#endif case CSR_MUCOUNTEREN: env->mucounteren =3D val_to_write; break; @@ -300,10 +302,9 @@ void csr_write_helper(CPURISCVState *env, target_ulong= val_to_write, case CSR_MBADADDR: env->mbadaddr =3D val_to_write; break; - case CSR_MISA: { - qemu_log_mask(LOG_UNIMP, "CSR_MISA: misa writes not supported"); - goto do_illegal; - } + case CSR_MISA: + /* misa is WARL so unsupported writes are ignored */ + break; case CSR_PMPCFG0: case CSR_PMPCFG1: case CSR_PMPCFG2: @@ -328,7 +329,6 @@ void csr_write_helper(CPURISCVState *env, target_ulong = val_to_write, case CSR_PMPADDR15: pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val_to_write); break; - do_illegal: #endif default: do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); --=20 2.7.0 From nobody Sat Oct 25 11:05:05 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521230266981941.2121741320668; Fri, 16 Mar 2018 12:57:46 -0700 (PDT) Received: from localhost ([::1]:59280 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvU1-00038R-SI for importer@patchew.org; Fri, 16 Mar 2018 15:57:45 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40469) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvFR-0007eo-35 for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ewvFO-0003qz-Ky for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:41 -0400 Received: from mail-pl0-x244.google.com ([2607:f8b0:400e:c01::244]:41623) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ewvFO-0003qm-Ed for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:38 -0400 Received: by mail-pl0-x244.google.com with SMTP id b7-v6so2425732plr.8 for ; Fri, 16 Mar 2018 12:42:38 -0700 (PDT) Received: from monty.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id k24sm13780469pff.77.2018.03.16.12.42.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 16 Mar 2018 12:42:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VoByu3qAZNTRbnvBtyhKGH0UNxevYf7YuBxpaK2evpQ=; b=ALvzgax68rO1ULS+LqRiXpCcnU3GbYQ6qAA9t6VVbv8BJT96oSxgOzN41uSooOc/jT s91d2CpCcCCoUvFjEpgTLyzckiB3N5KsglbZlm9Pvm5jIjWzWRL3JtHRmXe/VXjUxzfK 3HPl0aZZ9yVUOJB7fpqmtkfC0rvJlN3ssz070a4gVJGCjlzASTbalrIx6myqJT1wcIa8 pDgycLK6cTYrWosOvMoVF9Hfwd751GnOp1E+itQhq2N4KTup+362CeKqjAT46LPWO+yA 55QbtjaSmZfROTtiZDMNtadzd+/QkWwrQmNEd5Gx4o2qa00lgPRYtoSkqTU0q+764Mtx nrCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VoByu3qAZNTRbnvBtyhKGH0UNxevYf7YuBxpaK2evpQ=; b=rkeEp0DHes6AbUcpIS4z7DjIgRQmfu0vx+CE/zxRrYGyUTOVq3tLw8l91GV47tFb+K UXFvepZSS7rFiNE5AGGiJCKO0fcHZZ3htV13JAakt1nvelI8IMwcYPwUwqVSitk2gN6d GvedUVy8Jb9AJQ9Z/giOIspcobbvsQbmRJmy4S1IOTyvvUETDDdRfjDFKx3mIrtCgQbg f53ZcPXbPqtimwcIwI5g3OGMn1Xg/zkNMN95VoCYpDa27DG2trE3tLaG12AL8+MGbK8v eRjWgUSb9xhWrmJwcp3zRArhp6b3Vfc0TOqCxIrv8gAz566+s8iWnZ4dtrcpc4XuysTz i8Jg== X-Gm-Message-State: AElRT7GWjeHvJIK0o/0uz/8ZDpn5erjGh4Oz5QOUjILc70sAflhZNfLH PaFRjeLLvVCBsyrwq37bgyPRbxGVrRM= X-Google-Smtp-Source: AG47ELv4WnGTln5rnptogk9H72OCIlt2DGbcVfX0of+OU/aB48THA4xGVkCBF6qLYyDsVeKwoWTptw== X-Received: by 2002:a17:902:5957:: with SMTP id e23-v6mr3265879plj.323.1521229357477; Fri, 16 Mar 2018 12:42:37 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Fri, 16 Mar 2018 12:41:19 -0700 Message-Id: <1521229281-73637-23-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1521229281-73637-1-git-send-email-mjc@sifive.com> References: <1521229281-73637-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PATCH v3 22/24] RISC-V: Remove support for adhoc X_COP interrupt X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is essentially dead-code elimination. Support for more local interrupts will be added in a future revision, as they will be defined in a future version of the Privileged ISA specification. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt --- target/riscv/cpu_bits.h | 1 - target/riscv/op_helper.c | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 12b4757..133e070 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -346,7 +346,6 @@ #define IRQ_S_EXT 9 #define IRQ_H_EXT 10 /* until: priv-1.9.1 */ #define IRQ_M_EXT 11 /* until: priv-1.9.1 */ -#define IRQ_X_COP 12 /* non-standard */ =20 /* Default addresses */ #define DEFAULT_RSTVEC 0x00001000 diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index f8595a6..f543e61 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -90,7 +90,7 @@ void csr_write_helper(CPURISCVState *env, target_ulong va= l_to_write, target_ulong csrno) { #ifndef CONFIG_USER_ONLY - uint64_t delegable_ints =3D MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ= _X_COP); + uint64_t delegable_ints =3D MIP_SSIP | MIP_STIP | MIP_SEIP; uint64_t all_ints =3D delegable_ints | MIP_MSIP | MIP_MTIP; #endif =20 --=20 2.7.0 From nobody Sat Oct 25 11:05:05 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521230622022393.75559702444446; Fri, 16 Mar 2018 13:03:42 -0700 (PDT) Received: from localhost ([::1]:59315 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvZl-0007O1-25 for importer@patchew.org; Fri, 16 Mar 2018 16:03:41 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40466) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvFR-0007em-2r for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ewvFP-0003rO-M4 for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:41 -0400 Received: from mail-pl0-x244.google.com ([2607:f8b0:400e:c01::244]:39514) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ewvFP-0003rB-DC for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:39 -0400 Received: by mail-pl0-x244.google.com with SMTP id k22-v6so5671709pls.6 for ; Fri, 16 Mar 2018 12:42:39 -0700 (PDT) Received: from monty.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id k24sm13780469pff.77.2018.03.16.12.42.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 16 Mar 2018 12:42:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9TrMd4TF0lU50Lp53KGXfUEURaP7R+dxEXI3heuCE4U=; b=HZMI/zJNSw3YQ4Ar2NicNeq06h23E8JxB6YQcfQ0qMOoFsoSL2ub5ZjevIXXYRQYuv 9Y9xYeldWeLj0PNQ7dfQz790txgtXYjtTtljMPYtw7xVe7GIci4jvbMrbONGGk5Xt/Wc WbDqx3aYvP9pZ+E9lobCUNM47N4P0f7Uq5wJdxi8+gTUta7/EOnZ2omA4voWkVdfbXCq YUi+7Afu31p5XQvNLb3cNXms1acDSCP0MyugNurm195IhJL7AqXJj+L2wmcjsn/i4bpY PtpYXVkhU6+sCnk5thiVju2b681f0OIzXaGVw0H5kwZPMzUwmLAO1VmecbZM22eF/Tkb gfUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9TrMd4TF0lU50Lp53KGXfUEURaP7R+dxEXI3heuCE4U=; b=DAud/hKidJWkxd7SJisAo6KqLYuvDeceHjH7o0wBgfpWUsYcxY0wEQfEX65IXfQSJB pqPrc7ZxnATSygpheWbDf5vUuY88CvfxsaxDsM5QgJQaQKmTKxMc37olrYtrsRpJ46vn MvRcBRzCzHim/TRsD0Tsht4bNYOUcoYrl2iNz457jfOat8ANESOm+5zsp5YQ59LabQGB k2e06jIqvt/7vWUlpsYnfIeX69mENSlSYhGNXJkZ2OPT/CqLtYsrzr9w3fSIZkLdtZS7 a8w+kPVRdUYunmz8lMafueGZlwxALAL+Y9IzMdbL8mV4X6NlexevLmz+F75/v1OnVzqS A8Tg== X-Gm-Message-State: AElRT7GvKhq15QhXiqvJ54RpxjON6xASzDVVliSX0lQlej0ADyBNtWn7 Psx/72gkmJo8dFaClCMPuhvcg0W4SB4= X-Google-Smtp-Source: AG47ELt0kt5nThHr2rF/JobFtID7oJTVd+nubpV9drvF7Up9Iu+oHUurPOZFytOUqaJzgje/skNVBA== X-Received: by 2002:a17:902:864b:: with SMTP id y11-v6mr3297778plt.380.1521229358418; Fri, 16 Mar 2018 12:42:38 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Fri, 16 Mar 2018 12:41:20 -0700 Message-Id: <1521229281-73637-24-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1521229281-73637-1-git-send-email-mjc@sifive.com> References: <1521229281-73637-1-git-send-email-mjc@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PATCH v3 23/24] RISC-V: Convert cpu definition towards future model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , Michael Clark , Igor Mammedov , patches@groups.riscv.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 - Model borrowed from target/sh4/cpu.c - Rewrote riscv_cpu_list to use object_class_get_list - Dropped 'struct RISCVCPUInfo' and used TypeInfo array - Replaced riscv_cpu_register_types with DEFINE_TYPES - Marked base class as abstract Cc: Igor Mammedov Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Palmer Dabbelt Signed-off-by: Michael Clark Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Igor Mammedov --- target/riscv/cpu.c | 123 ++++++++++++++++++++++++++++++-------------------= ---- 1 file changed, 69 insertions(+), 54 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d2ae56a..1f25968 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -115,6 +115,8 @@ static void riscv_any_cpu_init(Object *obj) set_resetvec(env, DEFAULT_RSTVEC); } =20 +#if defined(TARGET_RISCV32) + static void rv32gcsu_priv1_09_1_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; @@ -141,6 +143,8 @@ static void rv32imacu_nommu_cpu_init(Object *obj) set_resetvec(env, DEFAULT_RSTVEC); } =20 +#elif defined(TARGET_RISCV64) + static void rv64gcsu_priv1_09_1_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; @@ -167,20 +171,7 @@ static void rv64imacu_nommu_cpu_init(Object *obj) set_resetvec(env, DEFAULT_RSTVEC); } =20 -static const RISCVCPUInfo riscv_cpus[] =3D { - { 96, TYPE_RISCV_CPU_ANY, riscv_any_cpu_init }, - { 32, TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init }, - { 32, TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init }, - { 32, TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init }, - { 32, TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init }, - { 32, TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init }, - { 64, TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init }, - { 64, TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init }, - { 64, TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init }, - { 64, TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init }, - { 64, TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init }, - { 0, NULL, NULL } -}; +#endif =20 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) { @@ -366,28 +357,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void = *data) cc->vmsd =3D &vmstate_riscv_cpu; } =20 -static void cpu_register(const RISCVCPUInfo *info) -{ - TypeInfo type_info =3D { - .name =3D info->name, - .parent =3D TYPE_RISCV_CPU, - .instance_size =3D sizeof(RISCVCPU), - .instance_init =3D info->initfn, - }; - - type_register(&type_info); -} - -static const TypeInfo riscv_cpu_type_info =3D { - .name =3D TYPE_RISCV_CPU, - .parent =3D TYPE_CPU, - .instance_size =3D sizeof(RISCVCPU), - .instance_init =3D riscv_cpu_init, - .abstract =3D false, - .class_size =3D sizeof(RISCVCPUClass), - .class_init =3D riscv_cpu_class_init, -}; - char *riscv_isa_string(RISCVCPU *cpu) { int i; @@ -403,30 +372,76 @@ char *riscv_isa_string(RISCVCPU *cpu) return isa_string; } =20 -void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf) +typedef struct RISCVCPUListState { + fprintf_function cpu_fprintf; + FILE *file; +} RISCVCPUListState; + +static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) { - const RISCVCPUInfo *info =3D riscv_cpus; + ObjectClass *class_a =3D (ObjectClass *)a; + ObjectClass *class_b =3D (ObjectClass *)b; + const char *name_a, *name_b; =20 - while (info->name) { - if (info->bit_widths & TARGET_LONG_BITS) { - (*cpu_fprintf)(f, "%s\n", info->name); - } - info++; - } + name_a =3D object_class_get_name(class_a); + name_b =3D object_class_get_name(class_b); + return strcmp(name_a, name_b); } =20 -static void riscv_cpu_register_types(void) +static void riscv_cpu_list_entry(gpointer data, gpointer user_data) { - const RISCVCPUInfo *info =3D riscv_cpus; + RISCVCPUListState *s =3D user_data; + const char *typename =3D object_class_get_name(OBJECT_CLASS(data)); + int len =3D strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); =20 - type_register_static(&riscv_cpu_type_info); + (*s->cpu_fprintf)(s->file, "%.*s\n", len, typename); +} =20 - while (info->name) { - if (info->bit_widths & TARGET_LONG_BITS) { - cpu_register(info); - } - info++; - } +void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf) +{ + RISCVCPUListState s =3D { + .cpu_fprintf =3D cpu_fprintf, + .file =3D f, + }; + GSList *list; + + list =3D object_class_get_list(TYPE_RISCV_CPU, false); + list =3D g_slist_sort(list, riscv_cpu_list_compare); + g_slist_foreach(list, riscv_cpu_list_entry, &s); + g_slist_free(list); } =20 -type_init(riscv_cpu_register_types) +#define DEFINE_CPU(type_name, initfn) \ + { \ + .name =3D type_name, \ + .parent =3D TYPE_RISCV_CPU, \ + .instance_init =3D initfn \ + } + +static const TypeInfo riscv_cpu_type_infos[] =3D { + { + .name =3D TYPE_RISCV_CPU, + .parent =3D TYPE_CPU, + .instance_size =3D sizeof(RISCVCPU), + .instance_init =3D riscv_cpu_init, + .abstract =3D true, + .class_size =3D sizeof(RISCVCPUClass), + .class_init =3D riscv_cpu_class_init, + }, + DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), +#if defined(TARGET_RISCV32) + DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_in= it), + DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_in= it), + DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_in= it) +#elif defined(TARGET_RISCV64) + DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_in= it), + DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_in= it), + DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_in= it) +#endif +}; + +DEFINE_TYPES(riscv_cpu_type_infos) --=20 2.7.0 From nobody Sat Oct 25 11:05:05 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 152123000706881.78435062036897; Fri, 16 Mar 2018 12:53:27 -0700 (PDT) Received: from localhost ([::1]:59251 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvPm-0007ju-Sp for importer@patchew.org; Fri, 16 Mar 2018 15:53:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40475) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewvFR-0007fN-Ep for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ewvFQ-0003rf-IK for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:41 -0400 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:43944) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ewvFQ-0003rS-Bk for qemu-devel@nongnu.org; Fri, 16 Mar 2018 15:42:40 -0400 Received: by mail-pg0-x242.google.com with SMTP id e9so4459854pgs.10 for ; Fri, 16 Mar 2018 12:42:40 -0700 (PDT) Received: from monty.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id k24sm13780469pff.77.2018.03.16.12.42.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 16 Mar 2018 12:42:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=WP6AI2JAVU1W0wqCtqRCrL41KNwJLMUqnA6N+vWisv0=; b=mE46S3/wkMmEFFAp1Jd3UBTuXCvnD88MTZhOeYh4nH0mCHTF0t8B5EfYxOD+3g6ZyA GjtpRoLg07BjnR/TEcZDg1yqm/R7i1Q7olxrbMhrtpp2jk1BRtpz3QjjyWQqYCwwx6S1 Q3Siv48qSj/zsG4ra1LkQVwLFyHNwjAk1T7ksxsbVB0vuHt9JEv7fIWoIw5s2/Rn7RfM JCpsHZRD/1euml5/7QNCErUjruNlUq0u5IFNH3pjzaDdPdfCPuoP4t8h4Tly3zqI84EM 8Nwa4eUj5AGVsBiqgaUC2s284z0oqghAkiL3a04rsEkbO/Hg6Kj59Anh4TqYiUGNv4sd gu4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=WP6AI2JAVU1W0wqCtqRCrL41KNwJLMUqnA6N+vWisv0=; b=QBrAx1m1N74D7SmEW8uMB89zyDclZBaB67mjp+MzFV6UHGhWVi7xRLQMpwY9d171xX PzmA4056SFCTGIqq8OUnO9AEvCwLuCMewaHBEAECVKj4g4O1RJfU7/ayvMrKSYh+WiJn wtMdRjNZ/zu6y20QsqlrsQ2CAMxESV30pRHHc17MOUU3Q4bDkmQJm82+BzitAN0zhTaT kBEo4cWPfDtW11lqq0PKcVpbo01ZMeMEiT6zTZl3Eanb1tHGmWFf/NrC9R/3LFgSkuqu qz927qL79xXmmfy+cHJTZJMSKX5iHmjsH70zPkAKez3IziqV5eWI3l7QLmtx12RY6HMe PG1A== X-Gm-Message-State: AElRT7HFv1DFqHv+YkwvVCrRvsjEoQhx4rXO4sihv1caZm8KRtMArAci fnwUp56vdGEif/XhBv1pNzh2DmgzDLU= X-Google-Smtp-Source: AG47ELuT7b/d+1Yj45Vp0tARlANgmUFQNTYghARLJd2sFbah/O5JGK+dxCpughyR7IOuruFfxXZElw== X-Received: by 10.99.124.1 with SMTP id x1mr2363626pgc.318.1521229359374; Fri, 16 Mar 2018 12:42:39 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Fri, 16 Mar 2018 12:41:21 -0700 Message-Id: <1521229281-73637-25-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1521229281-73637-1-git-send-email-mjc@sifive.com> References: <1521229281-73637-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v3 24/24] RISC-V: Clear mtval/stval on exceptions without info X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" mtval/stval must be set on all exceptions but zero is a legal value if there is no exception specific info. Placing the instruction bytes for illegal instruction exceptions in mtval/stval is an optional feature and is currently not supported by QEMU RISC-V. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Palmer Dabbelt Signed-off-by: Michael Clark --- target/riscv/helper.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/riscv/helper.c b/target/riscv/helper.c index c430e95..54d4ff7 100644 --- a/target/riscv/helper.c +++ b/target/riscv/helper.c @@ -499,6 +499,10 @@ void riscv_cpu_do_interrupt(CPUState *cs) ": badaddr 0x" TARGET_FMT_lx, env->mhartid, env->badad= dr); } env->sbadaddr =3D env->badaddr; + } else { + /* otherwise we must clear sbadaddr/stval + * todo: support populating stval on illegal instructions */ + env->sbadaddr =3D 0; } =20 target_ulong s =3D env->mstatus; @@ -520,6 +524,10 @@ void riscv_cpu_do_interrupt(CPUState *cs) ": badaddr 0x" TARGET_FMT_lx, env->mhartid, env->badad= dr); } env->mbadaddr =3D env->badaddr; + } else { + /* otherwise we must clear mbadaddr/mtval + * todo: support populating mtval on illegal instructions */ + env->mbadaddr =3D 0; } =20 target_ulong s =3D env->mstatus; --=20 2.7.0