From nobody Sat Oct 25 13:20:08 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521034365823430.8858734475142; Wed, 14 Mar 2018 06:32:45 -0700 (PDT) Received: from localhost ([::1]:46353 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ew6WK-0005e8-P6 for importer@patchew.org; Wed, 14 Mar 2018 09:32:44 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35122) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ew6UE-0004QT-0p for qemu-devel@nongnu.org; Wed, 14 Mar 2018 09:30:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ew6U8-0001wB-77 for qemu-devel@nongnu.org; Wed, 14 Mar 2018 09:30:34 -0400 Received: from smtp1.lauterbach.com ([62.154.241.196]:55868) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ew6U7-0001ll-L3 for qemu-devel@nongnu.org; Wed, 14 Mar 2018 09:30:27 -0400 Received: (qmail 29361 invoked by uid 484); 14 Mar 2018 13:30:10 -0000 Received: from unknown (HELO localhost.localdomain) (Authenticated_SSL:abouassida@[41.224.44.126]) (envelope-sender ) by smtp1.lauterbach.com (qmail-ldap-1.03) with ECDHE-RSA-AES256-SHA encrypted SMTP for ; 14 Mar 2018 13:30:10 -0000 X-Qmail-Scanner-Diagnostics: from 41.224.44.126 by smtp1.lauterbach.com (envelope-from , uid 484) with qmail-scanner-2.11 (mhr: 1.0. clamdscan: 0.99/21437. spamassassin: 3.4.0. Clear:RC:1(41.224.44.126):. Processed in 0.051562 secs); 14 Mar 2018 13:30:10 -0000 From: Abdallah Bouassida To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Wed, 14 Mar 2018 14:28:02 +0100 Message-Id: <1521034084-17344-2-git-send-email-abdallah.bouassida@lauterbach.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1521034084-17344-1-git-send-email-abdallah.bouassida@lauterbach.com> References: <1521034084-17344-1-git-send-email-abdallah.bouassida@lauterbach.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 62.154.241.196 Subject: [Qemu-devel] [PATCH v5 1/3] target/arm: Add "ARM_CP_NO_GDB" as a new bit field for ARMCPRegInfo type X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: khaled.jmal@lauterbach.com, qemu-arm@nongnu.org, Abdallah Bouassida Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is a preparation for the coming feature of creating dynamically an XML description for the ARM sysregs. A register has ARM_CP_NO_GDB enabled will not be shown in the dynamic XML. This bit is enabled automatically when creating CP_ANY wildcard aliases. This bit could be enabled manually for any register we want to remove from = the dynamic XML description. Signed-off-by: Abdallah Bouassida Reviewed-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 3 ++- target/arm/helper.c | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1e7e1f8..5a6ea24 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1815,10 +1815,11 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpr= egid) #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA #define ARM_CP_FPU 0x1000 #define ARM_CP_SVE 0x2000 +#define ARM_CP_NO_GDB 0x4000 /* Used only as a terminator for ARMCPRegInfo lists */ #define ARM_CP_SENTINEL 0xffff /* Mask of only the flag bits in a type field */ -#define ARM_CP_FLAG_MASK 0x30ff +#define ARM_CP_FLAG_MASK 0x70ff =20 /* Valid values for ARMCPRegInfo state field, indicating which of * the AArch32 and AArch64 execution states this register is visible in. diff --git a/target/arm/helper.c b/target/arm/helper.c index 09893e3..db8c925 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5664,7 +5664,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, if (((r->crm =3D=3D CP_ANY) && crm !=3D 0) || ((r->opc1 =3D=3D CP_ANY) && opc1 !=3D 0) || ((r->opc2 =3D=3D CP_ANY) && opc2 !=3D 0)) { - r2->type |=3D ARM_CP_ALIAS; + r2->type |=3D ARM_CP_ALIAS | ARM_CP_NO_GDB; } =20 /* Check that raw accesses are either forbidden or handled. Note that --=20 2.7.4