From nobody Sat Oct 25 08:57:38 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1520850863373331.817390954846; Mon, 12 Mar 2018 03:34:23 -0700 (PDT) Received: from localhost ([::1]:57600 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1evKmT-0005gz-8U for importer@patchew.org; Mon, 12 Mar 2018 06:34:13 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38972) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1evKkI-0004Mj-9c for qemu-devel@nongnu.org; Mon, 12 Mar 2018 06:31:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1evKkF-0003aa-CI for qemu-devel@nongnu.org; Mon, 12 Mar 2018 06:31:58 -0400 Received: from smtp1.lauterbach.com ([62.154.241.196]:38619) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1evKkF-00034V-2j for qemu-devel@nongnu.org; Mon, 12 Mar 2018 06:31:55 -0400 Received: (qmail 13374 invoked by uid 484); 12 Mar 2018 10:31:37 -0000 Received: from unknown (HELO localhost.localdomain) (Authenticated_SSL:abouassida@[41.224.44.126]) (envelope-sender ) by smtp1.lauterbach.com (qmail-ldap-1.03) with ECDHE-RSA-AES256-SHA encrypted SMTP for ; 12 Mar 2018 10:31:37 -0000 X-Qmail-Scanner-Diagnostics: from 41.224.44.126 by smtp1.lauterbach.com (envelope-from , uid 484) with qmail-scanner-2.11 (mhr: 1.0. clamdscan: 0.99/21437. spamassassin: 3.4.0. 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Processed in 0.051559 secs); 12 Mar 2018 10:31:37 -0000 From: Abdallah Bouassida To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Mon, 12 Mar 2018 11:31:27 +0100 Message-Id: <1520850690-23245-2-git-send-email-abdallah.bouassida@lauterbach.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1520850690-23245-1-git-send-email-abdallah.bouassida@lauterbach.com> References: <1520850690-23245-1-git-send-email-abdallah.bouassida@lauterbach.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 62.154.241.196 Subject: [Qemu-devel] [PATCH v4 1/4] target/arm: Add "ARM_CP_NO_GDB" as a new bit field for ARMCPRegInfo type X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: khaled.jmal@lauterbach.com, qemu-arm@nongnu.org, Abdallah Bouassida Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is a preparation for the coming feature of creating dynamically an XML description for the ARM sysregs. A register has ARM_CP_NO_GDB enabled will not be shown in the dynamic XML. This bit is enabled automatically when creating CP_ANY wildcard aliases. This bit could be enabled manually for any register we want to remove from = the dynamic XML description. Signed-off-by: Abdallah Bouassida Reviewed-by: Peter Maydell --- target/arm/cpu.h | 3 ++- target/arm/helper.c | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 2b97408..818a98a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1796,10 +1796,11 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpr= egid) #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA #define ARM_CP_FPU 0x1000 #define ARM_CP_SVE 0x2000 +#define ARM_CP_NO_GDB 0x4000 /* Used only as a terminator for ARMCPRegInfo lists */ #define ARM_CP_SENTINEL 0xffff /* Mask of only the flag bits in a type field */ -#define ARM_CP_FLAG_MASK 0x30ff +#define ARM_CP_FLAG_MASK 0x70ff =20 /* Valid values for ARMCPRegInfo state field, indicating which of * the AArch32 and AArch64 execution states this register is visible in. diff --git a/target/arm/helper.c b/target/arm/helper.c index c82f63d..c5d62c8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5663,7 +5663,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, if (((r->crm =3D=3D CP_ANY) && crm !=3D 0) || ((r->opc1 =3D=3D CP_ANY) && opc1 !=3D 0) || ((r->opc2 =3D=3D CP_ANY) && opc2 !=3D 0)) { - r2->type |=3D ARM_CP_ALIAS; + r2->type |=3D ARM_CP_ALIAS | ARM_CP_NO_GDB; } =20 /* Check that raw accesses are either forbidden or handled. Note that --=20 2.7.4 From nobody Sat Oct 25 08:57:38 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1520851013038851.1948704830879; Mon, 12 Mar 2018 03:36:53 -0700 (PDT) Received: from localhost ([::1]:57619 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1evKoz-000826-P9 for importer@patchew.org; Mon, 12 Mar 2018 06:36:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38989) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1evKkI-0004Mm-Ok for qemu-devel@nongnu.org; Mon, 12 Mar 2018 06:32:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1evKkG-0003bu-A7 for qemu-devel@nongnu.org; Mon, 12 Mar 2018 06:31:58 -0400 Received: from smtp1.lauterbach.com ([62.154.241.196]:37163) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1evKkF-00036p-TA for qemu-devel@nongnu.org; Mon, 12 Mar 2018 06:31:56 -0400 Received: (qmail 13406 invoked by uid 484); 12 Mar 2018 10:31:39 -0000 Received: from unknown (HELO localhost.localdomain) (Authenticated_SSL:abouassida@[41.224.44.126]) (envelope-sender ) by smtp1.lauterbach.com (qmail-ldap-1.03) with ECDHE-RSA-AES256-SHA encrypted SMTP for ; 12 Mar 2018 10:31:38 -0000 X-Qmail-Scanner-Diagnostics: from 41.224.44.126 by smtp1.lauterbach.com (envelope-from , uid 484) with qmail-scanner-2.11 (mhr: 1.0. clamdscan: 0.99/21437. spamassassin: 3.4.0. Clear:RC:1(41.224.44.126):. Processed in 0.051406 secs); 12 Mar 2018 10:31:39 -0000 From: Abdallah Bouassida To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Mon, 12 Mar 2018 11:31:28 +0100 Message-Id: <1520850690-23245-3-git-send-email-abdallah.bouassida@lauterbach.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1520850690-23245-1-git-send-email-abdallah.bouassida@lauterbach.com> References: <1520850690-23245-1-git-send-email-abdallah.bouassida@lauterbach.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 62.154.241.196 Subject: [Qemu-devel] [PATCH v4 2/4] target/arm: Add "_S" suffix to the secure version of a sysreg X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: khaled.jmal@lauterbach.com, qemu-arm@nongnu.org, Abdallah Bouassida Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is a preparation for the coming feature of creating dynamically an XML description for the ARM sysregs. Add "_S" suffix to the secure version of sysregs that have both S and NS vi= ews Replace (S) by _S and remove (NS) for the register that are manually define= d, so all the registers follow the same convention. Signed-off-by: Abdallah Bouassida Reviewed-by: Peter Maydell --- target/arm/helper.c | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index c5d62c8..3b31f71 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -694,12 +694,12 @@ static const ARMCPRegInfo cp_reginfo[] =3D { * the secure register to be properly reset and migrated. There is als= o no * v8 EL1 version of the register so the non-secure instance stands al= one. */ - { .name =3D "FCSEIDR(NS)", + { .name =3D "FCSEIDR", .cp =3D 15, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .secure =3D ARM_CP_SECSTATE_NS, .fieldoffset =3D offsetof(CPUARMState, cp15.fcseidr_ns), .resetvalue =3D 0, .writefn =3D fcse_write, .raw_writefn =3D raw_wri= te, }, - { .name =3D "FCSEIDR(S)", + { .name =3D "FCSEIDR_S", .cp =3D 15, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .secure =3D ARM_CP_SECSTATE_S, .fieldoffset =3D offsetof(CPUARMState, cp15.fcseidr_s), @@ -715,7 +715,7 @@ static const ARMCPRegInfo cp_reginfo[] =3D { .access =3D PL1_RW, .secure =3D ARM_CP_SECSTATE_NS, .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_el[1]), .resetvalue =3D 0, .writefn =3D contextidr_write, .raw_writefn =3D r= aw_write, }, - { .name =3D "CONTEXTIDR(S)", .state =3D ARM_CP_STATE_AA32, + { .name =3D "CONTEXTIDR_S", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 1, .access =3D PL1_RW, .secure =3D ARM_CP_SECSTATE_S, .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_s), @@ -1966,7 +1966,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { cp15.c14_timer[GTIMER_PHYS].ctl), .writefn =3D gt_phys_ctl_write, .raw_writefn =3D raw_write, }, - { .name =3D "CNTP_CTL(S)", + { .name =3D "CNTP_CTL_S", .cp =3D 15, .crn =3D 14, .crm =3D 2, .opc1 =3D 0, .opc2 =3D 1, .secure =3D ARM_CP_SECSTATE_S, .type =3D ARM_CP_IO | ARM_CP_ALIAS, .access =3D PL1_RW | PL0_R, @@ -2005,7 +2005,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { .accessfn =3D gt_ptimer_access, .readfn =3D gt_phys_tval_read, .writefn =3D gt_phys_tval_write, }, - { .name =3D "CNTP_TVAL(S)", + { .name =3D "CNTP_TVAL_S", .cp =3D 15, .crn =3D 14, .crm =3D 2, .opc1 =3D 0, .opc2 =3D 0, .secure =3D ARM_CP_SECSTATE_S, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL1_RW | PL0_R, @@ -2059,7 +2059,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { .accessfn =3D gt_ptimer_access, .writefn =3D gt_phys_cval_write, .raw_writefn =3D raw_write, }, - { .name =3D "CNTP_CVAL(S)", .cp =3D 15, .crm =3D 14, .opc1 =3D 2, + { .name =3D "CNTP_CVAL_S", .cp =3D 15, .crm =3D 14, .opc1 =3D 2, .secure =3D ARM_CP_SECSTATE_S, .access =3D PL1_RW | PL0_R, .type =3D ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, @@ -5562,7 +5562,8 @@ CpuDefinitionInfoList *arch_query_cpu_definitions(Err= or **errp) =20 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, void *opaque, int state, int secstate, - int crm, int opc1, int opc2) + int crm, int opc1, int opc2, + const char *name) { /* Private utility function for define_one_arm_cp_reg_with_opaque(): * add a single reginfo struct to the hash table. @@ -5572,6 +5573,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, int is64 =3D (r->type & ARM_CP_64BIT) ? 1 : 0; int ns =3D (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; =20 + r2->name =3D g_strdup(name); /* Reset the secure state to the specific incoming state. This is * necessary as the register may have been defined with both states. */ @@ -5803,19 +5805,24 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, /* Under AArch32 CP registers can be common * (same for secure and non-secure world) or banke= d. */ + char *name; + switch (r->secure) { case ARM_CP_SECSTATE_S: case ARM_CP_SECSTATE_NS: add_cpreg_to_hashtable(cpu, r, opaque, state, - r->secure, crm, opc1, o= pc2); + r->secure, crm, opc1, o= pc2, + r->name); break; default: + name =3D g_strdup_printf("%s_S", r->name); add_cpreg_to_hashtable(cpu, r, opaque, state, ARM_CP_SECSTATE_S, - crm, opc1, opc2); + crm, opc1, opc2, name); + g_free(name); add_cpreg_to_hashtable(cpu, r, opaque, state, ARM_CP_SECSTATE_NS, - crm, opc1, opc2); + crm, opc1, opc2, r->nam= e); break; } } else { @@ -5823,7 +5830,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, * of AArch32 */ add_cpreg_to_hashtable(cpu, r, opaque, state, ARM_CP_SECSTATE_NS, - crm, opc1, opc2); + crm, opc1, opc2, r->name); } } } --=20 2.7.4 From nobody Sat Oct 25 08:57:38 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1520850889787545.4632942076366; Mon, 12 Mar 2018 03:34:49 -0700 (PDT) Received: from localhost ([::1]:57603 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1evKn2-0006GG-VV for importer@patchew.org; Mon, 12 Mar 2018 06:34:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39000) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1evKkJ-0004Mo-1h for qemu-devel@nongnu.org; Mon, 12 Mar 2018 06:32:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1evKkH-0003dC-Dp for qemu-devel@nongnu.org; Mon, 12 Mar 2018 06:31:59 -0400 Received: from smtp1.lauterbach.com ([62.154.241.196]:37072) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1evKkH-00038m-1s for qemu-devel@nongnu.org; Mon, 12 Mar 2018 06:31:57 -0400 Received: (qmail 13441 invoked by uid 484); 12 Mar 2018 10:31:40 -0000 Received: from unknown (HELO localhost.localdomain) (Authenticated_SSL:abouassida@[41.224.44.126]) (envelope-sender ) by smtp1.lauterbach.com (qmail-ldap-1.03) with ECDHE-RSA-AES256-SHA encrypted SMTP for ; 12 Mar 2018 10:31:39 -0000 X-Qmail-Scanner-Diagnostics: from 41.224.44.126 by smtp1.lauterbach.com (envelope-from , uid 484) with qmail-scanner-2.11 (mhr: 1.0. clamdscan: 0.99/21437. spamassassin: 3.4.0. Clear:RC:1(41.224.44.126):. Processed in 0.052094 secs); 12 Mar 2018 10:31:40 -0000 From: Abdallah Bouassida To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Mon, 12 Mar 2018 11:31:29 +0100 Message-Id: <1520850690-23245-4-git-send-email-abdallah.bouassida@lauterbach.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1520850690-23245-1-git-send-email-abdallah.bouassida@lauterbach.com> References: <1520850690-23245-1-git-send-email-abdallah.bouassida@lauterbach.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 62.154.241.196 Subject: [Qemu-devel] [PATCH v4 3/4] target/arm: Add the XML dynamic generation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: khaled.jmal@lauterbach.com, qemu-arm@nongnu.org, Abdallah Bouassida Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Generate an XML description for the cp-regs. Register these regs with the gdb_register_coprocessor(). Add arm_gdb_get_sysreg() to use it as a callback to read those regs. Add a dummy arm_gdb_set_sysreg(). Signed-off-by: Abdallah Bouassida --- gdbstub.c | 10 ++++++++ include/qom/cpu.h | 5 +++- target/arm/cpu.c | 1 + target/arm/cpu.h | 17 +++++++++++++ target/arm/gdbstub.c | 71 ++++++++++++++++++++++++++++++++++++++++++++++++= ++++ target/arm/helper.c | 27 ++++++++++++++++++++ 6 files changed, 130 insertions(+), 1 deletion(-) diff --git a/gdbstub.c b/gdbstub.c index f1d5148..160bdbd 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -674,6 +674,16 @@ static const char *get_feature_xml(const char *p, cons= t char **newp, } return target_xml; } + if (cc->gdb_get_dynamic_xml) { + CPUState *cpu =3D first_cpu; + char *xmlname =3D g_strndup(p, len); + const char *xml =3D cc->gdb_get_dynamic_xml(cpu, xmlname, len); + + free(xmlname); + if (xml) { + return xml; + } + } for (i =3D 0; ; i++) { name =3D xml_builtin[i][0]; if (!name || (strncmp(name, p, len) =3D=3D 0 && strlen(name) =3D= =3D len)) diff --git a/include/qom/cpu.h b/include/qom/cpu.h index aff88fa..3f53da7 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -131,6 +131,9 @@ struct TranslationBlock; * before the insn which triggers a watchpoint rather than after= it. * @gdb_arch_name: Optional callback that returns the architecture name kn= own * to GDB. The caller must free the returned string with g_free. + * @gdb_get_dynamic_xml: Callback to return dynamically generated XML for = the + * gdb stub. Returns a pointer to the XML contents for the specified XML= file + * or NULL if the CPU doesn't have a dynamically generated content for i= t. * @cpu_exec_enter: Callback for cpu_exec preparation. * @cpu_exec_exit: Callback for cpu_exec cleanup. * @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec. @@ -197,7 +200,7 @@ typedef struct CPUClass { const struct VMStateDescription *vmsd; const char *gdb_core_xml_file; gchar * (*gdb_arch_name)(CPUState *cpu); - + char *(*gdb_get_dynamic_xml)(CPUState *cpu, char *xmlname, size_t len); void (*cpu_exec_enter)(CPUState *cpu); void (*cpu_exec_exit)(CPUState *cpu); bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 1b3ae62..4fdda2f 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1781,6 +1781,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_num_core_regs =3D 26; cc->gdb_core_xml_file =3D "arm-core.xml"; cc->gdb_arch_name =3D arm_gdb_arch_name; + cc->gdb_get_dynamic_xml =3D arm_gdb_get_dynamic_xml; cc->gdb_stop_before_watchpoint =3D true; cc->debug_excp_handler =3D arm_debug_excp_handler; cc->debug_check_watchpoint =3D arm_debug_check_watchpoint; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 818a98a..39b4f3a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -133,6 +133,19 @@ enum { s<2n+1> maps to the most significant half of d */ =20 +/** + * DynamicGDBXMLInfo: + * @desc: Contains the XML descriptions. + * @num_cpregs: Number of the Coprocessor registers seen by GDB. + * @cpregs_keys: Array that contains the corresponding Key of + * a given cpreg with the same order of the cpreg in the XML description. + */ +typedef struct DynamicGDBXMLInfo { + char *desc; + int num_cpregs; + uint32_t *cpregs_keys; +} DynamicGDBXMLInfo; + /* CPU state for each instance of a generic timer (in cp15 c14) */ typedef struct ARMGenericTimer { uint64_t cval; /* Timer CompareValue register */ @@ -682,6 +695,8 @@ struct ARMCPU { uint64_t *cpreg_vmstate_values; int32_t cpreg_vmstate_array_len; =20 + DynamicGDBXMLInfo dyn_xml; + /* Timers used by the generic (architected) timer */ QEMUTimer *gt_timer[NUM_GTIMERS]; /* GPIO outputs for generic timer */ @@ -846,6 +861,8 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu,= vaddr addr, =20 int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); +int arm_gen_dynamic_xml(CPUState *cpu); +char *arm_gdb_get_dynamic_xml(CPUState *cpu, char *xmlname, size_t len); =20 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, int cpuid, void *opaque); diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 04c1208..debd873 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -101,3 +101,74 @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *= mem_buf, int n) /* Unknown register. */ return 0; } + +static void arm_gen_one_xml_reg_tag(GString *s, DynamicGDBXMLInfo *dyn_xml, + ARMCPRegInfo *ri, uint32_t ri_key, + bool is64) +{ + g_string_append_printf(s, "name); + g_string_append_printf(s, " bitsize=3D\"%s\"", is64 ? "64" : "32"); + g_string_append_printf(s, " group=3D\"cp_regs\"/>"); + dyn_xml->num_cpregs++; + dyn_xml->cpregs_keys =3D g_renew(uint32_t, dyn_xml->cpregs_keys, + dyn_xml->num_cpregs); + dyn_xml->cpregs_keys[dyn_xml->num_cpregs - 1] =3D ri_key; +} + +static void arm_register_sysreg_for_xml(gpointer key, gpointer value, + gpointer p) +{ + uint32_t ri_key =3D *(uint32_t *)key; + ARMCPRegInfo *ri =3D value; + void **p_array =3D p; + ARMCPU *cpu =3D ARM_CPU((CPUState *)(p_array[0])); + CPUARMState *env =3D &cpu->env; + DynamicGDBXMLInfo *dyn_xml =3D &cpu->dyn_xml; + GString *s =3D (GString *)(p_array[1]); + + if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_NO_GDB))) { + if (env->aarch64) { + if (ri->state =3D=3D ARM_CP_STATE_AA64) { + arm_gen_one_xml_reg_tag(s , dyn_xml, ri, ri_key, 1); + } + } else { + if (ri->state =3D=3D ARM_CP_STATE_AA32) { + if (!arm_feature(env, ARM_FEATURE_EL3) && + (ri->secure & ARM_CP_SECSTATE_S)) { + return; + } + if (ri->type & ARM_CP_64BIT) { + arm_gen_one_xml_reg_tag(s , dyn_xml, ri, ri_key, 1); + } else { + arm_gen_one_xml_reg_tag(s , dyn_xml, ri, ri_key, 0); + } + } + } + } +} + +int arm_gen_dynamic_xml(CPUState *cs) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + GString *s =3D g_string_new(NULL); + void *p_array[] =3D {cs, s}; + + cpu->dyn_xml.num_cpregs =3D 0; + g_string_printf(s, ""); + g_string_append_printf(s, "= "); + g_string_append_printf(s, ""); + g_hash_table_foreach(cpu->cp_regs, arm_register_sysreg_for_xml, p_arra= y); + g_string_append_printf(s, ""); + cpu->dyn_xml.desc =3D g_string_free(s, false); + return cpu->dyn_xml.num_cpregs; +} + +char *arm_gdb_get_dynamic_xml(CPUState *cs, char *xmlname, size_t len) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + + if (strncmp(xmlname, "system-registers.xml", len) =3D=3D 0) { + return cpu->dyn_xml.desc; + } + return NULL; +} diff --git a/target/arm/helper.c b/target/arm/helper.c index 3b31f71..5929e0b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -219,6 +219,29 @@ static void write_raw_cp_reg(CPUARMState *env, const A= RMCPRegInfo *ri, } } =20 +static int arm_gdb_get_sysreg(CPUARMState *env, uint8_t *buf, int reg) +{ + ARMCPU *cpu =3D arm_env_get_cpu(env); + const ARMCPRegInfo *ri; + uint32_t key; + + key =3D cpu->dyn_xml.cpregs_keys[reg]; + ri =3D get_arm_cp_reginfo(cpu->cp_regs, key); + if (ri) { + if (cpreg_field_is_64bit(ri)) { + return gdb_get_reg64(buf, (uint64_t)read_raw_cp_reg(env, ri)); + } else { + return gdb_get_reg32(buf, (uint32_t)read_raw_cp_reg(env, ri)); + } + } + return 0; +} + +static int arm_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg) +{ + return 0; +} + static bool raw_accessors_invalid(const ARMCPRegInfo *ri) { /* Return true if the regdef would cause an assertion if you called @@ -5458,6 +5481,7 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *c= pu) { CPUState *cs =3D CPU(cpu); CPUARMState *env =3D &cpu->env; + int n; =20 if (arm_feature(env, ARM_FEATURE_AARCH64)) { gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg, @@ -5473,6 +5497,9 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *c= pu) gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 19, "arm-vfp.xml", 0); } + n =3D arm_gen_dynamic_xml(cs); + gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg, + n, "system-registers.xml", 0); } =20 /* Sort alphabetically by type name, except for "any". */ --=20 2.7.4 From nobody Sat Oct 25 08:57:38 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1520851050490165.2865138957502; Mon, 12 Mar 2018 03:37:30 -0700 (PDT) Received: from localhost ([::1]:57621 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1evKpd-00007A-NG for importer@patchew.org; Mon, 12 Mar 2018 06:37:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39028) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1evKkK-0004Nk-5V for qemu-devel@nongnu.org; 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Processed in 0.131647 secs); 12 Mar 2018 10:31:41 -0000 From: Abdallah Bouassida To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Mon, 12 Mar 2018 11:31:30 +0100 Message-Id: <1520850690-23245-5-git-send-email-abdallah.bouassida@lauterbach.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1520850690-23245-1-git-send-email-abdallah.bouassida@lauterbach.com> References: <1520850690-23245-1-git-send-email-abdallah.bouassida@lauterbach.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 62.154.241.196 Subject: [Qemu-devel] [PATCH v4 4/4] target/arm: Add arm_gdb_set_sysreg() callback X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: khaled.jmal@lauterbach.com, qemu-arm@nongnu.org, Abdallah Bouassida Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 This is a callback to set the cp-regs registered by the dynamic XML. Signed-off-by: Abdallah Bouassida --- >> Adding to that our customers may need this write access, our tool TRACE3= 2=C2=AE >> needs this also in some particular cases. For example: temporary disabli= ng MMU >> to do a physical memory access. > By clearing the SCTLR bit? That's a good example of a case that > won't work reliably. If you clear the SCTLR.M bit via raw_write > this will not perform the tlb_flush() that it needs to, which > means that if anything does a memory access via the QEMU TLB > it may get the wrong cached results. If you always clear the > bit, do one gdb memory access then set the bit then it will > probably not run into problems but you're walking on thin ice. Does adding tlb_flush() before or after write_raw_cp_reg() could solve the reliability issue for other particular cases? Or is there any improvement that could be done for this write callback in order to get more reliable results for other particular cases? target/arm/helper.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 5929e0b..bb5a97c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -239,6 +239,20 @@ static int arm_gdb_get_sysreg(CPUARMState *env, uint8_= t *buf, int reg) =20 static int arm_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg) { + ARMCPU *cpu =3D arm_env_get_cpu(env); + const ARMCPRegInfo *ri; + uint32_t key; + uint32_t tmp; + + tmp =3D ldl_p(buf); + key =3D cpu->dyn_xml.cpregs_keys[reg]; + ri =3D get_arm_cp_reginfo(arm_env_get_cpu(env)->cp_regs, key); + if (ri) { + if (!(ri->type & ARM_CP_CONST)) { + write_raw_cp_reg(env, ri, tmp); + return cpreg_field_is_64bit(ri) ? 8 : 4; + } + } return 0; } =20 --=20 2.7.4