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[125.237.39.90]) by smtp.gmail.com with ESMTPSA id h15sm334141pfi.56.2018.03.08.20.14.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 08 Mar 2018 20:14:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=sZu9amHft6wew0OyJ4XWOSGVSF4sKnLeBx/7kRVhuhA=; b=EGWmvCSO6cuwCratwQpnQ9sijBEjpPS2SZf5KnZEf635KB61+5rDSwIKUnG+LZrwlG nvHFUMX/5ykDBwnfhMGpxu4iCLfwk5PgpnylVfcG/Np9N2aThu1VsGRf5ohFoM7+GsFo AhCvS7B3IuRJXis5La1UCm01uc5B3gPHWoOFaMpbKKbXTklf1k6cgclqO5DRwFg76qUB aijI1vYRTYRqu9l3NsWplvt5mDXIqhemw4VrOSRC7xpadZekRiuMWp2yogleqi2AKbWD TV3myo0WVjk/ber5S1hqm+pBdIdHiPgo9d6Lk9z62HgH7ywGH1ZKHTnTMNRDjSWiDluU T6Lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=sZu9amHft6wew0OyJ4XWOSGVSF4sKnLeBx/7kRVhuhA=; b=uf2MKu4ToiK30x/6tVnClJWsu20KRgFck+03NL8wxF1m0zxf/75O70SFAM1X9Xs9Xh L9HOAPcR5cDXUd/xH/QFSfTorYI9ipmlnq1cshrl/IPBbKSyX+lGVtPhovO8Qr89Dttc YYwWQeSL7NfeYA5PjIG7LydfJulSWRvlAnE3LDKankEL9IoMKRe1TwQuNQQWD/SODvhI S8IViGjPrT7KQWY5Zs1+kW+xXPFMBF+vIV75RZ4dSBJCIEOJuI+sY5JEfWBL/YmwJOnt oN2mVtbC0RClatGDKOXMhnyHJ7QYNQdo+0jmbgX2tXnRR+xf/7vchkQnO8Dsx3odXnam BzJg== X-Gm-Message-State: APf1xPA1CsRa/2LsP1KxuG0oD1dqzeGvT9tUTA26kQD0AokqpWK11Ev9 WmMiL6CyCbJujSSwo5GPMsGhkMur0Tk= X-Google-Smtp-Source: AG47ELs1i+MSYUi6gWj95bs7piHRRRauBLq7+3f1jCsKNKMwzBS9ddS7/pHTYIk6q2lHghRLdLlCXQ== X-Received: by 10.99.1.148 with SMTP id 142mr23687242pgb.24.1520568852267; Thu, 08 Mar 2018 20:14:12 -0800 (PST) From: Michael Clark To: qemu-devel@nongnu.org Date: Fri, 9 Mar 2018 17:12:23 +1300 Message-Id: <1520568765-58189-2-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1520568765-58189-1-git-send-email-mjc@sifive.com> References: <1520568765-58189-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH v2 01/23] RISC-V: Make virt create_fdt interface consistent X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Michael Clark , Palmer Dabbelt , Sagar Karandikar Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" create_fdt sets the fdt variable on RISCVVirtState and this is used to access the fdt. This reverts a change introduced in https://github.com/riscv/riscv-qemu/pull/109 which introduced a redundant return value, overlooking the RISCVVirtState structure member that made create_fdt inconsistent with the other RISC-V machines. The other alternative is to change the other boards to return the fdt. Note: the RISCVVirtState also contains fdt_size. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/virt.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index e2c214e..37968d2 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -108,7 +108,7 @@ static hwaddr load_initrd(const char *filename, uint64_= t mem_size, return *start + size; } =20 -static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memma= p, +static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, uint64_t mem_size, const char *cmdline) { void *fdt; @@ -264,8 +264,6 @@ static void *create_fdt(RISCVVirtState *s, const struct= MemmapEntry *memmap, qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); g_free(nodename); - - return fdt; } =20 static void riscv_virt_board_init(MachineState *machine) @@ -279,7 +277,6 @@ static void riscv_virt_board_init(MachineState *machine) char *plic_hart_config; size_t plic_hart_config_len; int i; - void *fdt; =20 /* Initialize SOC */ object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY); @@ -299,7 +296,7 @@ static void riscv_virt_board_init(MachineState *machine) main_mem); =20 /* create device tree */ - fdt =3D create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdli= ne); + create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); =20 /* boot rom */ memory_region_init_ram(boot_rom, NULL, "riscv_virt_board.bootrom", @@ -314,9 +311,9 @@ static void riscv_virt_board_init(MachineState *machine) hwaddr end =3D load_initrd(machine->initrd_filename, machine->ram_size, kernel_entry, &start); - qemu_fdt_setprop_cell(fdt, "/chosen", - "linux,initrd-start", start); - qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", + qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-start", + start); + qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", end); } } --=20 2.7.0 From nobody Mon May 20 15:50:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 152056900252622.641543394805467; Thu, 8 Mar 2018 20:16:42 -0800 (PST) Received: from localhost ([::1]:43104 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eu9ST-0005C9-Ip for importer@patchew.org; Thu, 08 Mar 2018 23:16:41 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55581) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eu9Q9-0003px-RA for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:14:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eu9Q8-0006pL-JQ for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:14:17 -0500 Received: from mail-pf0-x241.google.com ([2607:f8b0:400e:c00::241]:45617) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eu9Q8-0006p6-BI for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:14:16 -0500 Received: by mail-pf0-x241.google.com with SMTP id h19so828827pfd.12 for ; Thu, 08 Mar 2018 20:14:16 -0800 (PST) Received: from localhost.localdomain (125-237-39-90-fibre.bb.spark.co.nz. [125.237.39.90]) by smtp.gmail.com with ESMTPSA id h15sm334141pfi.56.2018.03.08.20.14.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 08 Mar 2018 20:14:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QPBz7Fnm8zCTZxjDgsY9fojmmXnmGLqeFGCqpRAlGF4=; b=BbPbfN4sBat+o9X9sfXEsVtmvlkYjqR8XipEVb8dYgiO2b1/jst5oQq4Sx2XBNtZRp Fn8opQzej8m00AalnO+e+w3m9mTxr1aiQRECKBeivn0ybanuy8iNtpW5OLQRk+8l5Pwo 1puoAVOAgnyuwBakgPT2uLBG3Di8+UUAwQ7xkbOmOC3H1YtPRU+YaO4DElmhK+dmyJt4 P8XpLPUYY2x7LIqujCh/DOrggiPKnyBz0DkT9atZvxya4KRNOkZySbRV1fyluxQM+kTG p1xKQf8oELKZuopYd5wLCnHJfpMh8dOMWodJjfUbf9FF/kXt+E+NWQXQ4B/MX9pgYAFI Z/pA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QPBz7Fnm8zCTZxjDgsY9fojmmXnmGLqeFGCqpRAlGF4=; b=VJkM1uvf1amWD7HlYIBmCrUSqmiip9PKalqFy8/ineyOxeydG6RxBp5dhC9lygfirV xrhO/KUUZGgyhCckLu6FzoKT5jXhhTV8mQN56ZURHxcUebrZ51rqgr54yTP6tJROzs/q OkUrxhsev4y4mrTFe+8UubSFlNfTAZ5k/R/ASABCSUSEpb/Nas5wohn0VTcrWdGOwFE5 E1re4eWBFGfXTA9Gq2jYfDoyqk2DcDIT5/9FGyQRAKyW39REtjVQKn0PdbE/idFpff+l D30W9I8HID5qgKt30z8CJ5jGWbMc/q/6udzYKC2IDw8jc3W9kj67Jp5cwYQHO7Ij3O9j Rtpw== X-Gm-Message-State: APf1xPBsKNrKuvzMVXNSZduFhB1Cfwt6HJOhc9SQFpKjeBsTkxGs9vy4 byJk+R+vorCzBcpLkttKLPss4VeW988= X-Google-Smtp-Source: AG47ELuLJ6KW4iIXeIHl0Qu5P3K0J0QjukYaSd50qVIUqMlXW7j5hJbawVAHnIAY/BefyPYrsoETIg== X-Received: by 10.98.31.79 with SMTP id f76mr28739769pff.60.1520568855291; Thu, 08 Mar 2018 20:14:15 -0800 (PST) From: Michael Clark To: qemu-devel@nongnu.org Date: Fri, 9 Mar 2018 17:12:24 +1300 Message-Id: <1520568765-58189-3-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1520568765-58189-1-git-send-email-mjc@sifive.com> References: <1520568765-58189-1-git-send-email-mjc@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v2 02/23] RISC-V: Replace hardcoded constants with enum values X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Michael Clark , Palmer Dabbelt , Sagar Karandikar Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 The RISC-V device-tree code has a number of hard-coded constants and this change moves them into header enums. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/sifive_clint.c | 9 +++------ hw/riscv/sifive_u.c | 6 ++++-- hw/riscv/spike.c | 6 ++++-- hw/riscv/virt.c | 6 ++++-- include/hw/riscv/sifive_clint.h | 4 ++++ include/hw/riscv/sifive_u.h | 4 ++++ include/hw/riscv/spike.h | 4 ++++ include/hw/riscv/virt.h | 4 ++++ 8 files changed, 31 insertions(+), 12 deletions(-) diff --git a/hw/riscv/sifive_clint.c b/hw/riscv/sifive_clint.c index 4893453..7cc606e 100644 --- a/hw/riscv/sifive_clint.c +++ b/hw/riscv/sifive_clint.c @@ -26,13 +26,10 @@ #include "hw/riscv/sifive_clint.h" #include "qemu/timer.h" =20 -/* See: riscv-pk/machine/sbi_entry.S and arch/riscv/kernel/time.c */ -#define TIMER_FREQ (10 * 1000 * 1000) - static uint64_t cpu_riscv_read_rtc(void) { - return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), TIMER_FREQ, - NANOSECONDS_PER_SECOND); + return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + SIFIVE_CLINT_TIMEBASE_FREQ, NANOSECONDS_PER_SECOND); } =20 /* @@ -59,7 +56,7 @@ static void sifive_clint_write_timecmp(RISCVCPU *cpu, uin= t64_t value) diff =3D cpu->env.timecmp - rtc_r; /* back to ns (note args switched in muldiv64) */ next =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + - muldiv64(diff, NANOSECONDS_PER_SECOND, TIMER_FREQ); + muldiv64(diff, NANOSECONDS_PER_SECOND, SIFIVE_CLINT_TIMEBASE_FREQ); timer_mod(cpu->env.timer, next); } =20 diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 1c2deef..f3f7615 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -122,7 +122,8 @@ static void create_fdt(SiFiveUState *s, const struct Me= mmapEntry *memmap, g_free(nodename); =20 qemu_fdt_add_subnode(fdt, "/cpus"); - qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 10000000); + qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", + SIFIVE_CLINT_TIMEBASE_FREQ); qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); =20 @@ -131,7 +132,8 @@ static void create_fdt(SiFiveUState *s, const struct Me= mmapEntry *memmap, char *intc =3D g_strdup_printf("/cpus/cpu@%d/interrupt-controller"= , cpu); char *isa =3D riscv_isa_string(&s->soc.harts[cpu]); qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 1000000000= ); + qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", + SIFIVE_U_CLOCK_FREQ); qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 2d1f114..4c233ec 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -115,7 +115,8 @@ static void create_fdt(SpikeState *s, const struct Memm= apEntry *memmap, g_free(nodename); =20 qemu_fdt_add_subnode(fdt, "/cpus"); - qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 10000000); + qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", + SIFIVE_CLINT_TIMEBASE_FREQ); qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); =20 @@ -124,7 +125,8 @@ static void create_fdt(SpikeState *s, const struct Memm= apEntry *memmap, char *intc =3D g_strdup_printf("/cpus/cpu@%d/interrupt-controller"= , cpu); char *isa =3D riscv_isa_string(&s->soc.harts[cpu]); qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 1000000000= ); + qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", + SPIKE_CLOCK_FREQ); qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 37968d2..a402856 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -145,7 +145,8 @@ static void create_fdt(RISCVVirtState *s, const struct = MemmapEntry *memmap, g_free(nodename); =20 qemu_fdt_add_subnode(fdt, "/cpus"); - qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 10000000); + qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", + SIFIVE_CLINT_TIMEBASE_FREQ); qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); =20 @@ -155,7 +156,8 @@ static void create_fdt(RISCVVirtState *s, const struct = MemmapEntry *memmap, char *intc =3D g_strdup_printf("/cpus/cpu@%d/interrupt-controller"= , cpu); char *isa =3D riscv_isa_string(&s->soc.harts[cpu]); qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 1000000000= ); + qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", + VIRT_CLOCK_FREQ); qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); diff --git a/include/hw/riscv/sifive_clint.h b/include/hw/riscv/sifive_clin= t.h index aaa2a58..e2865be 100644 --- a/include/hw/riscv/sifive_clint.h +++ b/include/hw/riscv/sifive_clint.h @@ -47,4 +47,8 @@ enum { SIFIVE_TIME_BASE =3D 0xBFF8 }; =20 +enum { + SIFIVE_CLINT_TIMEBASE_FREQ =3D 10000000 +}; + #endif diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 662e8a1..be38aa0 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -50,6 +50,10 @@ enum { SIFIVE_U_UART1_IRQ =3D 4 }; =20 +enum { + SIFIVE_U_CLOCK_FREQ =3D 1000000000 +}; + #define SIFIVE_U_PLIC_HART_CONFIG "MS" #define SIFIVE_U_PLIC_NUM_SOURCES 127 #define SIFIVE_U_PLIC_NUM_PRIORITIES 7 diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h index cb55a14..d85a64e 100644 --- a/include/hw/riscv/spike.h +++ b/include/hw/riscv/spike.h @@ -42,6 +42,10 @@ enum { SPIKE_DRAM }; =20 +enum { + SPIKE_CLOCK_FREQ =3D 1000000000 +}; + #if defined(TARGET_RISCV32) #define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV32GCSU_V1_09_1 #define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0 diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 7525647..2fbe808 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -55,6 +55,10 @@ enum { VIRTIO_NDEV =3D 10 }; =20 +enum { + VIRT_CLOCK_FREQ =3D 1000000000 +}; + #define VIRT_PLIC_HART_CONFIG "MS" #define VIRT_PLIC_NUM_SOURCES 127 #define VIRT_PLIC_NUM_PRIORITIES 7 --=20 2.7.0 From nobody Mon May 20 15:50:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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[125.237.39.90]) by smtp.gmail.com with ESMTPSA id h15sm334141pfi.56.2018.03.08.20.14.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 08 Mar 2018 20:14:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=D2hpYq+xsLCLn+qK+ZFYTy/oLGvcpaSH4HzC7QRDYfk=; b=dfhDhDyHL16d8wDbHQAsjce4E07HrOGW7NP2VKwrapYvdiHgf9wCV3KMfnK3UV5qAj nIve4NPh0OV8vv4C8JmUXQefB+CcMgfGr+7BODlxZ99x5FukKmLZEdXLrBIjoFCXRSFn H0rZRIZluJA2u9vM1cMblXh35pB/CehBR9b7avcKiLJWGv6fv7cLag0MBRePZSbKkWx/ V/LLtmbWxb1UNjDByhdKa5JKPFJqG+O+vSRKqTr3W+Kz9J4S7ZvpdzUcgut9mmmJzjpq zFx4zgPnSnL5F9inkqx4gUlJNGPR8lYwCmS+pVlasO2S9n+9g//Km2iIqL/Mkk967VrZ YUPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=D2hpYq+xsLCLn+qK+ZFYTy/oLGvcpaSH4HzC7QRDYfk=; b=Tjs9BRUYY3Zi892e6X8MK/WIPQEz2wcVioKQvc199cwH3KdKrb1xvSvM35S27Mbe4I r2G4EAW7+RpoFHDZ2WyyTj25yH1SKKTZlpkxejIX04wLHaiBOGlINAE0pCIHc56uo81x GT+h1OhJib9zex4Fat9R8ez+2c/K4J5qGQ2Df4IxRS4SkUulTV5tc7RV/LjEaDM2VyVb UiqxaeJunlH/ctPOnrxcEes6WAFMzf1YjJ2cw7f53NST4Ke/HmE1XlJVfykaOrHFFDFN OrtJBHlKpPInfOU3waxW5AQRdgkhyVWKRYqFTIuFq/1jLMiJrAKyW9tnfh1yKpgWsp6I 8HyQ== X-Gm-Message-State: APf1xPCJDCPy5ZPFgaRneebvvRVXVH/O6zkE40HB2DEYbEOf/xSJnFY4 3s2oEvYeio+d/i3OBA7YTzIZ5rWrZRc= X-Google-Smtp-Source: AG47ELuNxkKyXqPARbTWyVU+ZMxzK+naaH6zuQRWDGbWfZqKoYKSm/ISFKjXyGQ5/ZrDxzvcM0vVJw== X-Received: by 10.98.8.219 with SMTP id 88mr28680920pfi.4.1520568858241; Thu, 08 Mar 2018 20:14:18 -0800 (PST) From: Michael Clark To: qemu-devel@nongnu.org Date: Fri, 9 Mar 2018 17:12:25 +1300 Message-Id: <1520568765-58189-4-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1520568765-58189-1-git-send-email-mjc@sifive.com> References: <1520568765-58189-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH v2 03/23] RISC-V: Make virt board description match spike X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Michael Clark , Palmer Dabbelt , Sagar Karandikar Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This makes 'qemu-system-riscv64 -machine help' output more tidy and consistent. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/virt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index a402856..0055439 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -404,7 +404,7 @@ static const TypeInfo riscv_virt_board_device =3D { =20 static void riscv_virt_board_machine_init(MachineClass *mc) { - mc->desc =3D "RISC-V VirtIO Board (Privileged spec v1.10)"; + mc->desc =3D "RISC-V VirtIO Board (Privileged ISA v1.10)"; mc->init =3D riscv_virt_board_init; mc->max_cpus =3D 8; /* hardcoded limit in BBL */ } --=20 2.7.0 From nobody Mon May 20 15:50:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1520569369332573.036854213784; Thu, 8 Mar 2018 20:22:49 -0800 (PST) Received: from localhost ([::1]:43135 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eu9YJ-0001jZ-3v for importer@patchew.org; Thu, 08 Mar 2018 23:22:43 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55613) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eu9QF-0003up-90 for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:14:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eu9QE-0006rP-AU for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:14:23 -0500 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:34296) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eu9QE-0006r7-4U for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:14:22 -0500 Received: by mail-pg0-x244.google.com with SMTP id m19so3123360pgn.1 for ; Thu, 08 Mar 2018 20:14:22 -0800 (PST) Received: from localhost.localdomain (125-237-39-90-fibre.bb.spark.co.nz. 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X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH v2 04/23] RISC-V: Use ROM base address and size from memmap X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Michael Clark , Palmer Dabbelt , Sagar Karandikar Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Another case of replaceing hard coded constants, this time referring to the definition in the virt machine's memmap. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/virt.c | 4 ++-- include/hw/riscv/virt.h | 2 -- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 0055439..0d101fc 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -338,11 +338,11 @@ static void riscv_virt_board_init(MachineState *machi= ne) }; =20 /* copy in the reset vector */ - copy_le32_to_phys(ROM_BASE, reset_vec, sizeof(reset_vec)); + copy_le32_to_phys(memmap[VIRT_MROM].base, reset_vec, sizeof(reset_vec)= ); =20 /* copy in the device tree */ qemu_fdt_dumpdtb(s->fdt, s->fdt_size); - cpu_physical_memory_write(ROM_BASE + sizeof(reset_vec), + cpu_physical_memory_write(memmap[VIRT_MROM].base + sizeof(reset_vec), s->fdt, s->fdt_size); =20 /* create PLIC hart topology configuration string */ diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 2fbe808..655e85d 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -23,8 +23,6 @@ #define VIRT(obj) \ OBJECT_CHECK(RISCVVirtState, (obj), TYPE_RISCV_VIRT_BOARD) =20 -enum { ROM_BASE =3D 0x1000 }; - typedef struct { /*< private >*/ SysBusDevice parent_obj; --=20 2.7.0 From nobody Mon May 20 15:50:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1520569187688197.621002251135; Thu, 8 Mar 2018 20:19:47 -0800 (PST) Received: from localhost ([::1]:43115 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eu9VS-0007cz-SB for importer@patchew.org; Thu, 08 Mar 2018 23:19:46 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55631) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eu9QI-0003vs-Qm for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:14:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eu9QH-0006se-6R for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:14:26 -0500 Received: from mail-pg0-x241.google.com ([2607:f8b0:400e:c05::241]:44793) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eu9QH-0006sM-0b for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:14:25 -0500 Received: by mail-pg0-x241.google.com with SMTP id l4so3116524pgp.11 for ; Thu, 08 Mar 2018 20:14:24 -0800 (PST) Received: from localhost.localdomain (125-237-39-90-fibre.bb.spark.co.nz. [125.237.39.90]) by smtp.gmail.com with ESMTPSA id h15sm334141pfi.56.2018.03.08.20.14.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 08 Mar 2018 20:14:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iQkLw7e7jDGRvqEWGlEj0fd4xyCWiis5BdoY3u6ygN0=; b=bBvIMShgKA1jJOyPpJ1Dpu6iyLGvW3CAWs0Kr2H/K/yYRkdFAFLtaDJz5/CJFD8a7W vToSSive/O1zvO4XXtgXZTsyId7sAVq1mOqOBQuevhuJIhygbpMAFxdBd37WOi2K2UOP QE+BSR3QwRLT8RWex7DbTNrBsQXMhlyiqjLvqqbLnJFEzPA4AoR+KY52dSvvsZKJKXLy Rdz5R3fF+C1We786DUxAgAHbe9t996u2r3fAYrfmW9MYbTVnfhjnsF339q+rzFZfY910 Cd/aqUfq3rSO4f2Tc34uPZiLVNarZXtiEEWcCdNU43WOm4ky7KqZ1fDNpA+sRZWpXhaW obiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iQkLw7e7jDGRvqEWGlEj0fd4xyCWiis5BdoY3u6ygN0=; b=YBiG7ArWYhITuiphEs31p6kwAn4ka0k4wIiBFYNeMwAT6jEd2UudESJn4dCB/Fp3gG 7s5WAul20E5w0+i+ACKUzRh445yz/ObCjRwaOI3sssWnSvEyWdROFbRPaDsiC/dQqQgh 2881547gcga/MHt1ROj1rBJB5hYwfl5SxE9O2xhP19K4CEzdLWaLfjrn1V2UM+Zcg5DM Mn5bYncCVHSWjqNRMqp+Z7LxcBDswl9VcLb+gqzhqGS+d6i4M6FJIOGjq5Fl5DAYFFK0 O971iIdm2t6LlKEpaM7kUtaVpRhNkH1xWvnVZq9hF5LzLW6CRMTRe//rTEh63N85lfuy jhCQ== X-Gm-Message-State: APf1xPCV6EFnd1X/wcCE4sxi6NJjpdLEqJRdFyx6g1tCcahUC/qPm4VT 4D6cHEqr6tzmd8i1Fr4JbyV74YOnZLU= X-Google-Smtp-Source: AG47ELt3xXkBN1Fqm3hkuegKTyID9WR9XH8fCzXRMvoIevAETkWwaqY5cFMMQdOXTVXRiRSjebLLBA== X-Received: by 10.99.183.5 with SMTP id t5mr23530517pgf.416.1520568864082; Thu, 08 Mar 2018 20:14:24 -0800 (PST) From: Michael Clark To: qemu-devel@nongnu.org Date: Fri, 9 Mar 2018 17:12:27 +1300 Message-Id: <1520568765-58189-6-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1520568765-58189-1-git-send-email-mjc@sifive.com> References: <1520568765-58189-1-git-send-email-mjc@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH v2 05/23] RISC-V: Remove identity_translate from load_elf X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Michael Clark , Palmer Dabbelt , Sagar Karandikar Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 When load_elf is called with NULL as an argument to the address translate callback, it does an identity translation. This commit removes the redundant identity_translate callback. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/sifive_e.c | 7 +------ hw/riscv/sifive_u.c | 7 +------ hw/riscv/spike.c | 7 +------ hw/riscv/virt.c | 7 +------ 4 files changed, 4 insertions(+), 24 deletions(-) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 19eca36..09c9d49 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -82,16 +82,11 @@ static void copy_le32_to_phys(hwaddr pa, uint32_t *rom,= size_t len) } } =20 -static uint64_t identity_translate(void *opaque, uint64_t addr) -{ - return addr; -} - static uint64_t load_kernel(const char *kernel_filename) { uint64_t kernel_entry, kernel_high; =20 - if (load_elf(kernel_filename, identity_translate, NULL, + if (load_elf(kernel_filename, NULL, NULL, &kernel_entry, NULL, &kernel_high, 0, ELF_MACHINE, 1, 0) < 0) { error_report("qemu: could not load kernel '%s'", kernel_filename); diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index f3f7615..6116c38 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -68,16 +68,11 @@ static void copy_le32_to_phys(hwaddr pa, uint32_t *rom,= size_t len) } } =20 -static uint64_t identity_translate(void *opaque, uint64_t addr) -{ - return addr; -} - static uint64_t load_kernel(const char *kernel_filename) { uint64_t kernel_entry, kernel_high; =20 - if (load_elf(kernel_filename, identity_translate, NULL, + if (load_elf(kernel_filename, NULL, NULL, &kernel_entry, NULL, &kernel_high, 0, ELF_MACHINE, 1, 0) < 0) { error_report("qemu: could not load kernel '%s'", kernel_filename); diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 4c233ec..7710333 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -59,16 +59,11 @@ static void copy_le32_to_phys(hwaddr pa, uint32_t *rom,= size_t len) } } =20 -static uint64_t identity_translate(void *opaque, uint64_t addr) -{ - return addr; -} - static uint64_t load_kernel(const char *kernel_filename) { uint64_t kernel_entry, kernel_high; =20 - if (load_elf_ram_sym(kernel_filename, identity_translate, NULL, + if (load_elf_ram_sym(kernel_filename, NULL, NULL, &kernel_entry, NULL, &kernel_high, 0, ELF_MACHINE, 1, 0, NULL, true, htif_symbol_callback) < 0) { error_report("qemu: could not load kernel '%s'", kernel_filename); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 0d101fc..f8c19b4 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -62,16 +62,11 @@ static void copy_le32_to_phys(hwaddr pa, uint32_t *rom,= size_t len) } } =20 -static uint64_t identity_translate(void *opaque, uint64_t addr) -{ - return addr; -} - static uint64_t load_kernel(const char *kernel_filename) { uint64_t kernel_entry, kernel_high; =20 - if (load_elf(kernel_filename, identity_translate, NULL, + if (load_elf(kernel_filename, NULL, NULL, &kernel_entry, NULL, &kernel_high, 0, ELF_MACHINE, 1, 0) < 0) { error_report("qemu: could not load kernel '%s'", kernel_filename); --=20 2.7.0 From nobody Mon May 20 15:50:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1520569017877469.56543330634304; Thu, 8 Mar 2018 20:16:57 -0800 (PST) Received: from localhost ([::1]:43105 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eu9Sj-0005PC-1e for importer@patchew.org; Thu, 08 Mar 2018 23:16:57 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55663) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eu9QN-00040I-FN for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:14:33 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eu9QK-0006tU-9j for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:14:31 -0500 Received: from mail-pl0-x243.google.com ([2607:f8b0:400e:c01::243]:44591) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eu9QK-0006tG-14 for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:14:28 -0500 Received: by mail-pl0-x243.google.com with SMTP id 9-v6so4604142ple.11 for ; Thu, 08 Mar 2018 20:14:27 -0800 (PST) Received: from localhost.localdomain (125-237-39-90-fibre.bb.spark.co.nz. [125.237.39.90]) by smtp.gmail.com with ESMTPSA id h15sm334141pfi.56.2018.03.08.20.14.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 08 Mar 2018 20:14:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KXs31ZQPDLR7Vw784vZDJ7FehxZMGqH0wnzWcDgDVRA=; b=ctyC2h9t5JUL0nYBIe2CL995WSHZ7v+rKkA5vWz1b/z9Ok92D5hs4pV2/NOdH+6bLj waIthvPEhCoFAH5w7M8KjMB0DMmVd/uSvxrxbnl0n/QGaw5TVDqs3XIm46salFoPNph3 nKG7YoPR431sA+wzNY6oLVbixvriqo0tE67inX+O2WZr9frKUPtYcgRL6iOzpSN/IUlT cR23B4TmNpnBlVtuGw9hXA8q89ih8TdYPXpEwOriUF/gmMdiUau/eAqTK2Q1EstCOPm7 iIc7ZNvJCtqwD7tMMTmkHsLYngttaEJZ8WA8lJOAUCVdivRG6HRZGC03wcynEroJB1R4 PRqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KXs31ZQPDLR7Vw784vZDJ7FehxZMGqH0wnzWcDgDVRA=; b=ICZnd7/yHd7JK3YpsHX3QYE7XLVXUMsARDnWCXJKo6yniIOZYg5EoQtCnlGc3zuQ4L Oi8nZQqK6CHhV6+MskXOg0eTjj2B9RDUWA2zxsMqn2rmRcbLviw/UYOQaCxvcgyK8r3W 9hSG9B7bbsBXq2tRXFQnZ3bqjKw4EAoNrId7n9io2lCs0NAhBXrslwW7ENGGxp/w+qaT gv+EALObnxI6mTaCVOqD4GVBXh3tpEjitUPxE6sZ/D4iYTQPSDgnmIgvIjm8EE78bQD3 IL/iO2g56QjdQfghTR5VhkKuXHnSdY0Zc0aavSu7LU8fFguT2nuVcRjBDxM4A7rVlwf3 g/7Q== X-Gm-Message-State: APf1xPAzHCsSQHexGTth3nshsheKkNLan0ZfoHVg1cELpu/11Lk1gH3D oX36ztJcRcyDyJ3cKuhmnbaID32LWkU= X-Google-Smtp-Source: AG47ELu4LzyRTEfUBQadydHMz+YChDOJahEgqFqp0nW4lvtoY5Coq6dg58rMuD/yr9sQgsOL7o8FGg== X-Received: by 2002:a17:902:5269:: with SMTP id z96-v6mr26344408plh.385.1520568867029; Thu, 08 Mar 2018 20:14:27 -0800 (PST) From: Michael Clark To: qemu-devel@nongnu.org Date: Fri, 9 Mar 2018 17:12:28 +1300 Message-Id: <1520568765-58189-7-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1520568765-58189-1-git-send-email-mjc@sifive.com> References: <1520568765-58189-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PATCH v2 06/23] RISC-V: Mark ROM read-only after copying in code X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Michael Clark , Palmer Dabbelt , Sagar Karandikar Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The sifive_u machine already marks its ROM readonly. This fixes the remaining boards. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 9 +++++---- hw/riscv/spike.c | 18 ++++++++++-------- hw/riscv/virt.c | 7 ++++--- include/hw/riscv/spike.h | 8 -------- 4 files changed, 19 insertions(+), 23 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 6116c38..25df16c 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -223,7 +223,7 @@ static void riscv_sifive_u_init(MachineState *machine) SiFiveUState *s =3D g_new0(SiFiveUState, 1); MemoryRegion *sys_memory =3D get_system_memory(); MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); - MemoryRegion *boot_rom =3D g_new(MemoryRegion, 1); + MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); =20 /* Initialize SOC */ object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY); @@ -246,10 +246,10 @@ static void riscv_sifive_u_init(MachineState *machine) create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); =20 /* boot rom */ - memory_region_init_ram(boot_rom, NULL, "riscv.sifive.u.mrom", + memory_region_init_ram(mask_rom, NULL, "riscv.sifive.u.mrom", memmap[SIFIVE_U_MROM].base, &error_fatal); - memory_region_set_readonly(boot_rom, true); - memory_region_add_subregion(sys_memory, 0x0, boot_rom); + memory_region_set_readonly(mask_rom, true); + memory_region_add_subregion(sys_memory, 0x0, mask_rom); =20 if (machine->kernel_filename) { load_kernel(machine->kernel_filename); @@ -279,6 +279,7 @@ static void riscv_sifive_u_init(MachineState *machine) qemu_fdt_dumpdtb(s->fdt, s->fdt_size); cpu_physical_memory_write(memmap[SIFIVE_U_MROM].base + sizeof(reset_vec), s->fdt, s->fdt_size); + memory_region_set_readonly(mask_rom, true); =20 /* MMIO */ s->plic =3D sifive_plic_create(memmap[SIFIVE_U_PLIC].base, diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 7710333..74edf33 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -173,7 +173,7 @@ static void spike_v1_10_0_board_init(MachineState *mach= ine) SpikeState *s =3D g_new0(SpikeState, 1); MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); - MemoryRegion *boot_rom =3D g_new(MemoryRegion, 1); + MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); =20 /* Initialize SOC */ object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY); @@ -196,9 +196,9 @@ static void spike_v1_10_0_board_init(MachineState *mach= ine) create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); =20 /* boot rom */ - memory_region_init_ram(boot_rom, NULL, "riscv.spike.bootrom", + memory_region_init_ram(mask_rom, NULL, "riscv.spike.mrom", s->fdt_size + 0x2000, &error_fatal); - memory_region_add_subregion(system_memory, 0x0, boot_rom); + memory_region_add_subregion(system_memory, 0x0, mask_rom); =20 if (machine->kernel_filename) { load_kernel(machine->kernel_filename); @@ -228,9 +228,10 @@ static void spike_v1_10_0_board_init(MachineState *mac= hine) qemu_fdt_dumpdtb(s->fdt, s->fdt_size); cpu_physical_memory_write(memmap[SPIKE_MROM].base + sizeof(reset_vec), s->fdt, s->fdt_size); + memory_region_set_readonly(mask_rom, true); =20 /* initialize HTIF using symbols found in load_kernel */ - htif_mm_init(system_memory, boot_rom, &s->soc.harts[0].env, serial_hds= [0]); + htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hds= [0]); =20 /* Core Local Interruptor (timer and IPI) */ sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size, @@ -244,7 +245,7 @@ static void spike_v1_09_1_board_init(MachineState *mach= ine) SpikeState *s =3D g_new0(SpikeState, 1); MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); - MemoryRegion *boot_rom =3D g_new(MemoryRegion, 1); + MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); =20 /* Initialize SOC */ object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY); @@ -264,9 +265,9 @@ static void spike_v1_09_1_board_init(MachineState *mach= ine) main_mem); =20 /* boot rom */ - memory_region_init_ram(boot_rom, NULL, "riscv.spike.bootrom", + memory_region_init_ram(mask_rom, NULL, "riscv.spike.mrom", 0x40000, &error_fatal); - memory_region_add_subregion(system_memory, 0x0, boot_rom); + memory_region_add_subregion(system_memory, 0x0, mask_rom); =20 if (machine->kernel_filename) { load_kernel(machine->kernel_filename); @@ -325,9 +326,10 @@ static void spike_v1_09_1_board_init(MachineState *mac= hine) /* copy in the config string */ cpu_physical_memory_write(memmap[SPIKE_MROM].base + sizeof(reset_vec), config_string, config_string_len); + memory_region_set_readonly(mask_rom, true); =20 /* initialize HTIF using symbols found in load_kernel */ - htif_mm_init(system_memory, boot_rom, &s->soc.harts[0].env, serial_hds= [0]); + htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hds= [0]); =20 /* Core Local Interruptor (timer and IPI) */ sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size, diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index f8c19b4..f1e3641 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -270,7 +270,7 @@ static void riscv_virt_board_init(MachineState *machine) RISCVVirtState *s =3D g_new0(RISCVVirtState, 1); MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); - MemoryRegion *boot_rom =3D g_new(MemoryRegion, 1); + MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); char *plic_hart_config; size_t plic_hart_config_len; int i; @@ -296,9 +296,9 @@ static void riscv_virt_board_init(MachineState *machine) create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); =20 /* boot rom */ - memory_region_init_ram(boot_rom, NULL, "riscv_virt_board.bootrom", + memory_region_init_ram(mask_rom, NULL, "riscv_virt_board.mrom", s->fdt_size + 0x2000, &error_fatal); - memory_region_add_subregion(system_memory, 0x0, boot_rom); + memory_region_add_subregion(system_memory, 0x0, mask_rom); =20 if (machine->kernel_filename) { uint64_t kernel_entry =3D load_kernel(machine->kernel_filename); @@ -339,6 +339,7 @@ static void riscv_virt_board_init(MachineState *machine) qemu_fdt_dumpdtb(s->fdt, s->fdt_size); cpu_physical_memory_write(memmap[VIRT_MROM].base + sizeof(reset_vec), s->fdt, s->fdt_size); + memory_region_set_readonly(mask_rom, true); =20 /* create PLIC hart topology configuration string */ plic_hart_config_len =3D (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpu= s; diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h index d85a64e..179b6cf 100644 --- a/include/hw/riscv/spike.h +++ b/include/hw/riscv/spike.h @@ -22,20 +22,12 @@ #define TYPE_RISCV_SPIKE_V1_09_1_BOARD "riscv.spike_v1_9_1" #define TYPE_RISCV_SPIKE_V1_10_0_BOARD "riscv.spike_v1_10" =20 -#define SPIKE(obj) \ - OBJECT_CHECK(SpikeState, (obj), TYPE_RISCV_SPIKE_BOARD) - typedef struct { - /*< private >*/ - SysBusDevice parent_obj; - - /*< public >*/ RISCVHartArrayState soc; void *fdt; int fdt_size; } SpikeState; =20 - enum { SPIKE_MROM, SPIKE_CLINT, --=20 2.7.0 From nobody Mon May 20 15:50:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1520569368666839.3038314182248; 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X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH v2 07/23] RISC-V: Remove unused class definitions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Michael Clark , Palmer Dabbelt , Sagar Karandikar Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Removes a whole lot of unnecessary boilerplate code. Machines don't need to be objects. The expansion of the SOC object model for the RISC-V machines will happen in the future as SiFive plans to add their FE310 and FU540 SOCs to QEMU. However, it seems that this present boilerplate is complete unnecessary. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/sifive_e.c | 25 ------------------------- hw/riscv/sifive_u.c | 25 ------------------------- hw/riscv/spike.c | 20 -------------------- hw/riscv/virt.c | 25 ------------------------- include/hw/riscv/sifive_e.h | 5 ----- include/hw/riscv/sifive_u.h | 5 ----- include/hw/riscv/spike.h | 7 ++++--- include/hw/riscv/virt.h | 5 ----- 8 files changed, 4 insertions(+), 113 deletions(-) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 09c9d49..4872b68 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -194,24 +194,6 @@ static void riscv_sifive_e_init(MachineState *machine) } } =20 -static int riscv_sifive_e_sysbus_device_init(SysBusDevice *sysbusdev) -{ - return 0; -} - -static void riscv_sifive_e_class_init(ObjectClass *klass, void *data) -{ - SysBusDeviceClass *k =3D SYS_BUS_DEVICE_CLASS(klass); - k->init =3D riscv_sifive_e_sysbus_device_init; -} - -static const TypeInfo riscv_sifive_e_device =3D { - .name =3D TYPE_SIFIVE_E, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(SiFiveEState), - .class_init =3D riscv_sifive_e_class_init, -}; - static void riscv_sifive_e_machine_init(MachineClass *mc) { mc->desc =3D "RISC-V Board compatible with SiFive E SDK"; @@ -220,10 +202,3 @@ static void riscv_sifive_e_machine_init(MachineClass *= mc) } =20 DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init) - -static void riscv_sifive_e_register_types(void) -{ - type_register_static(&riscv_sifive_e_device); -} - -type_init(riscv_sifive_e_register_types); diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 25df16c..083043a 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -302,31 +302,6 @@ static void riscv_sifive_u_init(MachineState *machine) SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); } =20 -static int riscv_sifive_u_sysbus_device_init(SysBusDevice *sysbusdev) -{ - return 0; -} - -static void riscv_sifive_u_class_init(ObjectClass *klass, void *data) -{ - SysBusDeviceClass *k =3D SYS_BUS_DEVICE_CLASS(klass); - k->init =3D riscv_sifive_u_sysbus_device_init; -} - -static const TypeInfo riscv_sifive_u_device =3D { - .name =3D TYPE_SIFIVE_U, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(SiFiveUState), - .class_init =3D riscv_sifive_u_class_init, -}; - -static void riscv_sifive_u_register_types(void) -{ - type_register_static(&riscv_sifive_u_device); -} - -type_init(riscv_sifive_u_register_types); - static void riscv_sifive_u_machine_init(MachineClass *mc) { mc->desc =3D "RISC-V Board compatible with SiFive U SDK"; diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 74edf33..64e585e 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -336,18 +336,6 @@ static void spike_v1_09_1_board_init(MachineState *mac= hine) smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); } =20 -static const TypeInfo spike_v_1_09_1_device =3D { - .name =3D TYPE_RISCV_SPIKE_V1_09_1_BOARD, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(SpikeState), -}; - -static const TypeInfo spike_v_1_10_0_device =3D { - .name =3D TYPE_RISCV_SPIKE_V1_10_0_BOARD, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(SpikeState), -}; - static void spike_v1_09_1_machine_init(MachineClass *mc) { mc->desc =3D "RISC-V Spike Board (Privileged ISA v1.9.1)"; @@ -365,11 +353,3 @@ static void spike_v1_10_0_machine_init(MachineClass *m= c) =20 DEFINE_MACHINE("spike_v1.9.1", spike_v1_09_1_machine_init) DEFINE_MACHINE("spike_v1.10", spike_v1_10_0_machine_init) - -static void riscv_spike_board_register_types(void) -{ - type_register_static(&spike_v_1_09_1_device); - type_register_static(&spike_v_1_10_0_device); -} - -type_init(riscv_spike_board_register_types); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index f1e3641..5913100 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -380,24 +380,6 @@ static void riscv_virt_board_init(MachineState *machin= e) serial_hds[0], DEVICE_LITTLE_ENDIAN); } =20 -static int riscv_virt_board_sysbus_device_init(SysBusDevice *sysbusdev) -{ - return 0; -} - -static void riscv_virt_board_class_init(ObjectClass *klass, void *data) -{ - SysBusDeviceClass *k =3D SYS_BUS_DEVICE_CLASS(klass); - k->init =3D riscv_virt_board_sysbus_device_init; -} - -static const TypeInfo riscv_virt_board_device =3D { - .name =3D TYPE_RISCV_VIRT_BOARD, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(RISCVVirtState), - .class_init =3D riscv_virt_board_class_init, -}; - static void riscv_virt_board_machine_init(MachineClass *mc) { mc->desc =3D "RISC-V VirtIO Board (Privileged ISA v1.10)"; @@ -406,10 +388,3 @@ static void riscv_virt_board_machine_init(MachineClass= *mc) } =20 DEFINE_MACHINE("virt", riscv_virt_board_machine_init) - -static void riscv_virt_board_register_types(void) -{ - type_register_static(&riscv_virt_board_device); -} - -type_init(riscv_virt_board_register_types); diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h index 0aebc57..12ad6d2 100644 --- a/include/hw/riscv/sifive_e.h +++ b/include/hw/riscv/sifive_e.h @@ -19,11 +19,6 @@ #ifndef HW_SIFIVE_E_H #define HW_SIFIVE_E_H =20 -#define TYPE_SIFIVE_E "riscv.sifive_e" - -#define SIFIVE_E(obj) \ - OBJECT_CHECK(SiFiveEState, (obj), TYPE_SIFIVE_E) - typedef struct SiFiveEState { /*< private >*/ SysBusDevice parent_obj; diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index be38aa0..94a3905 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -19,11 +19,6 @@ #ifndef HW_SIFIVE_U_H #define HW_SIFIVE_U_H =20 -#define TYPE_SIFIVE_U "riscv.sifive_u" - -#define SIFIVE_U(obj) \ - OBJECT_CHECK(SiFiveUState, (obj), TYPE_SIFIVE_U) - typedef struct SiFiveUState { /*< private >*/ SysBusDevice parent_obj; diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h index 179b6cf..8410430 100644 --- a/include/hw/riscv/spike.h +++ b/include/hw/riscv/spike.h @@ -19,10 +19,11 @@ #ifndef HW_SPIKE_H #define HW_SPIKE_H =20 -#define TYPE_RISCV_SPIKE_V1_09_1_BOARD "riscv.spike_v1_9_1" -#define TYPE_RISCV_SPIKE_V1_10_0_BOARD "riscv.spike_v1_10" - typedef struct { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ RISCVHartArrayState soc; void *fdt; int fdt_size; diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 655e85d..b91a412 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -19,10 +19,6 @@ #ifndef HW_VIRT_H #define HW_VIRT_H =20 -#define TYPE_RISCV_VIRT_BOARD "riscv.virt" -#define VIRT(obj) \ - OBJECT_CHECK(RISCVVirtState, (obj), TYPE_RISCV_VIRT_BOARD) - typedef struct { /*< private >*/ SysBusDevice parent_obj; @@ -45,7 +41,6 @@ enum { VIRT_DRAM }; =20 - enum { UART0_IRQ =3D 10, VIRTIO_IRQ =3D 1, /* 1 to 8 */ --=20 2.7.0 From nobody Mon May 20 15:50:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1520569530281535.175676883478; Thu, 8 Mar 2018 20:25:30 -0800 (PST) Received: from localhost ([::1]:43149 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eu9az-0004GI-AR for importer@patchew.org; Thu, 08 Mar 2018 23:25:29 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55698) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eu9QR-00044e-NA for qemu-devel@nongnu.org; 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X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PATCH v2 08/23] RISC-V: Make sure rom has space for fdt X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Michael Clark , Palmer Dabbelt , Sagar Karandikar Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Remove a potential buffer overflow (not seen in practice). Perhaps cpu_physical_memory_write already has bound checks. This change however makes space for the maximum device tree size and adds an explicit bounds check and error message. It doesn't trigger, but it may help in the future if the device-tree size is exceeded. e.g. large bootargs. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 20 ++++++++++++-------- hw/riscv/spike.c | 16 +++++++++++----- hw/riscv/virt.c | 13 +++++++++---- 3 files changed, 32 insertions(+), 17 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 083043a..57b4f4f 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -52,7 +52,7 @@ static const struct MemmapEntry { hwaddr size; } sifive_u_memmap[] =3D { [SIFIVE_U_DEBUG] =3D { 0x0, 0x100 }, - [SIFIVE_U_MROM] =3D { 0x1000, 0x2000 }, + [SIFIVE_U_MROM] =3D { 0x1000, 0x11000 }, [SIFIVE_U_CLINT] =3D { 0x2000000, 0x10000 }, [SIFIVE_U_PLIC] =3D { 0xc000000, 0x4000000 }, [SIFIVE_U_UART0] =3D { 0x10013000, 0x1000 }, @@ -221,7 +221,7 @@ static void riscv_sifive_u_init(MachineState *machine) const struct MemmapEntry *memmap =3D sifive_u_memmap; =20 SiFiveUState *s =3D g_new0(SiFiveUState, 1); - MemoryRegion *sys_memory =3D get_system_memory(); + MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); =20 @@ -239,7 +239,7 @@ static void riscv_sifive_u_init(MachineState *machine) /* register RAM */ memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram", machine->ram_size, &error_fatal); - memory_region_add_subregion(sys_memory, memmap[SIFIVE_U_DRAM].base, + memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base, main_mem); =20 /* create device tree */ @@ -247,9 +247,9 @@ static void riscv_sifive_u_init(MachineState *machine) =20 /* boot rom */ memory_region_init_ram(mask_rom, NULL, "riscv.sifive.u.mrom", - memmap[SIFIVE_U_MROM].base, &error_fatal); - memory_region_set_readonly(mask_rom, true); - memory_region_add_subregion(sys_memory, 0x0, mask_rom); + memmap[SIFIVE_U_MROM].size, &error_fatal); + memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base, + mask_rom); =20 if (machine->kernel_filename) { load_kernel(machine->kernel_filename); @@ -276,6 +276,10 @@ static void riscv_sifive_u_init(MachineState *machine) copy_le32_to_phys(memmap[SIFIVE_U_MROM].base, reset_vec, sizeof(reset_= vec)); =20 /* copy in the device tree */ + if (s->fdt_size >=3D memmap[SIFIVE_U_MROM].size - sizeof(reset_vec)) { + error_report("qemu: not enough space to store device-tree"); + exit(1); + } qemu_fdt_dumpdtb(s->fdt, s->fdt_size); cpu_physical_memory_write(memmap[SIFIVE_U_MROM].base + sizeof(reset_vec), s->fdt, s->fdt_size); @@ -293,9 +297,9 @@ static void riscv_sifive_u_init(MachineState *machine) SIFIVE_U_PLIC_CONTEXT_BASE, SIFIVE_U_PLIC_CONTEXT_STRIDE, memmap[SIFIVE_U_PLIC].size); - sifive_uart_create(sys_memory, memmap[SIFIVE_U_UART0].base, + sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base, serial_hds[0], SIFIVE_PLIC(s->plic)->irqs[SIFIVE_U_UART0_IRQ]); - /* sifive_uart_create(sys_memory, memmap[SIFIVE_U_UART1].base, + /* sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base, serial_hds[1], SIFIVE_PLIC(s->plic)->irqs[SIFIVE_U_UART1_IRQ]); */ sifive_clint_create(memmap[SIFIVE_U_CLINT].base, memmap[SIFIVE_U_CLINT].size, smp_cpus, diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 64e585e..c7d937b 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -46,7 +46,7 @@ static const struct MemmapEntry { hwaddr base; hwaddr size; } spike_memmap[] =3D { - [SPIKE_MROM] =3D { 0x1000, 0x2000 }, + [SPIKE_MROM] =3D { 0x1000, 0x11000 }, [SPIKE_CLINT] =3D { 0x2000000, 0x10000 }, [SPIKE_DRAM] =3D { 0x80000000, 0x0 }, }; @@ -197,8 +197,9 @@ static void spike_v1_10_0_board_init(MachineState *mach= ine) =20 /* boot rom */ memory_region_init_ram(mask_rom, NULL, "riscv.spike.mrom", - s->fdt_size + 0x2000, &error_fatal); - memory_region_add_subregion(system_memory, 0x0, mask_rom); + memmap[SPIKE_MROM].size, &error_fatal); + memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base, + mask_rom); =20 if (machine->kernel_filename) { load_kernel(machine->kernel_filename); @@ -225,6 +226,10 @@ static void spike_v1_10_0_board_init(MachineState *mac= hine) copy_le32_to_phys(memmap[SPIKE_MROM].base, reset_vec, sizeof(reset_vec= )); =20 /* copy in the device tree */ + if (s->fdt_size >=3D memmap[SPIKE_MROM].size - sizeof(reset_vec)) { + error_report("qemu: not enough space to store device-tree"); + exit(1); + } qemu_fdt_dumpdtb(s->fdt, s->fdt_size); cpu_physical_memory_write(memmap[SPIKE_MROM].base + sizeof(reset_vec), s->fdt, s->fdt_size); @@ -266,8 +271,9 @@ static void spike_v1_09_1_board_init(MachineState *mach= ine) =20 /* boot rom */ memory_region_init_ram(mask_rom, NULL, "riscv.spike.mrom", - 0x40000, &error_fatal); - memory_region_add_subregion(system_memory, 0x0, mask_rom); + memmap[SPIKE_MROM].size, &error_fatal); + memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base, + mask_rom); =20 if (machine->kernel_filename) { load_kernel(machine->kernel_filename); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 5913100..d680cbd 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -45,8 +45,8 @@ static const struct MemmapEntry { hwaddr size; } virt_memmap[] =3D { [VIRT_DEBUG] =3D { 0x0, 0x100 }, - [VIRT_MROM] =3D { 0x1000, 0x2000 }, - [VIRT_TEST] =3D { 0x4000, 0x1000 }, + [VIRT_MROM] =3D { 0x1000, 0x11000 }, + [VIRT_TEST] =3D { 0x100000, 0x1000 }, [VIRT_CLINT] =3D { 0x2000000, 0x10000 }, [VIRT_PLIC] =3D { 0xc000000, 0x4000000 }, [VIRT_UART0] =3D { 0x10000000, 0x100 }, @@ -297,8 +297,9 @@ static void riscv_virt_board_init(MachineState *machine) =20 /* boot rom */ memory_region_init_ram(mask_rom, NULL, "riscv_virt_board.mrom", - s->fdt_size + 0x2000, &error_fatal); - memory_region_add_subregion(system_memory, 0x0, mask_rom); + memmap[VIRT_MROM].size, &error_fatal); + memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, + mask_rom); =20 if (machine->kernel_filename) { uint64_t kernel_entry =3D load_kernel(machine->kernel_filename); @@ -336,6 +337,10 @@ static void riscv_virt_board_init(MachineState *machin= e) copy_le32_to_phys(memmap[VIRT_MROM].base, reset_vec, sizeof(reset_vec)= ); =20 /* copy in the device tree */ + if (s->fdt_size >=3D memmap[VIRT_MROM].size - sizeof(reset_vec)) { + error_report("qemu: not enough space to store device-tree"); + exit(1); + } qemu_fdt_dumpdtb(s->fdt, s->fdt_size); cpu_physical_memory_write(memmap[VIRT_MROM].base + sizeof(reset_vec), s->fdt, s->fdt_size); --=20 2.7.0 From nobody Mon May 20 15:50:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[125.237.39.90]) by smtp.gmail.com with ESMTPSA id h15sm334141pfi.56.2018.03.08.20.14.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 08 Mar 2018 20:14:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7CfZNEeH8cK/kvjsiUVLVgvJ07eCOI0ZWWcN6NTeFP4=; b=Rt+5EDskjhlvX3XLPo5a7vXgNZHhmZAu5XzRT1pZgakSVrPoWep0g7YZO4mz2BjLCw QERha/3R+yYWevQ6ISlSwWwWm5eyaY1D2nZk2gV9PbIYHWiD7kYljcv3JoqKo3NotX3Z pdGHwo/c5zUL0M4Ww/DScmgRvvd42ZgYHbc0vpbXbE+kfhltK1pTMEuCkTf6jQytWtny 59yig96e8dWTn9dYl/5O/43mMzBJMM2UwYmdfWaR5VagBI/OAeQRw7KuLz7TTKsnPZhT z6q3okPBExlDUhz1/5RZ7FN43x58ZmcI8tMiDAGbFl5xyI6lMfA0jeDhjL2tMtdRsIPe dDfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7CfZNEeH8cK/kvjsiUVLVgvJ07eCOI0ZWWcN6NTeFP4=; b=ZR5P1J2apAeG1jh51vadv4Z9Pcy433rs9Cw2sHd/vSSm51/CTiv3nC+5f3xmeGL8NW MOY47oaS6rm4sV/1xVqljT/SAyw89pR7DslWhY5/BjUeqldW1iTRYfp+3kqRQadZPgFT PC0yGR4As1JdoQJ0TmrSVL80kjhJD2+qKe6envdbLHgIF1WX4KHj9mmi9AiVRqtOthnj ttqlhrhnViNok5zda9cz/dP2PkanapJK4HIk9/0IrH8XH3uVcHljO98oSmLz0Nf+zvk2 rRRWhU/8mOQzkcqIPQR8ojkc1XAWNKxeqGpQ7+P//Jax8x0eejTJqAhIhxHq6qGujkmU z+dw== X-Gm-Message-State: AElRT7EcEWdBplN/HP0y8gQ0tB9Gy1WGH9jrF89InqTQAlNFsNO6InJb 3F00bHJhY7qivpYefH5CesNdJyoW5Ks= X-Google-Smtp-Source: AG47ELsMOUgxQEySvGhGqi6iB1Rlp6euKpuz+GuxUYErjJ0z6YMfqkNEsqNMrkB09dXaHJ+mlCvWtA== X-Received: by 2002:a17:902:8341:: with SMTP id z1-v6mr2875219pln.386.1520568876108; Thu, 08 Mar 2018 20:14:36 -0800 (PST) From: Michael Clark To: qemu-devel@nongnu.org Date: Fri, 9 Mar 2018 17:12:31 +1300 Message-Id: <1520568765-58189-10-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1520568765-58189-1-git-send-email-mjc@sifive.com> References: <1520568765-58189-1-git-send-email-mjc@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PATCH v2 09/23] RISC-V: Include intruction hex in disassembly X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Michael Clark , Palmer Dabbelt , Sagar Karandikar Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 This was added to help debug issues using -d in_asm. It is useful to see the instruction bytes, as one can detect if one is trying to execute ASCII or device-tree magic. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- disas/riscv.c | 39 ++++++++++++++++++++------------------- 1 file changed, 20 insertions(+), 19 deletions(-) diff --git a/disas/riscv.c b/disas/riscv.c index 3c17501..4580308 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -2769,25 +2769,6 @@ static void format_inst(char *buf, size_t buflen, si= ze_t tab, rv_decode *dec) char tmp[64]; const char *fmt; =20 - if (dec->op =3D=3D rv_op_illegal) { - size_t len =3D inst_length(dec->inst); - switch (len) { - case 2: - snprintf(buf, buflen, "(0x%04" PRIx64 ")", dec->inst); - break; - case 4: - snprintf(buf, buflen, "(0x%08" PRIx64 ")", dec->inst); - break; - case 6: - snprintf(buf, buflen, "(0x%012" PRIx64 ")", dec->inst); - break; - default: - snprintf(buf, buflen, "(0x%016" PRIx64 ")", dec->inst); - break; - } - return; - } - fmt =3D opcode_data[dec->op].format; while (*fmt) { switch (*fmt) { @@ -3004,6 +2985,11 @@ disasm_inst(char *buf, size_t buflen, rv_isa isa, ui= nt64_t pc, rv_inst inst) format_inst(buf, buflen, 16, &dec); } =20 +#define INST_FMT_2 "%04" PRIx64 " " +#define INST_FMT_4 "%08" PRIx64 " " +#define INST_FMT_6 "%012" PRIx64 " " +#define INST_FMT_8 "%016" PRIx64 " " + static int print_insn_riscv(bfd_vma memaddr, struct disassemble_info *info, rv_isa is= a) { @@ -3031,6 +3017,21 @@ print_insn_riscv(bfd_vma memaddr, struct disassemble= _info *info, rv_isa isa) } } =20 + switch (len) { + case 2: + (*info->fprintf_func)(info->stream, INST_FMT_2, inst); + break; + case 4: + (*info->fprintf_func)(info->stream, INST_FMT_4, inst); + break; + case 6: + (*info->fprintf_func)(info->stream, INST_FMT_6, inst); + break; + default: + (*info->fprintf_func)(info->stream, INST_FMT_8, inst); + break; + } + disasm_inst(buf, sizeof(buf), isa, memaddr, inst); (*info->fprintf_func)(info->stream, "%s", buf); =20 --=20 2.7.0 From nobody Mon May 20 15:50:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1520569368797999.887377124955; Thu, 8 Mar 2018 20:22:48 -0800 (PST) Received: from localhost ([::1]:43133 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eu9YC-0001e2-3t for importer@patchew.org; Thu, 08 Mar 2018 23:22:36 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55729) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eu9QX-0004AP-9b for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:14:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eu9QW-0006xq-Gf for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:14:41 -0500 Received: from mail-pg0-x241.google.com ([2607:f8b0:400e:c05::241]:46603) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eu9QW-0006xZ-9g for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:14:40 -0500 Received: by mail-pg0-x241.google.com with SMTP id r26so3113105pgv.13 for ; Thu, 08 Mar 2018 20:14:40 -0800 (PST) Received: from localhost.localdomain (125-237-39-90-fibre.bb.spark.co.nz. [125.237.39.90]) by smtp.gmail.com with ESMTPSA id h15sm334141pfi.56.2018.03.08.20.14.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 08 Mar 2018 20:14:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=aeKs7SuxlwsYHH8r29GkHugNz0c5+GrzvILr3D7owPA=; b=L0uXKDkyM9IBLX7/LJ6FgKRo60TwhYfdXjAQgOjXJarAbXvDch32MDQSBzsX5i8SpF uJpBEEII1+oKGlumtf7ZdvwNiOgBp3MWpGZ/aW1tSY0j9BSRnpIgZorg6T+jTQ/sdLwi yyYmuKZvsPaEL3EkTSY+Yqr/f9yi1/LL42s4xXRcMqOnZBfkod9WeTuQG8JOrdodkUAC +CkB8oyZQ0RxaZBGzWj6Mo1bk/0lpPc33y/Pxail35yebke4JQO12nSIK7YGyPjrEOYU gDhjHfriHWgr8lAAdAY4m7wSwImtyTyq8bwoHXNz6iiSpbqgXQnHZclhzed+7hbq9yiN 3pAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aeKs7SuxlwsYHH8r29GkHugNz0c5+GrzvILr3D7owPA=; b=GdwIWA3hg1f68LacrNtbb1wJS0+MtUFSIwMJ0vsqJ78tbQxrnGjcgcuKRnT6eIn+Wm elBFNL0hYZkrysphHUJTO1DUk7ttmZc6EQ0Ir+LLk2ZTdc9gLzIM/cKjcqFzC2syw6Zb JQJhT8K7wOTY0Q0P1VQ6/JKgiZH/7fsAlGtOM/Waax9+o2dUIsM+/V2Qo7TY3jkDhZ03 H2dvHFH9X3f89/m5KUTH9Lcv+GjT8dS4oKEV8N5AXJv1RdaiPDnTVqAp1Lkhs3Zn1xO+ jMz+XoOkOCvsYalyDNzP64Ylz8IbYztvxC/ZH99B02ijiaTzdZJ8gpX5XXtawwEUkRWf F1eg== X-Gm-Message-State: APf1xPAEjDhykBpKWjDnCa5Ii6zBvfAikJs3ssjlY3K6mnEpawN28mMV mRT2kYfk2scNWWCB9+A+GJbFsvourR8= X-Google-Smtp-Source: AG47ELs95cepB59D8VVgpzX7nLp0oRIAesVxcrPbE1rBUebz8fUrd9PTNv5WIcqSzF8PgFFnxWLjyA== X-Received: by 10.99.146.26 with SMTP id o26mr23206641pgd.309.1520568879378; Thu, 08 Mar 2018 20:14:39 -0800 (PST) From: Michael Clark To: qemu-devel@nongnu.org Date: Fri, 9 Mar 2018 17:12:32 +1300 Message-Id: <1520568765-58189-11-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1520568765-58189-1-git-send-email-mjc@sifive.com> References: <1520568765-58189-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH v2 10/23] RISC-V: Hold rcu_read_lock when accessing memory X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stefan O'Rear , Bastian Koppelmann , Michael Clark , Palmer Dabbelt , Sagar Karandikar Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From reading other code that accesses memory regions directly, it appears that the rcu_read_lock needs to be held. Note: the original code for accessing RAM directly was added because there is no other way to use atomic_cmpxchg on guest physical address space. Cc: Sagar Karandikar Cc: Bastian Koppelmann CC: Stefan O'Rear Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt --- target/riscv/helper.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/riscv/helper.c b/target/riscv/helper.c index 02cbcea..228933c 100644 --- a/target/riscv/helper.c +++ b/target/riscv/helper.c @@ -209,6 +209,7 @@ restart: as the PTE is no longer valid */ MemoryRegion *mr; hwaddr l =3D sizeof(target_ulong), addr1; + rcu_read_lock(); mr =3D address_space_translate(cs->as, pte_addr, &addr1, &l, false); if (memory_access_is_direct(mr, true)) { @@ -222,16 +223,19 @@ restart: target_ulong old_pte =3D atomic_cmpxchg(pte_pa, pte, updated_pte); if (old_pte !=3D pte) { + rcu_read_unlock(); goto restart; } else { pte =3D updated_pte; } #endif } else { + rcu_read_unlock(); /* misconfigured PTE in ROM (AD bits are not preset) or * PTE is in IO space and can't be updated atomically = */ return TRANSLATE_FAIL; } + rcu_read_unlock(); } =20 /* for superpage mappings, make a fake leaf PTE for the TLB's --=20 2.7.0 From nobody Mon May 20 15:50:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 152056952813976.67743407700823; Thu, 8 Mar 2018 20:25:28 -0800 (PST) Received: from localhost ([::1]:43148 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eu9ax-0004EY-7s for importer@patchew.org; Thu, 08 Mar 2018 23:25:27 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55742) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eu9Qa-0004BN-RE for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:14:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eu9QZ-0006yz-JR for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:14:44 -0500 Received: from mail-pl0-x242.google.com ([2607:f8b0:400e:c01::242]:46549) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eu9QZ-0006yj-B7 for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:14:43 -0500 Received: by mail-pl0-x242.google.com with SMTP id y8-v6so4587761pll.13 for ; Thu, 08 Mar 2018 20:14:43 -0800 (PST) Received: from localhost.localdomain (125-237-39-90-fibre.bb.spark.co.nz. [125.237.39.90]) by smtp.gmail.com with ESMTPSA id h15sm334141pfi.56.2018.03.08.20.14.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 08 Mar 2018 20:14:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=QkuuEv+D1Gy9OGIERK4NAdR5HD7g3kWvPngTihs5qC8=; b=PExOX2tfhTQ/aXKvFjauQ6p4mLwqIzOHSUo+jSvFhA9j7xPJz2qpjCdDz6Sf3fdVo3 Mnyjlhlm9FpUGDggLNoXkKbJuatsuQ70tAwEIklg1gu7OnvgCLgzfAmpHEpaCYNeRIXd cYo4q7izP0kG9B4Uk6JPD2Q+7yIkckLTAqgSjfTQdPd/saeZHghbgpgGAiYslifPPEQD GUFaatD+aqyq5qMS81Vlr50bSSx6klTlZ0wHgQ3/AhKP0b3+PXCaBgiWmaQS/3pXDNwt oHkmo8/6pM27sejtIZp7bXzg7P78N9XEQkkgxwVV2nI0YsJ4CrWwqUcel/0IPAOyVS8i e6kg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=QkuuEv+D1Gy9OGIERK4NAdR5HD7g3kWvPngTihs5qC8=; b=tXUcz+Zpk6cgFXxQdStoYT/OZ/OOXmtkrKpgKEiPLHncF8cnIncWpbdGswib2U8PW0 Yq+6efmH2C94+hi74QMW81T9r9UpAxI9JEwNwFWs62h8S3sb4M1GZp4DlJv+R/oG4hxD suCWzYmJ4yZpWhOwwglBNgo6ahB7hmh2sGj+8SR+eMr6pUl47e5/Vl99V/XJshyn28Ql 5tmkxYWmaB857sL46OoGqz1yCropFJ5qbB8epSTq+/VMIQirtUEDqIgVnHPoItgVkeVn d6LkwRkDpB/lt5cc6SrZJnLmnoqwkDZK/ONNEpCdc45Z7S+6EyTxGTCyk0o/BKEuz7NL aiCQ== X-Gm-Message-State: APf1xPCK8gVxCcJeeUWHbnt9deJqhWDqmiN9qiaeHe3Y6XDIuuIoT33G yPWR0t9WOLUSsYKHie+o0P8pZul697w= X-Google-Smtp-Source: AG47ELvWnQV5fhibNikpRXFpHvt6wU8JGpWR+MwccXrkUCPw2WrJeMhaPcJgGhi7Md2pLfmq8UXzRg== X-Received: by 2002:a17:902:7686:: with SMTP id m6-v6mr26718892pll.199.1520568882343; Thu, 08 Mar 2018 20:14:42 -0800 (PST) From: Michael Clark To: qemu-devel@nongnu.org Date: Fri, 9 Mar 2018 17:12:33 +1300 Message-Id: <1520568765-58189-12-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1520568765-58189-1-git-send-email-mjc@sifive.com> References: <1520568765-58189-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH v2 11/23] RISC-V: Improve page table walker spec compliance X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Michael Clark , Palmer Dabbelt , Sagar Karandikar Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" - Inline PTE_TABLE check for better readability - Improve readibility of User page U mode and SUM test - Disallow non U mode from fetching from User pages - Add reserved PTE flag check: W or W|X - Add misaligned PPN check - Change access checks from ternary operator to if statements - Improves page walker comments - No measurable performance impact on dd test Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt --- target/riscv/cpu_bits.h | 2 -- target/riscv/helper.c | 59 ++++++++++++++++++++++++++++++++++-----------= ---- 2 files changed, 41 insertions(+), 20 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 64aa097..12b4757 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -407,5 +407,3 @@ #define PTE_SOFT 0x300 /* Reserved for Software */ =20 #define PTE_PPN_SHIFT 10 - -#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) =3D=3D P= TE_V) diff --git a/target/riscv/helper.c b/target/riscv/helper.c index 228933c..162d5ec 100644 --- a/target/riscv/helper.c +++ b/target/riscv/helper.c @@ -185,16 +185,36 @@ restart: #endif target_ulong ppn =3D pte >> PTE_PPN_SHIFT; =20 - if (PTE_TABLE(pte)) { /* next level of page table */ + if (!(pte & PTE_V)) { + /* Invalid PTE */ + return TRANSLATE_FAIL; + } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { + /* Inner PTE, continue walking */ base =3D ppn << PGSHIFT; - } else if ((pte & PTE_U) ? (mode =3D=3D PRV_S) && !sum : !(mode = =3D=3D PRV_S)) { - break; - } else if (!(pte & PTE_V) || (!(pte & PTE_R) && (pte & PTE_W))) { - break; - } else if (access_type =3D=3D MMU_INST_FETCH ? !(pte & PTE_X) : - access_type =3D=3D MMU_DATA_LOAD ? !(pte & PTE_R) && - !(mxr && (pte & PTE_X)) : !((pte & PTE_R) && (pte & PTE_= W))) { - break; + } else if ((pte & (PTE_R | PTE_W | PTE_X)) =3D=3D PTE_W) { + /* Reserved leaf PTE flags: PTE_W */ + return TRANSLATE_FAIL; + } else if ((pte & (PTE_R | PTE_W | PTE_X)) =3D=3D (PTE_W | PTE_X))= { + /* Reserved leaf PTE flags: PTE_W + PTE_X */ + return TRANSLATE_FAIL; + } else if ((pte & PTE_U) && ((mode !=3D PRV_U) && + (!sum || access_type =3D=3D MMU_INST_FETCH))) { + /* User PTE flags when not U mode and mstatus.SUM is not set, + or the access type is an instruction fetch */ + return TRANSLATE_FAIL; + } else if (ppn & ((1ULL << ptshift) - 1)) { + /* Misasligned PPN */ + return TRANSLATE_FAIL; + } else if (access_type =3D=3D MMU_DATA_LOAD && !((pte & PTE_R) || + (mode !=3D PRV_U && (pte & PTE_X) && mxr))) { + /* Read access check failed */ + return TRANSLATE_FAIL; + } else if (access_type =3D=3D MMU_DATA_STORE && !(pte & PTE_W)) { + /* Write access check failed */ + return TRANSLATE_FAIL; + } else if (access_type =3D=3D MMU_INST_FETCH && !(pte & PTE_X)) { + /* Fetch access check failed */ + return TRANSLATE_FAIL; } else { /* if necessary, set accessed and dirty bits. */ target_ulong updated_pte =3D pte | PTE_A | @@ -202,11 +222,14 @@ restart: =20 /* Page table updates need to be atomic with MTTCG enabled */ if (updated_pte !=3D pte) { - /* if accessed or dirty bits need updating, and the PTE is - * in RAM, then we do so atomically with a compare and swa= p. - * if the PTE is in IO space, then it can't be updated. - * if the PTE changed, then we must re-walk the page table - as the PTE is no longer valid */ + /* + * - if accessed or dirty bits need updating, and the PTE = is + * in RAM, then we do so atomically with a compare and s= wap. + * - if the PTE is in IO space or ROM, then it can't be up= dated + * and we return TRANSLATE_FAIL. + * - if the PTE changed by the time we went to update it, = then + * it is no longer valid and we must re-walk the page ta= ble. + */ MemoryRegion *mr; hwaddr l =3D sizeof(target_ulong), addr1; rcu_read_lock(); @@ -243,15 +266,15 @@ restart: target_ulong vpn =3D addr >> PGSHIFT; *physical =3D (ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT; =20 - if ((pte & PTE_R)) { + /* set permissions on the TLB entry */ + if ((pte & PTE_R) || (mode !=3D PRV_U && (pte & PTE_X) && mxr)= ) { *prot |=3D PAGE_READ; } if ((pte & PTE_X)) { *prot |=3D PAGE_EXEC; } - /* only add write permission on stores or if the page - is already dirty, so that we don't miss further - page table walks to update the dirty bit */ + /* add write permission on stores or if the page is already di= rty, + so that we TLB miss on later writes to update the dirty bit= */ if ((pte & PTE_W) && (access_type =3D=3D MMU_DATA_STORE || (pte & PTE_D))) { *prot |=3D PAGE_WRITE; --=20 2.7.0 From nobody Mon May 20 15:50:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1520569206298123.7050596761552; Thu, 8 Mar 2018 20:20:06 -0800 (PST) Received: from localhost ([::1]:43117 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eu9Vl-0007tO-EL for importer@patchew.org; Thu, 08 Mar 2018 23:20:05 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55763) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eu9Qf-0004IY-Q5 for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:14:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eu9Qc-0006zy-Ki for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:14:49 -0500 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:34297) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eu9Qc-0006zd-El for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:14:46 -0500 Received: by mail-pg0-x244.google.com with SMTP id m19so3123710pgn.1 for ; Thu, 08 Mar 2018 20:14:46 -0800 (PST) Received: from localhost.localdomain (125-237-39-90-fibre.bb.spark.co.nz. [125.237.39.90]) by smtp.gmail.com with ESMTPSA id h15sm334141pfi.56.2018.03.08.20.14.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 08 Mar 2018 20:14:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=j4IsCu0Ogw4C4VGML3xebQtkhhgEZnHvVT7BhbcJNGc=; b=R76frV+4S5WS+xM/vqgqXOJ+3m+7W1Gi2u035Xce0Lx8sCssux2oN6DQGivSStreeu 0mTKl+pVNIM6MbP0OCGWOCBe4ItRqDIjHd4yBzRh2L81lAKvrtx290tDjMvFj5KJHnlA IPuLSbJA6z2iPp85ORqcEEQFNVzhixuxtOVbxY9wL0AHzEeOIvw1Hz1H9rfMwaYskZDF b02Df9gK+OBVcG+ZhQR6WwHt4SZeN5xcafBs8JZaFBKOReKCW7vhW2szVmpk+dJujtdB CDH6bqnRl+rVvo7NXxg+NUtwOQ37WBnc68Nrb19XwoKdpuNScXg2gpkj2mSsjgkPlbPo v8DA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=j4IsCu0Ogw4C4VGML3xebQtkhhgEZnHvVT7BhbcJNGc=; b=fEYr00c/jk0dNQCkD2gHeFStj8Tne6TQZIYZyPBBMhMTAvMSt+rq4OcvgcbHewf7lt kHXMHcvfojzKfhomKZr+v142t14Ngg19JQSwiyUL4HhF2eln+1mJyRt2Bx66Kbpe9ynq FPG7eKHH4sX4HCjsynlTTT1tnD69/IoK8xT9ufLwNrJWQ7bG8sTT/blY7vhnLrVV4rUj d93gMe/5VSOdW3txjD4gcJjr+vNsYkJJ2iFicQgd2bqBcqINPNoMDnaQpn6AQpd7CCDp VuUTsXiHIO0vjfPyhLxy+WF/Pz+f+OX6l5RSHziXyZSnL+UohLQWQWw6+Qd7D1kj6Tkq i9Gw== X-Gm-Message-State: APf1xPAOaJKXqqFLdbSCCkKbSsnWwTxYNRX3ugh54XFKNstt8rtf9mWX IcXqH2dZq4ECWR26lPg2YafhRYzx578= X-Google-Smtp-Source: AG47ELtVKW5kJXUEXij4vV4ffQY5Ux9epJo+O8+xDE2jhLXln4Mg37s89lhypa+CvIIAjOPlzcG/zw== X-Received: by 10.99.1.148 with SMTP id 142mr23688379pgb.24.1520568885558; Thu, 08 Mar 2018 20:14:45 -0800 (PST) From: Michael Clark To: qemu-devel@nongnu.org Date: Fri, 9 Mar 2018 17:12:34 +1300 Message-Id: <1520568765-58189-13-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1520568765-58189-1-git-send-email-mjc@sifive.com> References: <1520568765-58189-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH v2 12/23] RISC-V: Update E order and I extension order X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Michael Clark , Palmer Dabbelt , Sagar Karandikar Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Section 22.8 Subset Naming Convention of the RISC-V ISA Specification defines the canonical order for extensions in the ISA string. It is silent on the position of the E extension however E is a substitute for I so it must come early in the extension list order. A comment is added to state E and I are mutually exclusive, as the E extension will be added to the RISC-V port in the future. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4851890..d2ae56a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -26,7 +26,7 @@ =20 /* RISC-V CPU definitions */ =20 -static const char riscv_exts[26] =3D "IMAFDQECLBJTPVNSUHKORWXYZG"; +static const char riscv_exts[26] =3D "IEMAFDQCLBJTPVNSUHKORWXYZG"; =20 const char * const riscv_int_regnames[] =3D { "zero", "ra ", "sp ", "gp ", "tp ", "t0 ", "t1 ", "t2 ", diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index cff02a2..3a0ca2f 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -71,6 +71,7 @@ #define RV(x) ((target_ulong)1 << (x - 'A')) =20 #define RVI RV('I') +#define RVE RV('E') /* E and I are mutually exclusive */ #define RVM RV('M') #define RVA RV('A') #define RVF RV('F') --=20 2.7.0 From nobody Mon May 20 15:50:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15205693772161021.1425386600772; Thu, 8 Mar 2018 20:22:57 -0800 (PST) Received: from localhost ([::1]:43136 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eu9YW-0001ur-9B for importer@patchew.org; Thu, 08 Mar 2018 23:22:56 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55774) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eu9Qg-0004JR-Ov for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:14:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eu9Qf-00072E-Ly for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:14:50 -0500 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:36880) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eu9Qf-00071q-G4 for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:14:49 -0500 Received: by mail-pg0-x244.google.com with SMTP id y26so3124872pgv.4 for ; Thu, 08 Mar 2018 20:14:49 -0800 (PST) Received: from localhost.localdomain (125-237-39-90-fibre.bb.spark.co.nz. [125.237.39.90]) by smtp.gmail.com with ESMTPSA id h15sm334141pfi.56.2018.03.08.20.14.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 08 Mar 2018 20:14:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=s+Y8QO1OIXfG/QRzhargblNkvjI0pxBr4ksUffkutj0=; b=J9S9QcMswG7IeKUD72jRPNggKzS4HHXVf4d48hMHk3XeioS0j0K3K//y35+uyk4wyg ToAoVy1GE/mmcokZIGzOskCdh75STa/ZIaLaMhpz2awWojUyhreYXu4/+LhwUzIRsJ6Q Ukxe95K3H0TTC4TZtt4HwO7dgUxksfkD4hzdzfMGhMpZ01QfF193mEM3twrzRqPFN83Q KkPeugJT8rHgz3gG3wDp+Yc+kP9vbJAvR91IQ6pbaYMzrcPlgBDE/n4LVjczc76qZZD8 KwPOBEmuD5og3VzWSD9U2CP1/FS63WkbeTBUV+uT9adeR1Ab+xVpQqLFJXhbvhKewsW1 hPrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=s+Y8QO1OIXfG/QRzhargblNkvjI0pxBr4ksUffkutj0=; b=KHlX0qgApYwkiMplw8EAAa53Dhznw4YizVXf1Uzffq3UeJI8ZwyKpXqWK97tkOeKKB M9LM4un6OcaYpfgozXwAzHm4rSpPCoPCo+GCwp4uQGnpldLW4kZJJAUpCylUstK7RKiF B/kXdxYiUDfykAO43wEBnNpd6zsVC+dxOofEzC/GD6k39csr6gba5pSg4sRBjOacU45B cXfKBeIIoLv50PddFcXWCVw4mW8Lmqplngn3BMwwHMz7kXyqv4DWksvdk7H4ay/XqBtE KykJYyY34sb5yysYQUY18NpnWxWMoE4hvq0yW5E4lwCUhnSkkov5jTMrswHDT3y8r8RI 56fQ== X-Gm-Message-State: AElRT7H0kP06FeBIA6YaWrhPtwPDG01zzSeZINpOWLIhfq1IJOegtY0G LHGYa7ZYTHwK7ZZmu+E2MpftPQ2o/s4= X-Google-Smtp-Source: AG47ELtWnh7o/YSpmBxB+HmLxEHyksY3u4tj4lmM8fpI4EJV2yXLAj2WrEZaYg0U6b/T5uh//xRGwg== X-Received: by 10.98.48.195 with SMTP id w186mr20619350pfw.174.1520568888597; Thu, 08 Mar 2018 20:14:48 -0800 (PST) From: Michael Clark To: qemu-devel@nongnu.org Date: Fri, 9 Mar 2018 17:12:35 +1300 Message-Id: <1520568765-58189-14-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1520568765-58189-1-git-send-email-mjc@sifive.com> References: <1520568765-58189-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH v2 13/23] RISC-V: Make some header guards more specific X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Michael Clark , Palmer Dabbelt , Sagar Karandikar Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/riscv/spike.h | 4 ++-- include/hw/riscv/virt.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h index 8410430..641b70d 100644 --- a/include/hw/riscv/spike.h +++ b/include/hw/riscv/spike.h @@ -16,8 +16,8 @@ * this program. If not, see . */ =20 -#ifndef HW_SPIKE_H -#define HW_SPIKE_H +#ifndef HW_RISCV_SPIKE_H +#define HW_RISCV_SPIKE_H =20 typedef struct { /*< private >*/ diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index b91a412..3a4f23e 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -16,8 +16,8 @@ * this program. If not, see . */ =20 -#ifndef HW_VIRT_H -#define HW_VIRT_H +#ifndef HW_RISCV_VIRT_H +#define HW_RISCV_VIRT_H =20 typedef struct { /*< private >*/ --=20 2.7.0 From nobody Mon May 20 15:50:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 15205696774321010.0555507033009; Thu, 8 Mar 2018 20:27:57 -0800 (PST) Received: from localhost ([::1]:43165 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eu9dE-0006Ub-En for importer@patchew.org; Thu, 08 Mar 2018 23:27:48 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55793) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eu9Qj-0004Kj-AR for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:14:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eu9Qi-00073X-Ir for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:14:53 -0500 Received: from mail-pg0-x243.google.com ([2607:f8b0:400e:c05::243]:46605) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eu9Qi-00073B-C8 for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:14:52 -0500 Received: by mail-pg0-x243.google.com with SMTP id r26so3113283pgv.13 for ; Thu, 08 Mar 2018 20:14:52 -0800 (PST) Received: from localhost.localdomain (125-237-39-90-fibre.bb.spark.co.nz. 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X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH v2 14/23] RISC-V: Make virt header comment title consistent X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Michael Clark , Palmer Dabbelt , Sagar Karandikar Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/riscv/virt.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 3a4f23e..91163d6 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -1,5 +1,5 @@ /* - * SiFive VirtIO Board + * QEMU RISC-V VirtIO machine interface * * Copyright (c) 2017 SiFive, Inc. * --=20 2.7.0 From nobody Mon May 20 15:50:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15205698483661020.8024691367681; Thu, 8 Mar 2018 20:30:48 -0800 (PST) Received: from localhost ([::1]:43182 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eu9g7-0000jD-Km for importer@patchew.org; Thu, 08 Mar 2018 23:30:47 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55850) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eu9Qq-0004QO-17 for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:15:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eu9Ql-00074U-F2 for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:15:00 -0500 Received: from mail-pl0-x242.google.com ([2607:f8b0:400e:c01::242]:44593) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eu9Ql-00074C-8k for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:14:55 -0500 Received: by mail-pl0-x242.google.com with SMTP id 9-v6so4604762ple.11 for ; Thu, 08 Mar 2018 20:14:55 -0800 (PST) Received: from localhost.localdomain (125-237-39-90-fibre.bb.spark.co.nz. [125.237.39.90]) by smtp.gmail.com with ESMTPSA id h15sm334141pfi.56.2018.03.08.20.14.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 08 Mar 2018 20:14:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=eHR2h5f0Q0YrN/kZlLZAy2G3Z/Q1Fs0I02rf8Dyey58=; b=cl8b396o1FQk2ua5TyFa1HjPTXBFNa0b59Bwcgbn19mZE2942wH4UCk+XEPaUjmPhB oNlk9NHeGCo4au0nkft6ffu3mSWe1iKXl5/RCRBn9MlnkT82flsVPSBhFjkR7TwvZAoc JRluEaQNN3+MWB5h55NjEp1i4oWAf8GsV2cF6k8fiybPZM3mmphy4Hl0B01XxgPA+jci 0u4bf64wAICMXlqfccKNMp/XfRVQWEXqUP6Fo/QUQknZluNL/e2/GdqExxayzwId086y D3TDTcOLTl76vNtvOxCxX4HiYm7BNSbrgPbFRzjYbtfMh2keGgwHx8J7RQEuXwAT2dvu PKQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=eHR2h5f0Q0YrN/kZlLZAy2G3Z/Q1Fs0I02rf8Dyey58=; b=f8xua6tYeO0mTql0QIJblgmC7uqIKH3BYwJ5+JWBabVzz71ILBxzsWlXq2xNahVR5i CNPA1KXWxjI33mhLDxBa0hUxS+ID2iGx8CvkunUlkVGW6+XDe3bJmFPhHELdQSbrty17 nAOicI0d1PgVxDP9XTmPw5cQOaoUZTchA2gRfTKiBb4Twp4JLqbzkaS0OMjMhZwPhwnR BAtgmjH5nNdyXocKoOiVjdsUbJ14hlmT1cUghiTCNLeoD1ZAgcyWpcniMHibQF6NsE3k Wg/ThD/GWYl7QZQTa+okGsSyMVUHhIrjK5Gj46+/LUpEdLywq+ZaCZzFmW2c1mjv5+D7 hfQA== X-Gm-Message-State: APf1xPA8DgtLwc+V0OkKNVox5NiW8J1pUKJ1msiKCYmtTljMQ/iEqSrl V/c+2/R1D7Pfvk98kiOXv5HaqXjbBjY= X-Google-Smtp-Source: AG47ELs7gCB3iQs5FKSF/Ig/ATjsOqQAMR88PvIBGuIhphAH+ZBC4a5w+odA+fsvlS6ZeCAh7l7U2w== X-Received: by 2002:a17:902:6b82:: with SMTP id p2-v6mr26323637plk.326.1520568894423; Thu, 08 Mar 2018 20:14:54 -0800 (PST) From: Michael Clark To: qemu-devel@nongnu.org Date: Fri, 9 Mar 2018 17:12:37 +1300 Message-Id: <1520568765-58189-16-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1520568765-58189-1-git-send-email-mjc@sifive.com> References: <1520568765-58189-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH v2 15/23] RISC-V: Use memory_region_is_ram in pte update X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Michael Clark , Palmer Dabbelt , Sagar Karandikar Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" After reading cpu_physical_memory_write and friends, it seems that memory_region_is_ram is a more appropriate interface, and matches the intent of the code that is calling it. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/helper.c b/target/riscv/helper.c index 162d5ec..fc550d3 100644 --- a/target/riscv/helper.c +++ b/target/riscv/helper.c @@ -235,7 +235,7 @@ restart: rcu_read_lock(); mr =3D address_space_translate(cs->as, pte_addr, &addr1, &l, false); - if (memory_access_is_direct(mr, true)) { + if (memory_region_is_ram(mr)) { target_ulong *pte_pa =3D qemu_map_ram_ptr(mr->ram_block, addr1); #if TCG_OVERSIZED_GUEST --=20 2.7.0 From nobody Mon May 20 15:50:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1520569542808248.4241391624414; Thu, 8 Mar 2018 20:25:42 -0800 (PST) Received: from localhost ([::1]:43154 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eu9bC-0004Sr-1i for importer@patchew.org; Thu, 08 Mar 2018 23:25:42 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55847) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eu9Qp-0004Q6-MJ for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:15:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eu9Qo-00075X-HQ for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:14:59 -0500 Received: from mail-pl0-x241.google.com ([2607:f8b0:400e:c01::241]:45129) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eu9Qo-00075E-AY for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:14:58 -0500 Received: by mail-pl0-x241.google.com with SMTP id v9-v6so4592915plp.12 for ; Thu, 08 Mar 2018 20:14:58 -0800 (PST) Received: from localhost.localdomain (125-237-39-90-fibre.bb.spark.co.nz. [125.237.39.90]) by smtp.gmail.com with ESMTPSA id h15sm334141pfi.56.2018.03.08.20.14.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 08 Mar 2018 20:14:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+j/SSPlOst+oGGxyEGnpDqo/DJyW8hLnCdpp96OtkQY=; b=IMz19Uea7uOdkFGlvS33rrui0KJfAJp2P8y4GtRKM36ZEIFLY/W2+RypqgloeX/+O7 R4irzBcTMoDcwQzdKAmIlFYIVAmG+c8lKL5IJyH9MQKuLE7wFRE3a/vsnW3eGgC9MHTV kTVXavrMcFLOXdoEex8SLpjXS0an/3BCHa0Lv6c5CbjB1ykKHl2AwuU/Vg0lFZUwBSgE QxfWiZPKS7F5hjBGmSO4yQsuYlC/kWtFy7CDn5jfm6kSlOZ10sFMtF45PEdeswtPNjNu xtAUkI7la22OkuK2nrVIwfVNpVqTky1X1M3hVy4qIwl3PxnyCbwCNWPfI1vZzEDbHr7b KjAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+j/SSPlOst+oGGxyEGnpDqo/DJyW8hLnCdpp96OtkQY=; b=miJUthOOYPaXhoVa7Vd3Aem3QZ/esHfx4T+sqKIRt/UsxH/J4nGkjEj4f35cyJQPXf 913LrO958/Ql2IxjoxTITC0ONTiWmRk3by1Pb49ZZC4JSRNuBujHNgQg9aEfgGz+BNd3 k6Gr3ab8FNYLhFuNGBLToYs67BjIPj4Yuz1LBl+7hF5OO74/nwYkgSKHFisYDiZ/jJ4+ a9iFVkbwkb8hiVCbPPf0RDu/GcSyo6L3vo9bmBi3BgFqsUAO8kcauwhlonzaa0iFRDVf 23+UiC2t3vAdZJVaVIzkINfARUZsS2RiELYdijmq8RU8xhOPud7QVF4S+DxR4ABKYPhn SBsA== X-Gm-Message-State: AElRT7Ep9MTlBf59winvY117UKINY0X5FXXHAsX/IbDG2zSsw9C1agqb CSZ7fzsXjkLTNwigNbPPSQopPezOUdE= X-Google-Smtp-Source: AG47ELszQXZejrgsS8awPNq82lN9PLtcrmrWsw/gHo6nhuG/5vA9WbY7ICePbYA9cgIqIjAkZaIung== X-Received: by 2002:a17:902:70c5:: with SMTP id l5-v6mr6296713plt.13.1520568897380; Thu, 08 Mar 2018 20:14:57 -0800 (PST) From: Michael Clark To: qemu-devel@nongnu.org Date: Fri, 9 Mar 2018 17:12:38 +1300 Message-Id: <1520568765-58189-17-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1520568765-58189-1-git-send-email-mjc@sifive.com> References: <1520568765-58189-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::241 Subject: [Qemu-devel] [PATCH v2 16/23] RISC-V: Remove EM_RISCV ELF_MACHINE indirection X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Michael Clark , Palmer Dabbelt , Sagar Karandikar Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Pointless indirection. Other ports use EM_ constants directly. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/sifive_e.c | 2 +- hw/riscv/sifive_u.c | 2 +- hw/riscv/spike.c | 2 +- hw/riscv/virt.c | 2 +- target/riscv/cpu.h | 1 - 5 files changed, 4 insertions(+), 5 deletions(-) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 4872b68..39e4cb4 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -88,7 +88,7 @@ static uint64_t load_kernel(const char *kernel_filename) =20 if (load_elf(kernel_filename, NULL, NULL, &kernel_entry, NULL, &kernel_high, - 0, ELF_MACHINE, 1, 0) < 0) { + 0, EM_RISCV, 1, 0) < 0) { error_report("qemu: could not load kernel '%s'", kernel_filename); exit(1); } diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 57b4f4f..0e633a0 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -74,7 +74,7 @@ static uint64_t load_kernel(const char *kernel_filename) =20 if (load_elf(kernel_filename, NULL, NULL, &kernel_entry, NULL, &kernel_high, - 0, ELF_MACHINE, 1, 0) < 0) { + 0, EM_RISCV, 1, 0) < 0) { error_report("qemu: could not load kernel '%s'", kernel_filename); exit(1); } diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index c7d937b..70e697c 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -64,7 +64,7 @@ static uint64_t load_kernel(const char *kernel_filename) uint64_t kernel_entry, kernel_high; =20 if (load_elf_ram_sym(kernel_filename, NULL, NULL, - &kernel_entry, NULL, &kernel_high, 0, ELF_MACHINE, 1, 0, + &kernel_entry, NULL, &kernel_high, 0, EM_RISCV, 1, 0, NULL, true, htif_symbol_callback) < 0) { error_report("qemu: could not load kernel '%s'", kernel_filename); exit(1); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index d680cbd..e3f8bb7 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -68,7 +68,7 @@ static uint64_t load_kernel(const char *kernel_filename) =20 if (load_elf(kernel_filename, NULL, NULL, &kernel_entry, NULL, &kernel_high, - 0, ELF_MACHINE, 1, 0) < 0) { + 0, EM_RISCV, 1, 0) < 0) { error_report("qemu: could not load kernel '%s'", kernel_filename); exit(1); } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 3a0ca2f..7c4482b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -34,7 +34,6 @@ =20 #define TCG_GUEST_DEFAULT_MO 0 =20 -#define ELF_MACHINE EM_RISCV #define CPUArchState struct CPURISCVState =20 #include "qemu-common.h" --=20 2.7.0 From nobody Mon May 20 15:50:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 152056967891861.61850531674861; Thu, 8 Mar 2018 20:27:58 -0800 (PST) Received: from localhost ([::1]:43166 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eu9dF-0006Vm-LN for importer@patchew.org; Thu, 08 Mar 2018 23:27:49 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55870) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eu9Qs-0004Sn-6P for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:15:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eu9Qr-00076n-CS for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:15:02 -0500 Received: from mail-pl0-x244.google.com ([2607:f8b0:400e:c01::244]:33551) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eu9Qr-00076Y-6F for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:15:01 -0500 Received: by mail-pl0-x244.google.com with SMTP id c11-v6so4623402plo.0 for ; Thu, 08 Mar 2018 20:15:01 -0800 (PST) Received: from localhost.localdomain (125-237-39-90-fibre.bb.spark.co.nz. [125.237.39.90]) by smtp.gmail.com with ESMTPSA id h15sm334141pfi.56.2018.03.08.20.14.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 08 Mar 2018 20:14:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=skhNLehqLx7INkCfB7WkgTioVOYa2VI4KQLj/TiEtYM=; b=lwd3Hew1zQZhyL60M7r/jzQVZFLudaqvDjD5W/bDx/gOBGSKDg6TBBtTSdzU2SfA46 fgbwR1wZB3jnQyQN6pZ6FypKhrFu+CuALZ/URvbwnICTFKO4md3q1UBI472F0Fl4Q340 YIBAxDTWY+DluvOl44ywaOUOxO7GgodQQDqNFMuSOGL6KgTOtDIQwUwtWRNpO4LT/4zG 8ydnzb9K7vDRTLOzVMkl0oqYfLEgUJSjk5pqudZlny225xXH4U5GdOjSyGxg/5z/SDXQ Fn8A32jtefuAwM/e/edZDneSRC+DbVPVWYg1ImcCpHwt2mhDK/J65Ugvz0fH/rEjSjqK hc/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=skhNLehqLx7INkCfB7WkgTioVOYa2VI4KQLj/TiEtYM=; b=GKZMvINw/A+jO3PknPocxvuL7R0hjZC64ZgpXAogU3D5DnPbu7mi90TgbP9TIPp30I 5V/K+kl1zaN5LgmMbuel8twvVPKnq8cKZ59Wh11RjQbiEemrL55cNzCi4WWQd5YhvF0+ 0uHmr7Du2d1eKtVUO28mdlcoRMHw7C61JaZNwK7mLs+u1KY/aoq2BtdsgcRsyVdfYM/P j4x1o+9DsBBy8vhKrsCEFh26pEIPwgqu+fq8rE0obNxOGO6CYS7xkuYwpNiZqwo5b8kh N5HVOun1xzQ/JHTOSoKCiTzYMK/+o89SsQvd7u4l89iGPH7hxRGz/YaeQRrQ1RZARtl1 doYQ== X-Gm-Message-State: APf1xPDjsQS4gYoGr4mchBTJ/unQsQMoISbPdZ92AxYoPV7nuta735T7 nkqhtjncwcMQ0p9K7AbjYQ2grIjlGdE= X-Google-Smtp-Source: AG47ELs8RRCgKnUYaW4dijscSGPmC9GuAERIU9HY+aGNhqOqIUq48gYozIC9Z0Gc7rsF0suikXjjnA== X-Received: by 2002:a17:902:780c:: with SMTP id p12-v6mr26812900pll.161.1520568900345; Thu, 08 Mar 2018 20:15:00 -0800 (PST) From: Michael Clark To: qemu-devel@nongnu.org Date: Fri, 9 Mar 2018 17:12:39 +1300 Message-Id: <1520568765-58189-18-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1520568765-58189-1-git-send-email-mjc@sifive.com> References: <1520568765-58189-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PATCH v2 17/23] RISC-V: Hardwire satp to 0 for no-mmu case X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Michael Clark , Palmer Dabbelt , Sagar Karandikar Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" satp is WARL so it should not trap on illegal writes, rather it can be hardwired to zero and silently ignore illegal writes. It seems the RISC-V WARL behaviour is preferred to having to trap overhead versus simply reading back the value and checking if the write took (saves hundreds of cycles and more complex trap handling code). Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt --- target/riscv/op_helper.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index e34715d..dd3e417 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -242,7 +242,7 @@ void csr_write_helper(CPURISCVState *env, target_ulong = val_to_write, } case CSR_SATP: /* CSR_SPTBR */ { if (!riscv_feature(env, RISCV_FEATURE_MMU)) { - goto do_illegal; + break; } if (env->priv_ver <=3D PRIV_VERSION_1_09_1 && (val_to_write ^ env-= >sptbr)) { @@ -452,7 +452,10 @@ target_ulong csr_read_helper(CPURISCVState *env, targe= t_ulong csrno) return env->scounteren; case CSR_SCAUSE: return env->scause; - case CSR_SPTBR: + case CSR_SATP: /* CSR_SPTBR */ + if (!riscv_feature(env, RISCV_FEATURE_MMU)) { + return 0; + } if (env->priv_ver >=3D PRIV_VERSION_1_10_0) { return env->satp; } else { --=20 2.7.0 From nobody Mon May 20 15:50:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1520569525795968.325268887635; Thu, 8 Mar 2018 20:25:25 -0800 (PST) Received: from localhost ([::1]:43147 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eu9au-0004D5-V5 for importer@patchew.org; Thu, 08 Mar 2018 23:25:25 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55927) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eu9Qx-0004YW-FM for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:15:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eu9Qu-000786-9F for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:15:07 -0500 Received: from mail-pl0-x243.google.com ([2607:f8b0:400e:c01::243]:39670) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eu9Qu-00077g-3k for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:15:04 -0500 Received: by mail-pl0-x243.google.com with SMTP id s13-v6so4604663plq.6 for ; Thu, 08 Mar 2018 20:15:04 -0800 (PST) Received: from localhost.localdomain (125-237-39-90-fibre.bb.spark.co.nz. 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X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PATCH v2 18/23] RISC-V: Remove braces from satp case statement X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Michael Clark , Palmer Dabbelt , Sagar Karandikar Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/op_helper.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index dd3e417..f79716a 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -240,7 +240,7 @@ void csr_write_helper(CPURISCVState *env, target_ulong = val_to_write, csr_write_helper(env, next_mie, CSR_MIE); break; } - case CSR_SATP: /* CSR_SPTBR */ { + case CSR_SATP: /* CSR_SPTBR */ if (!riscv_feature(env, RISCV_FEATURE_MMU)) { break; } @@ -258,7 +258,6 @@ void csr_write_helper(CPURISCVState *env, target_ulong = val_to_write, env->satp =3D val_to_write; } break; - } case CSR_SEPC: env->sepc =3D val_to_write; break; --=20 2.7.0 From nobody Mon May 20 15:50:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 152056967507420.964296874699585; Thu, 8 Mar 2018 20:27:55 -0800 (PST) Received: from localhost ([::1]:43164 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eu9dC-0006Sl-5d for importer@patchew.org; Thu, 08 Mar 2018 23:27:46 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55938) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eu9Qy-0004ZQ-6X for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:15:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eu9Qx-000797-8i for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:15:08 -0500 Received: from mail-pl0-x243.google.com ([2607:f8b0:400e:c01::243]:36292) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eu9Qx-00078t-32 for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:15:07 -0500 Received: by mail-pl0-x243.google.com with SMTP id 61-v6so4614116plf.3 for ; Thu, 08 Mar 2018 20:15:07 -0800 (PST) Received: from localhost.localdomain (125-237-39-90-fibre.bb.spark.co.nz. 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X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PATCH v2 19/23] RISC-V: riscv-qemu port supports sv39 and sv48 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Michael Clark , Palmer Dabbelt , Sagar Karandikar Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7c4482b..f47fc9c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -24,8 +24,8 @@ #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */ #if defined(TARGET_RISCV64) #define TARGET_LONG_BITS 64 -#define TARGET_PHYS_ADDR_SPACE_BITS 50 -#define TARGET_VIRT_ADDR_SPACE_BITS 39 +#define TARGET_PHYS_ADDR_SPACE_BITS 52 +#define TARGET_VIRT_ADDR_SPACE_BITS 48 #elif defined(TARGET_RISCV32) #define TARGET_LONG_BITS 32 #define TARGET_PHYS_ADDR_SPACE_BITS 34 --=20 2.7.0 From nobody Mon May 20 15:50:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1520569797902157.8933493235677; Thu, 8 Mar 2018 20:29:57 -0800 (PST) Received: from localhost ([::1]:43176 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eu9fJ-0008Sv-3M for importer@patchew.org; Thu, 08 Mar 2018 23:29:57 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55963) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eu9R1-0004cR-3g for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:15:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eu9R0-0007AT-9C for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:15:11 -0500 Received: from mail-pf0-x244.google.com ([2607:f8b0:400e:c00::244]:46298) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eu9R0-0007AB-2w for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:15:10 -0500 Received: by mail-pf0-x244.google.com with SMTP id z10so826722pfh.13 for ; Thu, 08 Mar 2018 20:15:10 -0800 (PST) Received: from localhost.localdomain (125-237-39-90-fibre.bb.spark.co.nz. [125.237.39.90]) by smtp.gmail.com with ESMTPSA id h15sm334141pfi.56.2018.03.08.20.15.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 08 Mar 2018 20:15:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bt2M/AHC9Y7szQPwhX3hgmhil+uRswKhQTDlPUwKQgg=; b=kHkjJfBLJyNMdNmEa/349DKw+myrx0FIoD1/zx0xHLjYQO0ozfOyALGVCC6QWYiSwG sBjDQHrb9/XFUoe30Nuz/xrM1vdZZHoStCCK6CunRLHFzpCyMD5mnHsaN1EQqxEpT5o3 yudfqUdvqinquWAQ2SHoAJIZv5FxefSmgzrxKjXBMrV5nfEGHUk5y+rEMOr5oAlRI5zG QxDG5ZPrca30raAn731yDihkvmbAWH7IUeVJKYW0iz9UKmB2g7JeuYkd0G2zuES4bfd6 ojpfpasRl9P+IKpRbRfS/p74cOc4muf/6qi0broMhyfDM6Q7bwjfJaJbO9K6mFGGf4ah 1qLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bt2M/AHC9Y7szQPwhX3hgmhil+uRswKhQTDlPUwKQgg=; b=HytP4RshesEY/2V3Z4mwuVu779h0ryUr28h0NSCRhWmljT7GHtovzoYkX71NPrPkIY NfjWFqQoTFChTByeR3yD1J/iF6/Q5oVvG1yxoNhEfWwiBVXhF2ZgfjJq3g5VJhkRnKJh JME26eErMuSWWTrazvF8mttw1BEAR2GL3rVj5me0lwy7ZZnprnkQB8888ujhUjM3DGFi LQfJ7n4q1nOd2HE1Yt3a/fVaqr7SlsZ5HM71AV1GxvKvcCS+zKr6JuPyIftoiahosazi TYkIWQphvgK0ufXnXoCKDZniiWi4vVzYZu7LdJ88LFyYgPscIQ8Mk1oOyeu6lYrO+6wK r0fg== X-Gm-Message-State: APf1xPBYI5on4FvWnWpRNBo16ZpuD+iGYLQRZ6TtbKf19LZ0Gf2C35WR Gnq8+YZwwKjsZw3oEbIkFJ0BKDyEzn0= X-Google-Smtp-Source: AG47ELs97y3tS4QV/3fRA8JRaXSaUN0+JMPjmUMfbXnGYfjiHLjp3K3Dxxj/oPbtB9GKe1uVY4ZjcQ== X-Received: by 10.101.100.208 with SMTP id t16mr22250767pgv.398.1520568909135; Thu, 08 Mar 2018 20:15:09 -0800 (PST) From: Michael Clark To: qemu-devel@nongnu.org Date: Fri, 9 Mar 2018 17:12:42 +1300 Message-Id: <1520568765-58189-21-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1520568765-58189-1-git-send-email-mjc@sifive.com> References: <1520568765-58189-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH v2 20/23] RISC-V: vectored traps are optional X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Michael Clark , Palmer Dabbelt , Sagar Karandikar Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Vectored traps for asynchrounous interrupts are optional. The mtvec/stvec mode field is WARL and hence does not trap if an illegal value is written. Illegal values are ignored. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt --- target/riscv/op_helper.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index f79716a..aa101cc 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -262,11 +262,10 @@ void csr_write_helper(CPURISCVState *env, target_ulon= g val_to_write, env->sepc =3D val_to_write; break; case CSR_STVEC: - if (val_to_write & 1) { - qemu_log_mask(LOG_UNIMP, "CSR_STVEC: vectored traps not suppor= ted"); - goto do_illegal; + /* we do not support vectored traps for asynchrounous interrupts *= /=20 + if ((val_to_write & 3) =3D=3D 0) { + env->stvec =3D val_to_write >> 2 << 2; } - env->stvec =3D val_to_write >> 2 << 2; break; case CSR_SCOUNTEREN: env->scounteren =3D val_to_write; @@ -284,11 +283,10 @@ void csr_write_helper(CPURISCVState *env, target_ulon= g val_to_write, env->mepc =3D val_to_write; break; case CSR_MTVEC: - if (val_to_write & 1) { - qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: vectored traps not suppor= ted"); - goto do_illegal; + /* we do not support vectored traps for asynchrounous interrupts *= /=20 + if ((val_to_write & 3) =3D=3D 0) { + env->mtvec =3D val_to_write >> 2 << 2; } - env->mtvec =3D val_to_write >> 2 << 2; break; case CSR_MCOUNTEREN: env->mcounteren =3D val_to_write; --=20 2.7.0 From nobody Mon May 20 15:50:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1520569940083535.1480733938918; Thu, 8 Mar 2018 20:32:20 -0800 (PST) Received: from localhost ([::1]:43191 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eu9hb-0001or-Ap for importer@patchew.org; Thu, 08 Mar 2018 23:32:19 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56019) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eu9R6-0004hW-7A for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:15:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eu9R3-0007C9-8P for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:15:16 -0500 Received: from mail-pl0-x244.google.com ([2607:f8b0:400e:c01::244]:37655) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eu9R3-0007Bq-1u for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:15:13 -0500 Received: by mail-pl0-x244.google.com with SMTP id w12-v6so4619435plp.4 for ; Thu, 08 Mar 2018 20:15:13 -0800 (PST) Received: from localhost.localdomain (125-237-39-90-fibre.bb.spark.co.nz. [125.237.39.90]) by smtp.gmail.com with ESMTPSA id h15sm334141pfi.56.2018.03.08.20.15.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 08 Mar 2018 20:15:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=elXEjrujeHBejLZefg5SAzL2dxTnnLrXWqzO68PGJuU=; b=BL6Mg7OOSX8Ef0xyL5aYxhoUJbW0a5EoJH5a5zfUmQ5lV+Rtj7nYSF6NN6T+8oz12k Ed72Ts198Bb24IibjkiSked6lx5d7dbD/H6DeheyVvMAADK9za5G+p1gRU9rj0ooI+nn KUO6lribDcuxCnz/agWPp3gERaIxaUk0eMG2lTu7pyA54uf71XJoV9iINKSy+A672swK 2E3TExkohnB4rQWcRyVE54s1y0+8zeSldydWsUAx062SG8UNNEzQR0vcgrxYK4gte2i4 gwmM789kUD3ykihYE+QHZ2w1r7QdSpHhR1o7pCluilYvynBmqXnKZ9sPRRkG9gMOX/tg 27Mw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=elXEjrujeHBejLZefg5SAzL2dxTnnLrXWqzO68PGJuU=; b=fGYO0KfUmG8Kk3WJ+WHOlnVgSLbaxAE9y2y9qsrksUvlkef76+2zmG6wdgbFASGaxr Vtb/fl2OhQUjGzu6BaHgudlRo5sIyBS0BnghV6tCq7pJc6P7XWHg+joFJiUvyIKZWyEl HIc8t2oDVBxtlbviqAxpxPsGV7OUu5b9o/w8WjW5idgQ4w+RL4XFHWCoK68QCz7hQgl9 C9fGHhE9FLFrZZqFhNdOSfkU4uPRMmosMz9jo33m5LWOX9OU2P5yodxKPi9bmZ5LYPBh DdVe5WDSUG/cChDfLo0e/jvaq/ZVSWr7S8JFiUjvNfDa++VH6+0/IiQbIXNQ3s+OWm65 gI+w== X-Gm-Message-State: AElRT7GWgLo5rnyYPR5B//gbE7v2GauGGTPyNh5nfvMniZm2DSOqYbuh MeOguA4qX73agOK9iDjIUxtRugdrbMI= X-Google-Smtp-Source: AG47ELtD2pjxoQwJwo4URgba6LvM2mfLs0Ow4FJWWdRNbgDSlT7SIP20Tg0KMJp39kx6ZW0QsoJBiQ== X-Received: by 2002:a17:902:bf03:: with SMTP id bi3-v6mr21030074plb.343.1520568912207; Thu, 08 Mar 2018 20:15:12 -0800 (PST) From: Michael Clark To: qemu-devel@nongnu.org Date: Fri, 9 Mar 2018 17:12:43 +1300 Message-Id: <1520568765-58189-22-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1520568765-58189-1-git-send-email-mjc@sifive.com> References: <1520568765-58189-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PATCH v2 21/23] RISC-V: No traps on writes to misa, minstret, mcycle X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Michael Clark , Palmer Dabbelt , Sagar Karandikar Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" These fields are marked WARL in the specification so illegal writes are silently dropped. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt --- target/riscv/op_helper.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index aa101cc..f8595a6 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -200,17 +200,19 @@ void csr_write_helper(CPURISCVState *env, target_ulon= g val_to_write, break; } case CSR_MINSTRET: - qemu_log_mask(LOG_UNIMP, "CSR_MINSTRET: write not implemented"); - goto do_illegal; + /* minstret is WARL so unsupported writes are ignored */ + break; case CSR_MCYCLE: - qemu_log_mask(LOG_UNIMP, "CSR_MCYCLE: write not implemented"); - goto do_illegal; + /* mcycle is WARL so unsupported writes are ignored */ + break; +#if defined(TARGET_RISCV32) case CSR_MINSTRETH: - qemu_log_mask(LOG_UNIMP, "CSR_MINSTRETH: write not implemented"); - goto do_illegal; + /* minstreth is WARL so unsupported writes are ignored */ + break; case CSR_MCYCLEH: - qemu_log_mask(LOG_UNIMP, "CSR_MCYCLEH: write not implemented"); - goto do_illegal; + /* mcycleh is WARL so unsupported writes are ignored */ + break; +#endif case CSR_MUCOUNTEREN: env->mucounteren =3D val_to_write; break; @@ -300,10 +302,9 @@ void csr_write_helper(CPURISCVState *env, target_ulong= val_to_write, case CSR_MBADADDR: env->mbadaddr =3D val_to_write; break; - case CSR_MISA: { - qemu_log_mask(LOG_UNIMP, "CSR_MISA: misa writes not supported"); - goto do_illegal; - } + case CSR_MISA: + /* misa is WARL so unsupported writes are ignored */ + break; case CSR_PMPCFG0: case CSR_PMPCFG1: case CSR_PMPCFG2: @@ -328,7 +329,6 @@ void csr_write_helper(CPURISCVState *env, target_ulong = val_to_write, case CSR_PMPADDR15: pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val_to_write); break; - do_illegal: #endif default: do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); --=20 2.7.0 From nobody Mon May 20 15:50:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1520569794788203.26177072942744; Thu, 8 Mar 2018 20:29:54 -0800 (PST) Received: from localhost ([::1]:43175 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eu9fF-0008Pv-Ug for importer@patchew.org; Thu, 08 Mar 2018 23:29:54 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56037) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eu9R7-0004im-FZ for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:15:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eu9R6-0007FU-6V for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:15:17 -0500 Received: from mail-pl0-x242.google.com ([2607:f8b0:400e:c01::242]:43773) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eu9R5-0007Di-Vu for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:15:16 -0500 Received: by mail-pl0-x242.google.com with SMTP id f23-v6so4609731plr.10 for ; Thu, 08 Mar 2018 20:15:15 -0800 (PST) Received: from localhost.localdomain (125-237-39-90-fibre.bb.spark.co.nz. [125.237.39.90]) by smtp.gmail.com with ESMTPSA id h15sm334141pfi.56.2018.03.08.20.15.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 08 Mar 2018 20:15:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VoByu3qAZNTRbnvBtyhKGH0UNxevYf7YuBxpaK2evpQ=; b=Y4FkCcEvO00xJS7QeCTkdGGuuEh6bOp/cKhbc7s1ccRHLvQoMyOrn4IHnjAt6Oia9m yFLMGSJLjAqpttGO0qiV7yQIGC3fzEzFcJBsYybUHaesAVvfeZgEfTW7Hl+z3KtpRrdO 0KeKxOWXvYZ1rEZHKcBNc3odjTEDrq+szxTrl/hck29R3y1dxcUc+xe/OoCQ8Kt3WY+V m7jzkO8fjz9aS6qc4AVVUTMZfx7rRWBY2hbvQXTwkJ+AkZ0OwMcmtsCcwUcSmbkXgP3l /aMbkrv4ouHFU0s4eVq43XPDWzQvQ5tUvd4mVhaNFCfj0ANVcPgZ1gtLyrYMrKGb0NcP 5kYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VoByu3qAZNTRbnvBtyhKGH0UNxevYf7YuBxpaK2evpQ=; b=HnE8OD+aq/Bydo5e7GH5K6EdrVQ4ONwiHxFqVdK6h2PD1j7ENDvCg0N/Kgj1vep6Mg /y3uWyVcD8H6l61wp83XnjjmZOhPIsllOzfqj01k0RZHZyKsxY89ZWtd0dYYHcPz+7tC G1LM3UdSKSVRbDDhE8yRZXk9iNyESQba8KB1m3a4L/p7DDRGgTG5nT+dprPUHtFvBnkF 6wAPiB07Q8LunZct6c6XX/7wRP0/iNU5ohmf+juLC6wQML802cxCGWAxiu7OvxIU9A2h n0zgo/qwnfAjuAswEsIGoZYRHQC1hPd5m3gALCB0vLBULdLrjLxrDTXH21nxWhdUMzt+ OA/A== X-Gm-Message-State: APf1xPA7uhXjRYEn1ukFotQFF24ZahhXJEH4qbeldcnOTpazkGZShMvP rnryGrh409LYVhFaLnSweNr08BCgCuk= X-Google-Smtp-Source: AG47ELs36TG7low76d2OKQtbe5vlPUQvyOLuFUvXze0S2AJzKsVYXU89ep+TakM1mFtgTeetcQZLLw== X-Received: by 2002:a17:902:b903:: with SMTP id bf3-v6mr26682656plb.316.1520568915120; Thu, 08 Mar 2018 20:15:15 -0800 (PST) From: Michael Clark To: qemu-devel@nongnu.org Date: Fri, 9 Mar 2018 17:12:44 +1300 Message-Id: <1520568765-58189-23-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1520568765-58189-1-git-send-email-mjc@sifive.com> References: <1520568765-58189-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH v2 22/23] RISC-V: Remove support for adhoc X_COP interrupt X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Michael Clark , Palmer Dabbelt , Sagar Karandikar Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is essentially dead-code elimination. Support for more local interrupts will be added in a future revision, as they will be defined in a future version of the Privileged ISA specification. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt --- target/riscv/cpu_bits.h | 1 - target/riscv/op_helper.c | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 12b4757..133e070 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -346,7 +346,6 @@ #define IRQ_S_EXT 9 #define IRQ_H_EXT 10 /* until: priv-1.9.1 */ #define IRQ_M_EXT 11 /* until: priv-1.9.1 */ -#define IRQ_X_COP 12 /* non-standard */ =20 /* Default addresses */ #define DEFAULT_RSTVEC 0x00001000 diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index f8595a6..f543e61 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -90,7 +90,7 @@ void csr_write_helper(CPURISCVState *env, target_ulong va= l_to_write, target_ulong csrno) { #ifndef CONFIG_USER_ONLY - uint64_t delegable_ints =3D MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ= _X_COP); + uint64_t delegable_ints =3D MIP_SSIP | MIP_STIP | MIP_SEIP; uint64_t all_ints =3D delegable_ints | MIP_MSIP | MIP_MTIP; #endif =20 --=20 2.7.0 From nobody Mon May 20 15:50:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 152056999763520.972688886630635; Thu, 8 Mar 2018 20:33:17 -0800 (PST) Received: from localhost ([::1]:43192 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eu9iN-0002G3-Rw for importer@patchew.org; Thu, 08 Mar 2018 23:33:07 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56072) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eu9RB-0004lJ-AE for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:15:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eu9RA-0007KK-2e for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:15:21 -0500 Received: from mail-pl0-x244.google.com ([2607:f8b0:400e:c01::244]:38001) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eu9R9-0007JW-BI for qemu-devel@nongnu.org; Thu, 08 Mar 2018 23:15:19 -0500 Received: by mail-pl0-x244.google.com with SMTP id m22-v6so4620761pls.5 for ; Thu, 08 Mar 2018 20:15:19 -0800 (PST) Received: from localhost.localdomain (125-237-39-90-fibre.bb.spark.co.nz. [125.237.39.90]) by smtp.gmail.com with ESMTPSA id h15sm334141pfi.56.2018.03.08.20.15.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 08 Mar 2018 20:15:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+FPO4FUGVGGilTNb0qA0hw1TJozXzFAPMyAvHhLGQUg=; b=EzgqDM9+I0JjrTsuKf3dXozsflHkL9wK9aOI9PR9rHBt9SLbql9XOISqFZN+PJa9ur oNyVBoKcZ5XDOAPMoLYNFtKZdtazeTX7HMQW4DRNhJw4B8/LCH/K5wgwbDU0ynkzQnfA ltrk+3hjuKCeNLjPI0wU+mmVLKuFgyAnJJkDrxGfpZcGoEODciorteLhQAfoSiJ4knzj Aj5uWvcuGUSMHQsNt0YXo4INw2Ghkjs2zQ3tX05jE4lIxGQt9hgU12oQyh3Z6KoaSlAi M2kovzcWl6CWvzAdkn2XWEHYKRS0PRjGZrVGc7gelWoE7PlWfKsVcRhsgQShrD5dErM0 QIqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+FPO4FUGVGGilTNb0qA0hw1TJozXzFAPMyAvHhLGQUg=; b=JQP/yCxjvlaO1V8+8FnAgl5//Bvqh7xzId5Y73KLM7vmiOvyqeLWMdDxI/FnZHqb0q HNV22xFKJcO41HqYKrxo9xVgMg/D2oUk9AI+XuqGFdlARD2yB5j+dYHJG9cdoY8La9Na kQOwNQMJV7JmR/mAVh3ev06u3qyOd7zIHFO+0c0yE1Lpg6k+xSMK9bI5yRKcwDpOLDw6 GZGOokJ1nTEn178forA0ZQDsuJrIH4JmFxsycYpzubs/1GjEz0kygzbZuzl5Gv4d3GnC XMkwT1QTxuKGshWCtM0lLgYemXJRYRfnxOEQdto3FvBBrcXKXHYTqC2MNK+UM3KjFaIm 4iOA== X-Gm-Message-State: APf1xPDeAKxTGDltu5Ok2LeSgXcFQisvlFMVpt88n5MMl+aaiyL/uAUp uGD8rSYD69iE69b+njTSTHm8HupPSAQ= X-Google-Smtp-Source: AG47ELveoALNznBhqviewpJrVOQCkHXH7BlOsu01dm0T6w7iNRka3jNs4JXpxzZ9IwKXyRK1JjGKHQ== X-Received: by 2002:a17:902:7686:: with SMTP id m6-v6mr26720396pll.199.1520568918474; Thu, 08 Mar 2018 20:15:18 -0800 (PST) From: Michael Clark To: qemu-devel@nongnu.org Date: Fri, 9 Mar 2018 17:12:45 +1300 Message-Id: <1520568765-58189-24-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1520568765-58189-1-git-send-email-mjc@sifive.com> References: <1520568765-58189-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PATCH v2 23/23] RISC-V: Convert cpu definition towards future model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Igor Mammedov , Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" - Model borrowed from target/sh4/cpu.c - Rewrote riscv_cpu_list to use object_class_get_list - Dropped 'struct RISCVCPUInfo' and used TypeInfo array - Replaced riscv_cpu_register_types with DEFINE_TYPES - Marked base class as abstract Cc: Igor Mammedov Cc: Palmer Dabbelt Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by Michael Clark Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/cpu.c | 123 ++++++++++++++++++++++++++++++-------------------= ---- 1 file changed, 69 insertions(+), 54 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d2ae56a..1f25968 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -115,6 +115,8 @@ static void riscv_any_cpu_init(Object *obj) set_resetvec(env, DEFAULT_RSTVEC); } =20 +#if defined(TARGET_RISCV32) + static void rv32gcsu_priv1_09_1_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; @@ -141,6 +143,8 @@ static void rv32imacu_nommu_cpu_init(Object *obj) set_resetvec(env, DEFAULT_RSTVEC); } =20 +#elif defined(TARGET_RISCV64) + static void rv64gcsu_priv1_09_1_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; @@ -167,20 +171,7 @@ static void rv64imacu_nommu_cpu_init(Object *obj) set_resetvec(env, DEFAULT_RSTVEC); } =20 -static const RISCVCPUInfo riscv_cpus[] =3D { - { 96, TYPE_RISCV_CPU_ANY, riscv_any_cpu_init }, - { 32, TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init }, - { 32, TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init }, - { 32, TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init }, - { 32, TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init }, - { 32, TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init }, - { 64, TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init }, - { 64, TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init }, - { 64, TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init }, - { 64, TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init }, - { 64, TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init }, - { 0, NULL, NULL } -}; +#endif =20 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) { @@ -366,28 +357,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void = *data) cc->vmsd =3D &vmstate_riscv_cpu; } =20 -static void cpu_register(const RISCVCPUInfo *info) -{ - TypeInfo type_info =3D { - .name =3D info->name, - .parent =3D TYPE_RISCV_CPU, - .instance_size =3D sizeof(RISCVCPU), - .instance_init =3D info->initfn, - }; - - type_register(&type_info); -} - -static const TypeInfo riscv_cpu_type_info =3D { - .name =3D TYPE_RISCV_CPU, - .parent =3D TYPE_CPU, - .instance_size =3D sizeof(RISCVCPU), - .instance_init =3D riscv_cpu_init, - .abstract =3D false, - .class_size =3D sizeof(RISCVCPUClass), - .class_init =3D riscv_cpu_class_init, -}; - char *riscv_isa_string(RISCVCPU *cpu) { int i; @@ -403,30 +372,76 @@ char *riscv_isa_string(RISCVCPU *cpu) return isa_string; } =20 -void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf) +typedef struct RISCVCPUListState { + fprintf_function cpu_fprintf; + FILE *file; +} RISCVCPUListState; + +static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) { - const RISCVCPUInfo *info =3D riscv_cpus; + ObjectClass *class_a =3D (ObjectClass *)a; + ObjectClass *class_b =3D (ObjectClass *)b; + const char *name_a, *name_b; =20 - while (info->name) { - if (info->bit_widths & TARGET_LONG_BITS) { - (*cpu_fprintf)(f, "%s\n", info->name); - } - info++; - } + name_a =3D object_class_get_name(class_a); + name_b =3D object_class_get_name(class_b); + return strcmp(name_a, name_b); } =20 -static void riscv_cpu_register_types(void) +static void riscv_cpu_list_entry(gpointer data, gpointer user_data) { - const RISCVCPUInfo *info =3D riscv_cpus; + RISCVCPUListState *s =3D user_data; + const char *typename =3D object_class_get_name(OBJECT_CLASS(data)); + int len =3D strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); =20 - type_register_static(&riscv_cpu_type_info); + (*s->cpu_fprintf)(s->file, "%.*s\n", len, typename); +} =20 - while (info->name) { - if (info->bit_widths & TARGET_LONG_BITS) { - cpu_register(info); - } - info++; - } +void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf) +{ + RISCVCPUListState s =3D { + .cpu_fprintf =3D cpu_fprintf, + .file =3D f, + }; + GSList *list; + + list =3D object_class_get_list(TYPE_RISCV_CPU, false); + list =3D g_slist_sort(list, riscv_cpu_list_compare); + g_slist_foreach(list, riscv_cpu_list_entry, &s); + g_slist_free(list); } =20 -type_init(riscv_cpu_register_types) +#define DEFINE_CPU(type_name, initfn) \ + { \ + .name =3D type_name, \ + .parent =3D TYPE_RISCV_CPU, \ + .instance_init =3D initfn \ + } + +static const TypeInfo riscv_cpu_type_infos[] =3D { + { + .name =3D TYPE_RISCV_CPU, + .parent =3D TYPE_CPU, + .instance_size =3D sizeof(RISCVCPU), + .instance_init =3D riscv_cpu_init, + .abstract =3D true, + .class_size =3D sizeof(RISCVCPUClass), + .class_init =3D riscv_cpu_class_init, + }, + DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), +#if defined(TARGET_RISCV32) + DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_in= it), + DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_in= it), + DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_in= it) +#elif defined(TARGET_RISCV64) + DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_in= it), + DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_in= it), + DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_in= it) +#endif +}; + +DEFINE_TYPES(riscv_cpu_type_infos) --=20 2.7.0