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[125.237.39.90]) by smtp.gmail.com with ESMTPSA id y6sm39123791pfg.71.2018.03.06.12.45.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 06 Mar 2018 12:45:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=K4rCrznVRhCHXTdveldfo6BSSBxabwWybwWvx3oombk=; b=O3yY4AwyG+Bag3VtRAa7X020MCix8h2e3K1nIj8SOpBqE21uLH3apO1YQc/OBYlVHF RldvgnxIHR5u/vMYrsuuz1gZWG8sywwZHirYuFWFyDdUfPo/RwLxyMzHL1b3fH8/R0aF NVgZGZ0fs5q5KTJoQsVcxAp1i6iA4QhmfsSLWqWqs2zh7cyqV7H2eTB7etlO6mDiYBe2 RIBvdteZsqWkpLjhU7DjeyUe8fEMTHkJi2DXdmcaOLliftNXSZtY/5XZ4TytNDFq/faJ /ow+oHpXMwAsCsPRD0CtMcOkWM19XkQdDuefcVMcN2KU9U1fCPeeUIYy3C/ef+YZEgic cJAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=K4rCrznVRhCHXTdveldfo6BSSBxabwWybwWvx3oombk=; b=moRG56LShFGxxDuaU0A2MAwfWgocCDEj+kiJ/FHDzaHWLirG+YWb4ImwyEA5Vwk3Ar htXT4rk93WPgj5lxfVNVBNiKqSAA1i3Asiie+SNIamJg1sqQ6zKONMg7QoGciYOo3iEu +IZujIhXCrzzDeBcwYf1/GBppT6VW1C89nz6cH4UgQGN4611+DROymyMdgkSALQNnFUr ruRmQoX/6jVqfs12yXNzm3U49heqLvAEXGzFF2zfIessr+NKvxCDs+tcX84Zy14Dj9Tl b2Nh3V2IueBuFBkKzLmzJ//+X7cxroSzgIetat1R5o1FDb6jdscMsy1maz04RkKlJ2dJ Q4dQ== X-Gm-Message-State: APf1xPCBYL8YsQjRA3rf4pk2qZRvIh660MKYC0i17LhRyF8TCbHDCyOp piWGf8icXLMXskJQq0r0MlVTuSOg8xo= X-Google-Smtp-Source: AG47ELv08SPNE/2epcHeBX8VB51PIbBFunaDekA9lUkhsObSgljsMiW5ZVOhRX4Rd7S1+ZAH7SXAkg== X-Received: by 10.99.44.22 with SMTP id s22mr16204104pgs.111.1520369134605; Tue, 06 Mar 2018 12:45:34 -0800 (PST) From: Michael Clark To: qemu-devel@nongnu.org Date: Wed, 7 Mar 2018 09:43:42 +1300 Message-Id: <1520369037-37977-8-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1520369037-37977-1-git-send-email-mjc@sifive.com> References: <1520369037-37977-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH v1 07/22] RISC-V: Remove unused class definitions from X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Michael Clark , Palmer Dabbelt , Sagar Karandikar , RISC-V Patches machines Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Removes a whole lot of unnecessary boilerplate code. Machines don't need to be objects. The expansion of the SOC object model for the RISC-V machines will happen in the future as SiFive plans to add their FE310 and FU540 SOCs to QEMU. However, it seems that this present boilerplate is complete unnecessary. Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_e.c | 25 ------------------------- hw/riscv/sifive_u.c | 25 ------------------------- hw/riscv/spike.c | 20 -------------------- hw/riscv/virt.c | 25 ------------------------- include/hw/riscv/sifive_e.h | 9 --------- include/hw/riscv/sifive_u.h | 9 --------- include/hw/riscv/virt.h | 9 --------- 7 files changed, 122 deletions(-) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 09c9d49..4872b68 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -194,24 +194,6 @@ static void riscv_sifive_e_init(MachineState *machine) } } =20 -static int riscv_sifive_e_sysbus_device_init(SysBusDevice *sysbusdev) -{ - return 0; -} - -static void riscv_sifive_e_class_init(ObjectClass *klass, void *data) -{ - SysBusDeviceClass *k =3D SYS_BUS_DEVICE_CLASS(klass); - k->init =3D riscv_sifive_e_sysbus_device_init; -} - -static const TypeInfo riscv_sifive_e_device =3D { - .name =3D TYPE_SIFIVE_E, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(SiFiveEState), - .class_init =3D riscv_sifive_e_class_init, -}; - static void riscv_sifive_e_machine_init(MachineClass *mc) { mc->desc =3D "RISC-V Board compatible with SiFive E SDK"; @@ -220,10 +202,3 @@ static void riscv_sifive_e_machine_init(MachineClass *= mc) } =20 DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init) - -static void riscv_sifive_e_register_types(void) -{ - type_register_static(&riscv_sifive_e_device); -} - -type_init(riscv_sifive_e_register_types); diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 25df16c..083043a 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -302,31 +302,6 @@ static void riscv_sifive_u_init(MachineState *machine) SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); } =20 -static int riscv_sifive_u_sysbus_device_init(SysBusDevice *sysbusdev) -{ - return 0; -} - -static void riscv_sifive_u_class_init(ObjectClass *klass, void *data) -{ - SysBusDeviceClass *k =3D SYS_BUS_DEVICE_CLASS(klass); - k->init =3D riscv_sifive_u_sysbus_device_init; -} - -static const TypeInfo riscv_sifive_u_device =3D { - .name =3D TYPE_SIFIVE_U, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(SiFiveUState), - .class_init =3D riscv_sifive_u_class_init, -}; - -static void riscv_sifive_u_register_types(void) -{ - type_register_static(&riscv_sifive_u_device); -} - -type_init(riscv_sifive_u_register_types); - static void riscv_sifive_u_machine_init(MachineClass *mc) { mc->desc =3D "RISC-V Board compatible with SiFive U SDK"; diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 74edf33..64e585e 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -336,18 +336,6 @@ static void spike_v1_09_1_board_init(MachineState *mac= hine) smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); } =20 -static const TypeInfo spike_v_1_09_1_device =3D { - .name =3D TYPE_RISCV_SPIKE_V1_09_1_BOARD, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(SpikeState), -}; - -static const TypeInfo spike_v_1_10_0_device =3D { - .name =3D TYPE_RISCV_SPIKE_V1_10_0_BOARD, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(SpikeState), -}; - static void spike_v1_09_1_machine_init(MachineClass *mc) { mc->desc =3D "RISC-V Spike Board (Privileged ISA v1.9.1)"; @@ -365,11 +353,3 @@ static void spike_v1_10_0_machine_init(MachineClass *m= c) =20 DEFINE_MACHINE("spike_v1.9.1", spike_v1_09_1_machine_init) DEFINE_MACHINE("spike_v1.10", spike_v1_10_0_machine_init) - -static void riscv_spike_board_register_types(void) -{ - type_register_static(&spike_v_1_09_1_device); - type_register_static(&spike_v_1_10_0_device); -} - -type_init(riscv_spike_board_register_types); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index f1e3641..5913100 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -380,24 +380,6 @@ static void riscv_virt_board_init(MachineState *machin= e) serial_hds[0], DEVICE_LITTLE_ENDIAN); } =20 -static int riscv_virt_board_sysbus_device_init(SysBusDevice *sysbusdev) -{ - return 0; -} - -static void riscv_virt_board_class_init(ObjectClass *klass, void *data) -{ - SysBusDeviceClass *k =3D SYS_BUS_DEVICE_CLASS(klass); - k->init =3D riscv_virt_board_sysbus_device_init; -} - -static const TypeInfo riscv_virt_board_device =3D { - .name =3D TYPE_RISCV_VIRT_BOARD, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(RISCVVirtState), - .class_init =3D riscv_virt_board_class_init, -}; - static void riscv_virt_board_machine_init(MachineClass *mc) { mc->desc =3D "RISC-V VirtIO Board (Privileged ISA v1.10)"; @@ -406,10 +388,3 @@ static void riscv_virt_board_machine_init(MachineClass= *mc) } =20 DEFINE_MACHINE("virt", riscv_virt_board_machine_init) - -static void riscv_virt_board_register_types(void) -{ - type_register_static(&riscv_virt_board_device); -} - -type_init(riscv_virt_board_register_types); diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h index 0aebc57..818fbdc 100644 --- a/include/hw/riscv/sifive_e.h +++ b/include/hw/riscv/sifive_e.h @@ -19,16 +19,7 @@ #ifndef HW_SIFIVE_E_H #define HW_SIFIVE_E_H =20 -#define TYPE_SIFIVE_E "riscv.sifive_e" - -#define SIFIVE_E(obj) \ - OBJECT_CHECK(SiFiveEState, (obj), TYPE_SIFIVE_E) - typedef struct SiFiveEState { - /*< private >*/ - SysBusDevice parent_obj; - - /*< public >*/ RISCVHartArrayState soc; DeviceState *plic; } SiFiveEState; diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index be38aa0..8ebd545 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -19,16 +19,7 @@ #ifndef HW_SIFIVE_U_H #define HW_SIFIVE_U_H =20 -#define TYPE_SIFIVE_U "riscv.sifive_u" - -#define SIFIVE_U(obj) \ - OBJECT_CHECK(SiFiveUState, (obj), TYPE_SIFIVE_U) - typedef struct SiFiveUState { - /*< private >*/ - SysBusDevice parent_obj; - - /*< public >*/ RISCVHartArrayState soc; DeviceState *plic; void *fdt; diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 655e85d..9588909 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -19,15 +19,7 @@ #ifndef HW_VIRT_H #define HW_VIRT_H =20 -#define TYPE_RISCV_VIRT_BOARD "riscv.virt" -#define VIRT(obj) \ - OBJECT_CHECK(RISCVVirtState, (obj), TYPE_RISCV_VIRT_BOARD) - typedef struct { - /*< private >*/ - SysBusDevice parent_obj; - - /*< public >*/ RISCVHartArrayState soc; DeviceState *plic; void *fdt; @@ -45,7 +37,6 @@ enum { VIRT_DRAM }; =20 - enum { UART0_IRQ =3D 10, VIRTIO_IRQ =3D 1, /* 1 to 8 */ --=20 2.7.0