From nobody Fri Oct 24 22:00:19 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1520227149684449.61968918534546; Sun, 4 Mar 2018 21:19:09 -0800 (PST) Received: from localhost ([::1]:47178 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1esiWd-000592-7C for importer@patchew.org; Mon, 05 Mar 2018 00:19:03 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33886) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1esiUp-00044U-L6 for qemu-devel@nongnu.org; Mon, 05 Mar 2018 00:17:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1esiUm-0006tY-EX for qemu-devel@nongnu.org; Mon, 05 Mar 2018 00:17:11 -0500 Received: from mx3-rdu2.redhat.com ([66.187.233.73]:51606 helo=mx1.redhat.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1esiUm-0006sB-AE; Mon, 05 Mar 2018 00:17:08 -0500 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 6E97140FB65B; Mon, 5 Mar 2018 05:17:05 +0000 (UTC) Received: from thh440s.redhat.com (ovpn-116-103.ams2.redhat.com [10.36.116.103]) by smtp.corp.redhat.com (Postfix) with ESMTP id C208B111DCE7; Mon, 5 Mar 2018 05:16:59 +0000 (UTC) From: Thomas Huth To: Cornelia Huck , qemu-devel@nongnu.org Date: Mon, 5 Mar 2018 06:16:58 +0100 Message-Id: <1520227018-4061-1-git-send-email-thuth@redhat.com> X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.7]); Mon, 05 Mar 2018 05:17:05 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.7]); Mon, 05 Mar 2018 05:17:05 +0000 (UTC) for IP:'10.11.54.3' DOMAIN:'int-mx03.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'thuth@redhat.com' RCPT:'' X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.187.233.73 Subject: [Qemu-devel] [PATCH] target/s390x: Remove leading underscores from #defines X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-s390x@nongnu.org, Richard Henderson , David Hildenbrand Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We should not use leading underscores followed by a capital letter in #defines since such identifiers are reserved by the C standard. For ASCE_ORIGIN, REGION_ENTRY_ORIGIN and SEGMENT_ENTRY_ORIGIN I also added parentheses around the value to silence an error message from checkpatch.pl. Signed-off-by: Thomas Huth Reviewed-by: David Hildenbrand --- target/s390x/cpu.h | 66 +++++++++++++++++++++++--------------------= ---- target/s390x/mem_helper.c | 20 +++++++------- target/s390x/mmu_helper.c | 54 +++++++++++++++++++------------------- 3 files changed, 70 insertions(+), 70 deletions(-) diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index c5ef930..5f357a4e 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -538,39 +538,39 @@ typedef union SysIB { QEMU_BUILD_BUG_ON(sizeof(SysIB) !=3D 4096); =20 /* MMU defines */ -#define _ASCE_ORIGIN ~0xfffULL /* segment table origin = */ -#define _ASCE_SUBSPACE 0x200 /* subspace group control = */ -#define _ASCE_PRIVATE_SPACE 0x100 /* private space control = */ -#define _ASCE_ALT_EVENT 0x80 /* storage alteration event cont= rol */ -#define _ASCE_SPACE_SWITCH 0x40 /* space switch event = */ -#define _ASCE_REAL_SPACE 0x20 /* real space control = */ -#define _ASCE_TYPE_MASK 0x0c /* asce table type mask = */ -#define _ASCE_TYPE_REGION1 0x0c /* region first table type = */ -#define _ASCE_TYPE_REGION2 0x08 /* region second table type = */ -#define _ASCE_TYPE_REGION3 0x04 /* region third table type = */ -#define _ASCE_TYPE_SEGMENT 0x00 /* segment table type = */ -#define _ASCE_TABLE_LENGTH 0x03 /* region table length = */ - -#define _REGION_ENTRY_ORIGIN ~0xfffULL /* region/segment table origin = */ -#define _REGION_ENTRY_RO 0x200 /* region/segment protection bit= */ -#define _REGION_ENTRY_TF 0xc0 /* region/segment table offset = */ -#define _REGION_ENTRY_INV 0x20 /* invalid region table entry = */ -#define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mas= k */ -#define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type = */ -#define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type = */ -#define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type = */ -#define _REGION_ENTRY_LENGTH 0x03 /* region third length = */ - -#define _SEGMENT_ENTRY_ORIGIN ~0x7ffULL /* segment table origin = */ -#define _SEGMENT_ENTRY_FC 0x400 /* format control = */ -#define _SEGMENT_ENTRY_RO 0x200 /* page protection bit = */ -#define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry = */ - -#define VADDR_PX 0xff000 /* page index bits = */ - -#define _PAGE_RO 0x200 /* HW read-only bit */ -#define _PAGE_INVALID 0x400 /* HW invalid bit */ -#define _PAGE_RES0 0x800 /* bit must be zero */ +#define ASCE_ORIGIN (~0xfffULL) /* segment table origin = */ +#define ASCE_SUBSPACE 0x200 /* subspace group control = */ +#define ASCE_PRIVATE_SPACE 0x100 /* private space control = */ +#define ASCE_ALT_EVENT 0x80 /* storage alteration event cont= rol */ +#define ASCE_SPACE_SWITCH 0x40 /* space switch event = */ +#define ASCE_REAL_SPACE 0x20 /* real space control = */ +#define ASCE_TYPE_MASK 0x0c /* asce table type mask = */ +#define ASCE_TYPE_REGION1 0x0c /* region first table type = */ +#define ASCE_TYPE_REGION2 0x08 /* region second table type = */ +#define ASCE_TYPE_REGION3 0x04 /* region third table type = */ +#define ASCE_TYPE_SEGMENT 0x00 /* segment table type = */ +#define ASCE_TABLE_LENGTH 0x03 /* region table length = */ + +#define REGION_ENTRY_ORIGIN (~0xfffULL) /* region/segment table origin = */ +#define REGION_ENTRY_RO 0x200 /* region/segment protection bit= */ +#define REGION_ENTRY_TF 0xc0 /* region/segment table offset = */ +#define REGION_ENTRY_INV 0x20 /* invalid region table entry = */ +#define REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mas= k */ +#define REGION_ENTRY_TYPE_R1 0x0c /* region first table type = */ +#define REGION_ENTRY_TYPE_R2 0x08 /* region second table type = */ +#define REGION_ENTRY_TYPE_R3 0x04 /* region third table type = */ +#define REGION_ENTRY_LENGTH 0x03 /* region third length = */ + +#define SEGMENT_ENTRY_ORIGIN (~0x7ffULL) /* segment table origin */ +#define SEGMENT_ENTRY_FC 0x400 /* format control */ +#define SEGMENT_ENTRY_RO 0x200 /* page protection bit */ +#define SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */ + +#define VADDR_PX 0xff000 /* page index bits */ + +#define PAGE_RO 0x200 /* HW read-only bit */ +#define PAGE_INVALID 0x400 /* HW invalid bit */ +#define PAGE_RES0 0x800 /* bit must be zero */ =20 #define SK_C (0x1 << 1) #define SK_R (0x1 << 2) diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index d5291b2..a0e28bd 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -1924,20 +1924,20 @@ void HELPER(idte)(CPUS390XState *env, uint64_t r1, = uint64_t r2, uint32_t m4) =20 if (!(r2 & 0x800)) { /* invalidation-and-clearing operation */ - table =3D r1 & _ASCE_ORIGIN; + table =3D r1 & ASCE_ORIGIN; entries =3D (r2 & 0x7ff) + 1; =20 - switch (r1 & _ASCE_TYPE_MASK) { - case _ASCE_TYPE_REGION1: + switch (r1 & ASCE_TYPE_MASK) { + case ASCE_TYPE_REGION1: index =3D (r2 >> 53) & 0x7ff; break; - case _ASCE_TYPE_REGION2: + case ASCE_TYPE_REGION2: index =3D (r2 >> 42) & 0x7ff; break; - case _ASCE_TYPE_REGION3: + case ASCE_TYPE_REGION3: index =3D (r2 >> 31) & 0x7ff; break; - case _ASCE_TYPE_SEGMENT: + case ASCE_TYPE_SEGMENT: index =3D (r2 >> 20) & 0x7ff; break; } @@ -1945,9 +1945,9 @@ void HELPER(idte)(CPUS390XState *env, uint64_t r1, ui= nt64_t r2, uint32_t m4) /* addresses are not wrapped in 24/31bit mode but table index = is */ raddr =3D table + ((index + i) & 0x7ff) * sizeof(entry); entry =3D cpu_ldq_real_ra(env, raddr, ra); - if (!(entry & _REGION_ENTRY_INV)) { + if (!(entry & REGION_ENTRY_INV)) { /* we are allowed to not store if already invalid */ - entry |=3D _REGION_ENTRY_INV; + entry |=3D REGION_ENTRY_INV; cpu_stq_real_ra(env, raddr, entry, ra); } } @@ -1971,12 +1971,12 @@ void HELPER(ipte)(CPUS390XState *env, uint64_t pto,= uint64_t vaddr, uint64_t pte_addr, pte; =20 /* Compute the page table entry address */ - pte_addr =3D (pto & _SEGMENT_ENTRY_ORIGIN); + pte_addr =3D (pto & SEGMENT_ENTRY_ORIGIN); pte_addr +=3D (vaddr & VADDR_PX) >> 9; =20 /* Mark the page table entry as invalid */ pte =3D cpu_ldq_real_ra(env, pte_addr, ra); - pte |=3D _PAGE_INVALID; + pte |=3D PAGE_INVALID; cpu_stq_real_ra(env, pte_addr, pte, ra); =20 /* XXX we exploit the fact that Linux passes the exact virtual diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c index 23fb2e7..1deeb6e 100644 --- a/target/s390x/mmu_helper.c +++ b/target/s390x/mmu_helper.c @@ -128,11 +128,11 @@ static bool lowprot_enabled(const CPUS390XState *env,= uint64_t asc) /* Check the private-space control bit */ switch (asc) { case PSW_ASC_PRIMARY: - return !(env->cregs[1] & _ASCE_PRIVATE_SPACE); + return !(env->cregs[1] & ASCE_PRIVATE_SPACE); case PSW_ASC_SECONDARY: - return !(env->cregs[7] & _ASCE_PRIVATE_SPACE); + return !(env->cregs[7] & ASCE_PRIVATE_SPACE); case PSW_ASC_HOME: - return !(env->cregs[13] & _ASCE_PRIVATE_SPACE); + return !(env->cregs[13] & ASCE_PRIVATE_SPACE); default: /* We don't support access register mode */ error_report("unsupported addressing mode"); @@ -159,20 +159,20 @@ static int mmu_translate_pte(CPUS390XState *env, targ= et_ulong vaddr, uint64_t asc, uint64_t pt_entry, target_ulong *raddr, int *flags, int rw, bool= exc) { - if (pt_entry & _PAGE_INVALID) { + if (pt_entry & PAGE_INVALID) { DPRINTF("%s: PTE=3D0x%" PRIx64 " invalid\n", __func__, pt_entry); trigger_page_fault(env, vaddr, PGM_PAGE_TRANS, asc, rw, exc); return -1; } - if (pt_entry & _PAGE_RES0) { + if (pt_entry & PAGE_RES0) { trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw, exc); return -1; } - if (pt_entry & _PAGE_RO) { + if (pt_entry & PAGE_RO) { *flags &=3D ~PAGE_WRITE; } =20 - *raddr =3D pt_entry & _ASCE_ORIGIN; + *raddr =3D pt_entry & ASCE_ORIGIN; =20 PTE_DPRINTF("%s: PTE=3D0x%" PRIx64 "\n", __func__, pt_entry); =20 @@ -188,11 +188,11 @@ static int mmu_translate_segment(CPUS390XState *env, = target_ulong vaddr, CPUState *cs =3D CPU(s390_env_get_cpu(env)); uint64_t origin, offs, pt_entry; =20 - if (st_entry & _SEGMENT_ENTRY_RO) { + if (st_entry & SEGMENT_ENTRY_RO) { *flags &=3D ~PAGE_WRITE; } =20 - if ((st_entry & _SEGMENT_ENTRY_FC) && (env->cregs[0] & CR0_EDAT)) { + if ((st_entry & SEGMENT_ENTRY_FC) && (env->cregs[0] & CR0_EDAT)) { /* Decode EDAT1 segment frame absolute address (1MB page) */ *raddr =3D (st_entry & 0xfffffffffff00000ULL) | (vaddr & 0xfffff); PTE_DPRINTF("%s: SEG=3D0x%" PRIx64 "\n", __func__, st_entry); @@ -200,7 +200,7 @@ static int mmu_translate_segment(CPUS390XState *env, ta= rget_ulong vaddr, } =20 /* Look up 4KB page entry */ - origin =3D st_entry & _SEGMENT_ENTRY_ORIGIN; + origin =3D st_entry & SEGMENT_ENTRY_ORIGIN; offs =3D (vaddr & VADDR_PX) >> 9; pt_entry =3D ldq_phys(cs->as, origin + offs); PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " =3D> 0x%016" PRIx64 "\n= ", @@ -223,39 +223,39 @@ static int mmu_translate_region(CPUS390XState *env, t= arget_ulong vaddr, =20 PTE_DPRINTF("%s: 0x%" PRIx64 "\n", __func__, entry); =20 - origin =3D entry & _REGION_ENTRY_ORIGIN; + origin =3D entry & REGION_ENTRY_ORIGIN; offs =3D (vaddr >> (17 + 11 * level / 4)) & 0x3ff8; =20 new_entry =3D ldq_phys(cs->as, origin + offs); PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " =3D> 0x%016" PRIx64 "\n= ", __func__, origin, offs, new_entry); =20 - if ((new_entry & _REGION_ENTRY_INV) !=3D 0) { + if ((new_entry & REGION_ENTRY_INV) !=3D 0) { DPRINTF("%s: invalid region\n", __func__); trigger_page_fault(env, vaddr, pchks[level / 4], asc, rw, exc); return -1; } =20 - if ((new_entry & _REGION_ENTRY_TYPE_MASK) !=3D level) { + if ((new_entry & REGION_ENTRY_TYPE_MASK) !=3D level) { trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw, exc); return -1; } =20 - if (level =3D=3D _ASCE_TYPE_SEGMENT) { + if (level =3D=3D ASCE_TYPE_SEGMENT) { return mmu_translate_segment(env, vaddr, asc, new_entry, raddr, fl= ags, rw, exc); } =20 /* Check region table offset and length */ offs =3D (vaddr >> (28 + 11 * (level - 4) / 4)) & 3; - if (offs < ((new_entry & _REGION_ENTRY_TF) >> 6) - || offs > (new_entry & _REGION_ENTRY_LENGTH)) { + if (offs < ((new_entry & REGION_ENTRY_TF) >> 6) + || offs > (new_entry & REGION_ENTRY_LENGTH)) { DPRINTF("%s: invalid offset or len (%lx)\n", __func__, new_entry); trigger_page_fault(env, vaddr, pchks[level / 4 - 1], asc, rw, exc); return -1; } =20 - if ((env->cregs[0] & CR0_EDAT) && (new_entry & _REGION_ENTRY_RO)) { + if ((env->cregs[0] & CR0_EDAT) && (new_entry & REGION_ENTRY_RO)) { *flags &=3D ~PAGE_WRITE; } =20 @@ -271,52 +271,52 @@ static int mmu_translate_asce(CPUS390XState *env, tar= get_ulong vaddr, int level; int r; =20 - if (asce & _ASCE_REAL_SPACE) { + if (asce & ASCE_REAL_SPACE) { /* direct mapping */ *raddr =3D vaddr; return 0; } =20 - level =3D asce & _ASCE_TYPE_MASK; + level =3D asce & ASCE_TYPE_MASK; switch (level) { - case _ASCE_TYPE_REGION1: - if ((vaddr >> 62) > (asce & _ASCE_TABLE_LENGTH)) { + case ASCE_TYPE_REGION1: + if ((vaddr >> 62) > (asce & ASCE_TABLE_LENGTH)) { trigger_page_fault(env, vaddr, PGM_REG_FIRST_TRANS, asc, rw, e= xc); return -1; } break; - case _ASCE_TYPE_REGION2: + case ASCE_TYPE_REGION2: if (vaddr & 0xffe0000000000000ULL) { DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64 " 0xffe0000000000000ULL\n", __func__, vaddr); trigger_page_fault(env, vaddr, PGM_ASCE_TYPE, asc, rw, exc); return -1; } - if ((vaddr >> 51 & 3) > (asce & _ASCE_TABLE_LENGTH)) { + if ((vaddr >> 51 & 3) > (asce & ASCE_TABLE_LENGTH)) { trigger_page_fault(env, vaddr, PGM_REG_SEC_TRANS, asc, rw, exc= ); return -1; } break; - case _ASCE_TYPE_REGION3: + case ASCE_TYPE_REGION3: if (vaddr & 0xfffffc0000000000ULL) { DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64 " 0xfffffc0000000000ULL\n", __func__, vaddr); trigger_page_fault(env, vaddr, PGM_ASCE_TYPE, asc, rw, exc); return -1; } - if ((vaddr >> 40 & 3) > (asce & _ASCE_TABLE_LENGTH)) { + if ((vaddr >> 40 & 3) > (asce & ASCE_TABLE_LENGTH)) { trigger_page_fault(env, vaddr, PGM_REG_THIRD_TRANS, asc, rw, e= xc); return -1; } break; - case _ASCE_TYPE_SEGMENT: + case ASCE_TYPE_SEGMENT: if (vaddr & 0xffffffff80000000ULL) { DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64 " 0xffffffff80000000ULL\n", __func__, vaddr); trigger_page_fault(env, vaddr, PGM_ASCE_TYPE, asc, rw, exc); return -1; } - if ((vaddr >> 29 & 3) > (asce & _ASCE_TABLE_LENGTH)) { + if ((vaddr >> 29 & 3) > (asce & ASCE_TABLE_LENGTH)) { trigger_page_fault(env, vaddr, PGM_SEGMENT_TRANS, asc, rw, exc= ); return -1; } --=20 1.8.3.1