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[125.237.39.90]) by smtp.gmail.com with ESMTPSA id g16sm14046966pfd.23.2018.03.02.05.54.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 02 Mar 2018 05:54:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=clutPHMFxadYvpqFv+YAe4hpDgmGtr2bLv0tu1fg19U=; b=ODw0jCETXrFAThjPznLkvhHbY15/zGAsz/it+nlTEjEQIdR1gfzWMeR0Ktdn0WAYQU Z6AXTsuQLZpfRPxfPMR5XM1WS6nUd4IuWZuQJAWMCpuvyKai1XanO0bJfIoUM+MkT65y vRJdDnElOM7pDLE+q51aLbJQlhypEmjU2qtUPi0zZm/gBG4GDxjuSlTj/xa73Yc9vYC6 dhi5DrA1uzhBRvenkv/ccdK/oplYQf5t5dDApCHPWdXM0d5Je+EUiPhU+ot1KTsAF98w V0j4CY0iBfgmdzUsCxJq75BLNgzPIgNw7FL7mZIp7lcSZgbJCGqSZhOEKqouYp3z/Xnw J0aA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=clutPHMFxadYvpqFv+YAe4hpDgmGtr2bLv0tu1fg19U=; b=JyKiVE+a0TAWUOLPOwsIIX6fFjnmdg3YeA8tiK4gElCH+7S27JQ6hZjXO/tS82XEW3 D3pqimvcDtEYhINO7QivRN1dc79hJZmvoUFYJpO2FkuZ1psVnlhd5Wlky46GkorNoB1X d5Wf49GACKFU3iq4q6DA0t4GMXlzyE4sj7OwDqqMTe6SVG2uipalDfxjsf5gKkC2i9ST HIARHDn6vQx7CbfE4u82bpZpIz6tTWHExweCmIaZJA9ypGAMefl3dCFBjNuf0CFSxvj4 IRJ2vReITuJEXJgzevtlslGAF1cMYLQKBn8IUTQzAbsMYTcVBpDcQ0q6Wb2L5z3wJ0X0 wNSQ== X-Gm-Message-State: APf1xPDG0LnG7z5F3DfVOS6JEmlgaMsecv1frp69pYrvnAJoJ3FhXjWs wfQMHblCvmE75lnXJo0XhX20QEgrVYs= X-Google-Smtp-Source: AG47ELtQON/I9IgVrineMeEFR8F9S6F8Kq85xQoYhpGIdCTmhUlz4g0N4BdrH4fVAR0lfJxX9hfRLw== X-Received: by 2002:a17:902:57c1:: with SMTP id g1-v6mr5340755plj.381.1519998865348; Fri, 02 Mar 2018 05:54:25 -0800 (PST) From: Michael Clark To: qemu-devel@nongnu.org Date: Sat, 3 Mar 2018 02:51:50 +1300 Message-Id: <1519998711-73430-23-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1519998711-73430-1-git-send-email-mjc@sifive.com> References: <1519998711-73430-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PATCH v8 22/23] SiFive Freedom U Series RISC-V Machine X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Michael Clark , Palmer Dabbelt , Sagar Karandikar , RISC-V Patches Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This provides a RISC-V Board compatible with the the SiFive Freedom U SDK. The following machine is implemented: - 'sifive_u'; CLINT, PLIC, UART, device-tree Acked-by: Richard Henderson Signed-off-by: Sagar Karandikar Signed-off-by: Palmer Dabbelt Signed-off-by: Michael Clark --- hw/riscv/sifive_u.c | 339 ++++++++++++++++++++++++++++++++++++++++= ++++ include/hw/riscv/sifive_u.h | 69 +++++++++ 2 files changed, 408 insertions(+) create mode 100644 hw/riscv/sifive_u.c create mode 100644 include/hw/riscv/sifive_u.h diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c new file mode 100644 index 0000000..1c2deef --- /dev/null +++ b/hw/riscv/sifive_u.c @@ -0,0 +1,339 @@ +/* + * QEMU RISC-V Board Compatible with SiFive Freedom U SDK + * + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * Copyright (c) 2017 SiFive, Inc. + * + * Provides a board compatible with the SiFive Freedom U SDK: + * + * 0) UART + * 1) CLINT (Core Level Interruptor) + * 2) PLIC (Platform Level Interrupt Controller) + * + * This board currently uses a hardcoded devicetree that indicates one har= t. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/error-report.h" +#include "qapi/error.h" +#include "hw/hw.h" +#include "hw/boards.h" +#include "hw/loader.h" +#include "hw/sysbus.h" +#include "hw/char/serial.h" +#include "target/riscv/cpu.h" +#include "hw/riscv/riscv_hart.h" +#include "hw/riscv/sifive_plic.h" +#include "hw/riscv/sifive_clint.h" +#include "hw/riscv/sifive_uart.h" +#include "hw/riscv/sifive_prci.h" +#include "hw/riscv/sifive_u.h" +#include "chardev/char.h" +#include "sysemu/arch_init.h" +#include "sysemu/device_tree.h" +#include "exec/address-spaces.h" +#include "elf.h" + +static const struct MemmapEntry { + hwaddr base; + hwaddr size; +} sifive_u_memmap[] =3D { + [SIFIVE_U_DEBUG] =3D { 0x0, 0x100 }, + [SIFIVE_U_MROM] =3D { 0x1000, 0x2000 }, + [SIFIVE_U_CLINT] =3D { 0x2000000, 0x10000 }, + [SIFIVE_U_PLIC] =3D { 0xc000000, 0x4000000 }, + [SIFIVE_U_UART0] =3D { 0x10013000, 0x1000 }, + [SIFIVE_U_UART1] =3D { 0x10023000, 0x1000 }, + [SIFIVE_U_DRAM] =3D { 0x80000000, 0x0 }, +}; + +static void copy_le32_to_phys(hwaddr pa, uint32_t *rom, size_t len) +{ + int i; + for (i =3D 0; i < (len >> 2); i++) { + stl_phys(&address_space_memory, pa + (i << 2), rom[i]); + } +} + +static uint64_t identity_translate(void *opaque, uint64_t addr) +{ + return addr; +} + +static uint64_t load_kernel(const char *kernel_filename) +{ + uint64_t kernel_entry, kernel_high; + + if (load_elf(kernel_filename, identity_translate, NULL, + &kernel_entry, NULL, &kernel_high, + 0, ELF_MACHINE, 1, 0) < 0) { + error_report("qemu: could not load kernel '%s'", kernel_filename); + exit(1); + } + return kernel_entry; +} + +static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, + uint64_t mem_size, const char *cmdline) +{ + void *fdt; + int cpu; + uint32_t *cells; + char *nodename; + uint32_t plic_phandle; + + fdt =3D s->fdt =3D create_device_tree(&s->fdt_size); + if (!fdt) { + error_report("create_device_tree() failed"); + exit(1); + } + + qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu"); + qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev= "); + qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); + qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); + + qemu_fdt_add_subnode(fdt, "/soc"); + qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); + qemu_fdt_setprop_string(fdt, "/soc", "compatible", "ucbbar,spike-bare-= soc"); + qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); + qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); + + nodename =3D g_strdup_printf("/memory@%lx", + (long)memmap[SIFIVE_U_DRAM].base); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_cells(fdt, nodename, "reg", + memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base, + mem_size >> 32, mem_size); + qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); + g_free(nodename); + + qemu_fdt_add_subnode(fdt, "/cpus"); + qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 10000000); + qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); + qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); + + for (cpu =3D s->soc.num_harts - 1; cpu >=3D 0; cpu--) { + nodename =3D g_strdup_printf("/cpus/cpu@%d", cpu); + char *intc =3D g_strdup_printf("/cpus/cpu@%d/interrupt-controller"= , cpu); + char *isa =3D riscv_isa_string(&s->soc.harts[cpu]); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 1000000000= ); + qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); + qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); + qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); + qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); + qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); + qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); + qemu_fdt_add_subnode(fdt, intc); + qemu_fdt_setprop_cell(fdt, intc, "phandle", 1); + qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", 1); + qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); + qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); + qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); + g_free(isa); + g_free(intc); + g_free(nodename); + } + + cells =3D g_new0(uint32_t, s->soc.num_harts * 4); + for (cpu =3D 0; cpu < s->soc.num_harts; cpu++) { + nodename =3D + g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); + uint32_t intc_phandle =3D qemu_fdt_get_phandle(fdt, nodename); + cells[cpu * 4 + 0] =3D cpu_to_be32(intc_phandle); + cells[cpu * 4 + 1] =3D cpu_to_be32(IRQ_M_SOFT); + cells[cpu * 4 + 2] =3D cpu_to_be32(intc_phandle); + cells[cpu * 4 + 3] =3D cpu_to_be32(IRQ_M_TIMER); + g_free(nodename); + } + nodename =3D g_strdup_printf("/soc/clint@%lx", + (long)memmap[SIFIVE_U_CLINT].base); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0"); + qemu_fdt_setprop_cells(fdt, nodename, "reg", + 0x0, memmap[SIFIVE_U_CLINT].base, + 0x0, memmap[SIFIVE_U_CLINT].size); + qemu_fdt_setprop(fdt, nodename, "interrupts-extended", + cells, s->soc.num_harts * sizeof(uint32_t) * 4); + g_free(cells); + g_free(nodename); + + cells =3D g_new0(uint32_t, s->soc.num_harts * 4); + for (cpu =3D 0; cpu < s->soc.num_harts; cpu++) { + nodename =3D + g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); + uint32_t intc_phandle =3D qemu_fdt_get_phandle(fdt, nodename); + cells[cpu * 4 + 0] =3D cpu_to_be32(intc_phandle); + cells[cpu * 4 + 1] =3D cpu_to_be32(IRQ_M_EXT); + cells[cpu * 4 + 2] =3D cpu_to_be32(intc_phandle); + cells[cpu * 4 + 3] =3D cpu_to_be32(IRQ_S_EXT); + g_free(nodename); + } + nodename =3D g_strdup_printf("/soc/interrupt-controller@%lx", + (long)memmap[SIFIVE_U_PLIC].base); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1); + qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0"); + qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); + qemu_fdt_setprop(fdt, nodename, "interrupts-extended", + cells, s->soc.num_harts * sizeof(uint32_t) * 4); + qemu_fdt_setprop_cells(fdt, nodename, "reg", + 0x0, memmap[SIFIVE_U_PLIC].base, + 0x0, memmap[SIFIVE_U_PLIC].size); + qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); + qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7); + qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 4); + qemu_fdt_setprop_cells(fdt, nodename, "phandle", 2); + qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", 2); + plic_phandle =3D qemu_fdt_get_phandle(fdt, nodename); + g_free(cells); + g_free(nodename); + + nodename =3D g_strdup_printf("/uart@%lx", + (long)memmap[SIFIVE_U_UART0].base); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); + qemu_fdt_setprop_cells(fdt, nodename, "reg", + 0x0, memmap[SIFIVE_U_UART0].base, + 0x0, memmap[SIFIVE_U_UART0].size); + qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle= ); + qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 1); + + qemu_fdt_add_subnode(fdt, "/chosen"); + qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); + qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); + g_free(nodename); +} + +static void riscv_sifive_u_init(MachineState *machine) +{ + const struct MemmapEntry *memmap =3D sifive_u_memmap; + + SiFiveUState *s =3D g_new0(SiFiveUState, 1); + MemoryRegion *sys_memory =3D get_system_memory(); + MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); + MemoryRegion *boot_rom =3D g_new(MemoryRegion, 1); + + /* Initialize SOC */ + object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY); + object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc), + &error_abort); + object_property_set_str(OBJECT(&s->soc), SIFIVE_U_CPU, "cpu-type", + &error_abort); + object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts", + &error_abort); + object_property_set_bool(OBJECT(&s->soc), true, "realized", + &error_abort); + + /* register RAM */ + memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram", + machine->ram_size, &error_fatal); + memory_region_add_subregion(sys_memory, memmap[SIFIVE_U_DRAM].base, + main_mem); + + /* create device tree */ + create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); + + /* boot rom */ + memory_region_init_ram(boot_rom, NULL, "riscv.sifive.u.mrom", + memmap[SIFIVE_U_MROM].base, &error_fatal); + memory_region_set_readonly(boot_rom, true); + memory_region_add_subregion(sys_memory, 0x0, boot_rom); + + if (machine->kernel_filename) { + load_kernel(machine->kernel_filename); + } + + /* reset vector */ + uint32_t reset_vec[8] =3D { + 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ + 0x02028593, /* addi a1, t0, %pcrel_lo(1b)= */ + 0xf1402573, /* csrr a0, mhartid */ +#if defined(TARGET_RISCV32) + 0x0182a283, /* lw t0, 24(t0) */ +#elif defined(TARGET_RISCV64) + 0x0182b283, /* ld t0, 24(t0) */ +#endif + 0x00028067, /* jr t0 */ + 0x00000000, + memmap[SIFIVE_U_DRAM].base, /* start: .dword DRAM_BASE */ + 0x00000000, + /* dtb: */ + }; + + /* copy in the reset vector */ + copy_le32_to_phys(memmap[SIFIVE_U_MROM].base, reset_vec, sizeof(reset_= vec)); + + /* copy in the device tree */ + qemu_fdt_dumpdtb(s->fdt, s->fdt_size); + cpu_physical_memory_write(memmap[SIFIVE_U_MROM].base + + sizeof(reset_vec), s->fdt, s->fdt_size); + + /* MMIO */ + s->plic =3D sifive_plic_create(memmap[SIFIVE_U_PLIC].base, + (char *)SIFIVE_U_PLIC_HART_CONFIG, + SIFIVE_U_PLIC_NUM_SOURCES, + SIFIVE_U_PLIC_NUM_PRIORITIES, + SIFIVE_U_PLIC_PRIORITY_BASE, + SIFIVE_U_PLIC_PENDING_BASE, + SIFIVE_U_PLIC_ENABLE_BASE, + SIFIVE_U_PLIC_ENABLE_STRIDE, + SIFIVE_U_PLIC_CONTEXT_BASE, + SIFIVE_U_PLIC_CONTEXT_STRIDE, + memmap[SIFIVE_U_PLIC].size); + sifive_uart_create(sys_memory, memmap[SIFIVE_U_UART0].base, + serial_hds[0], SIFIVE_PLIC(s->plic)->irqs[SIFIVE_U_UART0_IRQ]); + /* sifive_uart_create(sys_memory, memmap[SIFIVE_U_UART1].base, + serial_hds[1], SIFIVE_PLIC(s->plic)->irqs[SIFIVE_U_UART1_IRQ]); */ + sifive_clint_create(memmap[SIFIVE_U_CLINT].base, + memmap[SIFIVE_U_CLINT].size, smp_cpus, + SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); +} + +static int riscv_sifive_u_sysbus_device_init(SysBusDevice *sysbusdev) +{ + return 0; +} + +static void riscv_sifive_u_class_init(ObjectClass *klass, void *data) +{ + SysBusDeviceClass *k =3D SYS_BUS_DEVICE_CLASS(klass); + k->init =3D riscv_sifive_u_sysbus_device_init; +} + +static const TypeInfo riscv_sifive_u_device =3D { + .name =3D TYPE_SIFIVE_U, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(SiFiveUState), + .class_init =3D riscv_sifive_u_class_init, +}; + +static void riscv_sifive_u_register_types(void) +{ + type_register_static(&riscv_sifive_u_device); +} + +type_init(riscv_sifive_u_register_types); + +static void riscv_sifive_u_machine_init(MachineClass *mc) +{ + mc->desc =3D "RISC-V Board compatible with SiFive U SDK"; + mc->init =3D riscv_sifive_u_init; + mc->max_cpus =3D 1; +} + +DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init) diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h new file mode 100644 index 0000000..662e8a1 --- /dev/null +++ b/include/hw/riscv/sifive_u.h @@ -0,0 +1,69 @@ +/* + * SiFive U series machine interface + * + * Copyright (c) 2017 SiFive, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#ifndef HW_SIFIVE_U_H +#define HW_SIFIVE_U_H + +#define TYPE_SIFIVE_U "riscv.sifive_u" + +#define SIFIVE_U(obj) \ + OBJECT_CHECK(SiFiveUState, (obj), TYPE_SIFIVE_U) + +typedef struct SiFiveUState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + RISCVHartArrayState soc; + DeviceState *plic; + void *fdt; + int fdt_size; +} SiFiveUState; + +enum { + SIFIVE_U_DEBUG, + SIFIVE_U_MROM, + SIFIVE_U_CLINT, + SIFIVE_U_PLIC, + SIFIVE_U_UART0, + SIFIVE_U_UART1, + SIFIVE_U_DRAM +}; + +enum { + SIFIVE_U_UART0_IRQ =3D 3, + SIFIVE_U_UART1_IRQ =3D 4 +}; + +#define SIFIVE_U_PLIC_HART_CONFIG "MS" +#define SIFIVE_U_PLIC_NUM_SOURCES 127 +#define SIFIVE_U_PLIC_NUM_PRIORITIES 7 +#define SIFIVE_U_PLIC_PRIORITY_BASE 0x0 +#define SIFIVE_U_PLIC_PENDING_BASE 0x1000 +#define SIFIVE_U_PLIC_ENABLE_BASE 0x2000 +#define SIFIVE_U_PLIC_ENABLE_STRIDE 0x80 +#define SIFIVE_U_PLIC_CONTEXT_BASE 0x200000 +#define SIFIVE_U_PLIC_CONTEXT_STRIDE 0x1000 + +#if defined(TARGET_RISCV32) +#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34 +#elif defined(TARGET_RISCV64) +#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54 +#endif + +#endif --=20 2.7.0