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Processed in 0.110572 secs); 28 Feb 2018 11:01:57 -0000 From: Abdallah Bouassida To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Wed, 28 Feb 2018 12:01:23 +0100 Message-Id: <1519815685-29200-3-git-send-email-abdallah.bouassida@lauterbach.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1519815685-29200-1-git-send-email-abdallah.bouassida@lauterbach.com> References: <1519815685-29200-1-git-send-email-abdallah.bouassida@lauterbach.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 62.154.241.196 Subject: [Qemu-devel] [PATCH v3 2/4] target/arm: Add "_S" suffix to the secure version of a sysreg X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: khaled.jmal@lauterbach.com, qemu-arm@nongnu.org, Abdallah Bouassida Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is a preparation for the coming feature of creating dynamically an XML description for the ARM sysregs. Add "_S" suffix to the secure version of sysregs that have both S and NS vi= ews Replace (S) and (NS) by _S and _NS for the register that are manually defin= ed, so all the registers follow the same convention. Signed-off-by: Abdallah Bouassida --- target/arm/helper.c | 31 ++++++++++++++++++++----------- 1 file changed, 20 insertions(+), 11 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index bdd212f..1594ec45 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -694,12 +694,12 @@ static const ARMCPRegInfo cp_reginfo[] =3D { * the secure register to be properly reset and migrated. There is als= o no * v8 EL1 version of the register so the non-secure instance stands al= one. */ - { .name =3D "FCSEIDR(NS)", + { .name =3D "FCSEIDR_NS", .cp =3D 15, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .secure =3D ARM_CP_SECSTATE_NS, .fieldoffset =3D offsetof(CPUARMState, cp15.fcseidr_ns), .resetvalue =3D 0, .writefn =3D fcse_write, .raw_writefn =3D raw_wri= te, }, - { .name =3D "FCSEIDR(S)", + { .name =3D "FCSEIDR_S", .cp =3D 15, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .secure =3D ARM_CP_SECSTATE_S, .fieldoffset =3D offsetof(CPUARMState, cp15.fcseidr_s), @@ -715,7 +715,7 @@ static const ARMCPRegInfo cp_reginfo[] =3D { .access =3D PL1_RW, .secure =3D ARM_CP_SECSTATE_NS, .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_el[1]), .resetvalue =3D 0, .writefn =3D contextidr_write, .raw_writefn =3D r= aw_write, }, - { .name =3D "CONTEXTIDR(S)", .state =3D ARM_CP_STATE_AA32, + { .name =3D "CONTEXTIDR_S", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 1, .access =3D PL1_RW, .secure =3D ARM_CP_SECSTATE_S, .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_s), @@ -1966,7 +1966,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { cp15.c14_timer[GTIMER_PHYS].ctl), .writefn =3D gt_phys_ctl_write, .raw_writefn =3D raw_write, }, - { .name =3D "CNTP_CTL(S)", + { .name =3D "CNTP_CTL_S", .cp =3D 15, .crn =3D 14, .crm =3D 2, .opc1 =3D 0, .opc2 =3D 1, .secure =3D ARM_CP_SECSTATE_S, .type =3D ARM_CP_IO | ARM_CP_ALIAS, .access =3D PL1_RW | PL0_R, @@ -2005,7 +2005,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { .accessfn =3D gt_ptimer_access, .readfn =3D gt_phys_tval_read, .writefn =3D gt_phys_tval_write, }, - { .name =3D "CNTP_TVAL(S)", + { .name =3D "CNTP_TVAL_S", .cp =3D 15, .crn =3D 14, .crm =3D 2, .opc1 =3D 0, .opc2 =3D 0, .secure =3D ARM_CP_SECSTATE_S, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL1_RW | PL0_R, @@ -2059,7 +2059,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { .accessfn =3D gt_ptimer_access, .writefn =3D gt_phys_cval_write, .raw_writefn =3D raw_write, }, - { .name =3D "CNTP_CVAL(S)", .cp =3D 15, .crm =3D 14, .opc1 =3D 2, + { .name =3D "CNTP_CVAL_S", .cp =3D 15, .crm =3D 14, .opc1 =3D 2, .secure =3D ARM_CP_SECSTATE_S, .access =3D PL1_RW | PL0_R, .type =3D ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, @@ -5562,7 +5562,8 @@ CpuDefinitionInfoList *arch_query_cpu_definitions(Err= or **errp) =20 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, void *opaque, int state, int secstate, - int crm, int opc1, int opc2) + int crm, int opc1, int opc2, + const char *name) { /* Private utility function for define_one_arm_cp_reg_with_opaque(): * add a single reginfo struct to the hash table. @@ -5572,6 +5573,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, int is64 =3D (r->type & ARM_CP_64BIT) ? 1 : 0; int ns =3D (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; =20 + r2->name =3D name; /* Reset the secure state to the specific incoming state. This is * necessary as the register may have been defined with both states. */ @@ -5803,19 +5805,26 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, /* Under AArch32 CP registers can be common * (same for secure and non-secure world) or banke= d. */ + const char *name; + GString *s; + switch (r->secure) { case ARM_CP_SECSTATE_S: case ARM_CP_SECSTATE_NS: add_cpreg_to_hashtable(cpu, r, opaque, state, - r->secure, crm, opc1, o= pc2); + r->secure, crm, opc1, o= pc2, + r->name); break; default: + s =3D g_string_new(r->name); + g_string_append_printf(s, "_S"); + name =3D g_string_free(s, false); add_cpreg_to_hashtable(cpu, r, opaque, state, ARM_CP_SECSTATE_S, - crm, opc1, opc2); + crm, opc1, opc2, name); add_cpreg_to_hashtable(cpu, r, opaque, state, ARM_CP_SECSTATE_NS, - crm, opc1, opc2); + crm, opc1, opc2, r->nam= e); break; } } else { @@ -5823,7 +5832,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, * of AArch32 */ add_cpreg_to_hashtable(cpu, r, opaque, state, ARM_CP_SECSTATE_NS, - crm, opc1, opc2); + crm, opc1, opc2, r->name); } } } --=20 2.7.4