From nobody Fri Oct 24 09:57:35 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519815874440455.55197905335797; Wed, 28 Feb 2018 03:04:34 -0800 (PST) Received: from localhost ([::1]:43304 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eqzXF-0004rj-6S for importer@patchew.org; Wed, 28 Feb 2018 06:04:33 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40161) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eqzV4-0003ac-4G for qemu-devel@nongnu.org; Wed, 28 Feb 2018 06:02:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eqzUy-0007Kl-D5 for qemu-devel@nongnu.org; Wed, 28 Feb 2018 06:02:18 -0500 Received: from smtp1.lauterbach.com ([62.154.241.196]:51694) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eqzUy-0007Cp-1Y for qemu-devel@nongnu.org; Wed, 28 Feb 2018 06:02:12 -0500 Received: (qmail 994 invoked by uid 484); 28 Feb 2018 11:01:55 -0000 Received: from unknown (HELO localhost.localdomain) (Authenticated_SSL:abouassida@[41.224.44.126]) (envelope-sender ) by smtp1.lauterbach.com (qmail-ldap-1.03) with ECDHE-RSA-AES256-SHA encrypted SMTP for ; 28 Feb 2018 11:01:54 -0000 X-Qmail-Scanner-Diagnostics: from 41.224.44.126 by smtp1.lauterbach.com (envelope-from , uid 484) with qmail-scanner-2.11 (mhr: 1.0. clamdscan: 0.99/21437. spamassassin: 3.4.0. Clear:RC:1(41.224.44.126):. Processed in 0.056838 secs); 28 Feb 2018 11:01:55 -0000 From: Abdallah Bouassida To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Wed, 28 Feb 2018 12:01:22 +0100 Message-Id: <1519815685-29200-2-git-send-email-abdallah.bouassida@lauterbach.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1519815685-29200-1-git-send-email-abdallah.bouassida@lauterbach.com> References: <1519815685-29200-1-git-send-email-abdallah.bouassida@lauterbach.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 62.154.241.196 Subject: [Qemu-devel] [PATCH v3 1/4] target/arm: Add "ARM_CP_NO_GDB" as a new bit field for ARMCPRegInfo type X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: khaled.jmal@lauterbach.com, qemu-arm@nongnu.org, Abdallah Bouassida Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is a preparation for the coming feature of creating dynamically an XML description for the ARM sysregs. A register has ARM_CP_NO_GDB enabled will not be shown in the dynamic XML. This bit is enabled automatically when creating CP_ANY wildcard aliases. This bit could be enabled manually for any register we want to remove from = the dynamic XML description. Signed-off-by: Abdallah Bouassida Reviewed-by: Peter Maydell --- target/arm/cpu.h | 3 ++- target/arm/helper.c | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8c839fa..92cfe4c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1776,10 +1776,11 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpr= egid) #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA #define ARM_CP_FPU 0x1000 #define ARM_CP_SVE 0x2000 +#define ARM_CP_NO_GDB 0x4000 /* Used only as a terminator for ARMCPRegInfo lists */ #define ARM_CP_SENTINEL 0xffff /* Mask of only the flag bits in a type field */ -#define ARM_CP_FLAG_MASK 0x30ff +#define ARM_CP_FLAG_MASK 0x70ff =20 /* Valid values for ARMCPRegInfo state field, indicating which of * the AArch32 and AArch64 execution states this register is visible in. diff --git a/target/arm/helper.c b/target/arm/helper.c index c5bc69b..bdd212f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5663,7 +5663,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, if (((r->crm =3D=3D CP_ANY) && crm !=3D 0) || ((r->opc1 =3D=3D CP_ANY) && opc1 !=3D 0) || ((r->opc2 =3D=3D CP_ANY) && opc2 !=3D 0)) { - r2->type |=3D ARM_CP_ALIAS; + r2->type |=3D ARM_CP_ALIAS | ARM_CP_NO_GDB; } =20 /* Check that raw accesses are either forbidden or handled. Note that --=20 2.7.4 From nobody Fri Oct 24 09:57:35 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519815857141641.8505055308319; Wed, 28 Feb 2018 03:04:17 -0800 (PST) Received: from localhost ([::1]:43302 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eqzWx-0004bi-FS for importer@patchew.org; Wed, 28 Feb 2018 06:04:15 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40136) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eqzV2-0003aE-5B for qemu-devel@nongnu.org; Wed, 28 Feb 2018 06:02:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eqzV0-0007Lb-NA for qemu-devel@nongnu.org; Wed, 28 Feb 2018 06:02:16 -0500 Received: from smtp1.lauterbach.com ([62.154.241.196]:41065) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eqzV0-0007Df-CL for qemu-devel@nongnu.org; Wed, 28 Feb 2018 06:02:14 -0500 Received: (qmail 1032 invoked by uid 484); 28 Feb 2018 11:01:57 -0000 Received: from unknown (HELO localhost.localdomain) (Authenticated_SSL:abouassida@[41.224.44.126]) (envelope-sender ) by smtp1.lauterbach.com (qmail-ldap-1.03) with ECDHE-RSA-AES256-SHA encrypted SMTP for ; 28 Feb 2018 11:01:56 -0000 X-Qmail-Scanner-Diagnostics: from 41.224.44.126 by smtp1.lauterbach.com (envelope-from , uid 484) with qmail-scanner-2.11 (mhr: 1.0. clamdscan: 0.99/21437. spamassassin: 3.4.0. Clear:RC:1(41.224.44.126):. Processed in 0.110572 secs); 28 Feb 2018 11:01:57 -0000 From: Abdallah Bouassida To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Wed, 28 Feb 2018 12:01:23 +0100 Message-Id: <1519815685-29200-3-git-send-email-abdallah.bouassida@lauterbach.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1519815685-29200-1-git-send-email-abdallah.bouassida@lauterbach.com> References: <1519815685-29200-1-git-send-email-abdallah.bouassida@lauterbach.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 62.154.241.196 Subject: [Qemu-devel] [PATCH v3 2/4] target/arm: Add "_S" suffix to the secure version of a sysreg X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: khaled.jmal@lauterbach.com, qemu-arm@nongnu.org, Abdallah Bouassida Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is a preparation for the coming feature of creating dynamically an XML description for the ARM sysregs. Add "_S" suffix to the secure version of sysregs that have both S and NS vi= ews Replace (S) and (NS) by _S and _NS for the register that are manually defin= ed, so all the registers follow the same convention. Signed-off-by: Abdallah Bouassida --- target/arm/helper.c | 31 ++++++++++++++++++++----------- 1 file changed, 20 insertions(+), 11 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index bdd212f..1594ec45 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -694,12 +694,12 @@ static const ARMCPRegInfo cp_reginfo[] =3D { * the secure register to be properly reset and migrated. There is als= o no * v8 EL1 version of the register so the non-secure instance stands al= one. */ - { .name =3D "FCSEIDR(NS)", + { .name =3D "FCSEIDR_NS", .cp =3D 15, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .secure =3D ARM_CP_SECSTATE_NS, .fieldoffset =3D offsetof(CPUARMState, cp15.fcseidr_ns), .resetvalue =3D 0, .writefn =3D fcse_write, .raw_writefn =3D raw_wri= te, }, - { .name =3D "FCSEIDR(S)", + { .name =3D "FCSEIDR_S", .cp =3D 15, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .secure =3D ARM_CP_SECSTATE_S, .fieldoffset =3D offsetof(CPUARMState, cp15.fcseidr_s), @@ -715,7 +715,7 @@ static const ARMCPRegInfo cp_reginfo[] =3D { .access =3D PL1_RW, .secure =3D ARM_CP_SECSTATE_NS, .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_el[1]), .resetvalue =3D 0, .writefn =3D contextidr_write, .raw_writefn =3D r= aw_write, }, - { .name =3D "CONTEXTIDR(S)", .state =3D ARM_CP_STATE_AA32, + { .name =3D "CONTEXTIDR_S", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 1, .access =3D PL1_RW, .secure =3D ARM_CP_SECSTATE_S, .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_s), @@ -1966,7 +1966,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { cp15.c14_timer[GTIMER_PHYS].ctl), .writefn =3D gt_phys_ctl_write, .raw_writefn =3D raw_write, }, - { .name =3D "CNTP_CTL(S)", + { .name =3D "CNTP_CTL_S", .cp =3D 15, .crn =3D 14, .crm =3D 2, .opc1 =3D 0, .opc2 =3D 1, .secure =3D ARM_CP_SECSTATE_S, .type =3D ARM_CP_IO | ARM_CP_ALIAS, .access =3D PL1_RW | PL0_R, @@ -2005,7 +2005,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { .accessfn =3D gt_ptimer_access, .readfn =3D gt_phys_tval_read, .writefn =3D gt_phys_tval_write, }, - { .name =3D "CNTP_TVAL(S)", + { .name =3D "CNTP_TVAL_S", .cp =3D 15, .crn =3D 14, .crm =3D 2, .opc1 =3D 0, .opc2 =3D 0, .secure =3D ARM_CP_SECSTATE_S, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL1_RW | PL0_R, @@ -2059,7 +2059,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { .accessfn =3D gt_ptimer_access, .writefn =3D gt_phys_cval_write, .raw_writefn =3D raw_write, }, - { .name =3D "CNTP_CVAL(S)", .cp =3D 15, .crm =3D 14, .opc1 =3D 2, + { .name =3D "CNTP_CVAL_S", .cp =3D 15, .crm =3D 14, .opc1 =3D 2, .secure =3D ARM_CP_SECSTATE_S, .access =3D PL1_RW | PL0_R, .type =3D ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, @@ -5562,7 +5562,8 @@ CpuDefinitionInfoList *arch_query_cpu_definitions(Err= or **errp) =20 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, void *opaque, int state, int secstate, - int crm, int opc1, int opc2) + int crm, int opc1, int opc2, + const char *name) { /* Private utility function for define_one_arm_cp_reg_with_opaque(): * add a single reginfo struct to the hash table. @@ -5572,6 +5573,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, int is64 =3D (r->type & ARM_CP_64BIT) ? 1 : 0; int ns =3D (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; =20 + r2->name =3D name; /* Reset the secure state to the specific incoming state. This is * necessary as the register may have been defined with both states. */ @@ -5803,19 +5805,26 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, /* Under AArch32 CP registers can be common * (same for secure and non-secure world) or banke= d. */ + const char *name; + GString *s; + switch (r->secure) { case ARM_CP_SECSTATE_S: case ARM_CP_SECSTATE_NS: add_cpreg_to_hashtable(cpu, r, opaque, state, - r->secure, crm, opc1, o= pc2); + r->secure, crm, opc1, o= pc2, + r->name); break; default: + s =3D g_string_new(r->name); + g_string_append_printf(s, "_S"); + name =3D g_string_free(s, false); add_cpreg_to_hashtable(cpu, r, opaque, state, ARM_CP_SECSTATE_S, - crm, opc1, opc2); + crm, opc1, opc2, name); add_cpreg_to_hashtable(cpu, r, opaque, state, ARM_CP_SECSTATE_NS, - crm, opc1, opc2); + crm, opc1, opc2, r->nam= e); break; } } else { @@ -5823,7 +5832,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, * of AArch32 */ add_cpreg_to_hashtable(cpu, r, opaque, state, ARM_CP_SECSTATE_NS, - crm, opc1, opc2); + crm, opc1, opc2, r->name); } } } --=20 2.7.4 From nobody Fri Oct 24 09:57:35 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519816039768250.9937811795487; Wed, 28 Feb 2018 03:07:19 -0800 (PST) Received: from localhost ([::1]:43324 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eqzZu-0007Tc-Ey for importer@patchew.org; Wed, 28 Feb 2018 06:07:18 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40192) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eqzV7-0003cN-B6 for qemu-devel@nongnu.org; Wed, 28 Feb 2018 06:02:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eqzV2-0007Mi-PT for qemu-devel@nongnu.org; Wed, 28 Feb 2018 06:02:21 -0500 Received: from smtp1.lauterbach.com ([62.154.241.196]:50408) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eqzV2-0007ES-Av for qemu-devel@nongnu.org; Wed, 28 Feb 2018 06:02:16 -0500 Received: (qmail 1065 invoked by uid 484); 28 Feb 2018 11:01:59 -0000 Received: from unknown (HELO localhost.localdomain) (Authenticated_SSL:abouassida@[41.224.44.126]) (envelope-sender ) by smtp1.lauterbach.com (qmail-ldap-1.03) with ECDHE-RSA-AES256-SHA encrypted SMTP for ; 28 Feb 2018 11:01:58 -0000 X-Qmail-Scanner-Diagnostics: from 41.224.44.126 by smtp1.lauterbach.com (envelope-from , uid 484) with qmail-scanner-2.11 (mhr: 1.0. clamdscan: 0.99/21437. spamassassin: 3.4.0. Clear:RC:1(41.224.44.126):. Processed in 0.051834 secs); 28 Feb 2018 11:01:59 -0000 From: Abdallah Bouassida To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Wed, 28 Feb 2018 12:01:24 +0100 Message-Id: <1519815685-29200-4-git-send-email-abdallah.bouassida@lauterbach.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1519815685-29200-1-git-send-email-abdallah.bouassida@lauterbach.com> References: <1519815685-29200-1-git-send-email-abdallah.bouassida@lauterbach.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 62.154.241.196 Subject: [Qemu-devel] [PATCH v3 3/4] target/arm: Add the XML dynamic generation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: khaled.jmal@lauterbach.com, qemu-arm@nongnu.org, Abdallah Bouassida Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Generate an XML description for the cp-regs. Register these regs with the gdb_register_coprocessor(). Add arm_gdb_get_sysreg() to use it as a callback to read those regs. Signed-off-by: Abdallah Bouassida --- gdbstub.c | 7 ++++ include/qom/cpu.h | 9 ++++- target/arm/cpu.c | 3 ++ target/arm/cpu.h | 17 +++++++++ target/arm/gdbstub.c | 97 ++++++++++++++++++++++++++++++++++++++++++++++++= ++++ 5 files changed, 132 insertions(+), 1 deletion(-) diff --git a/gdbstub.c b/gdbstub.c index f1d5148..ffab30b 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -665,6 +665,9 @@ static const char *get_feature_xml(const char *p, const= char **newp, pstrcat(target_xml, sizeof(target_xml), "gdb_core_xml_file); pstrcat(target_xml, sizeof(target_xml), "\"/>"); + if (cc->gdb_has_dynamic_xml) { + cc->register_gdb_regs_for_features(cpu); + } for (r =3D cpu->gdb_regs; r; r =3D r->next) { pstrcat(target_xml, sizeof(target_xml), "xml); @@ -674,6 +677,10 @@ static const char *get_feature_xml(const char *p, cons= t char **newp, } return target_xml; } + if (strncmp(p, "system-registers.xml", len) =3D=3D 0) { + CPUState *cpu =3D first_cpu; + return cc->gdb_get_dynamic_xml(cpu); + } for (i =3D 0; ; i++) { name =3D xml_builtin[i][0]; if (!name || (strncmp(name, p, len) =3D=3D 0 && strlen(name) =3D= =3D len)) diff --git a/include/qom/cpu.h b/include/qom/cpu.h index aff88fa..04771b3 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -131,6 +131,11 @@ struct TranslationBlock; * before the insn which triggers a watchpoint rather than after= it. * @gdb_arch_name: Optional callback that returns the architecture name kn= own * to GDB. The caller must free the returned string with g_free. + * @gdb_has_dynamic_xml: Indicates if GDB supports generating a dynamic XML + * description for the sysregs of this CPU. + * @register_gdb_regs_for_features: Callback for letting GDB create a dyna= mic + * XML description for the sysregs and register those sysregs afterw= ards. + * @gdb_get_dynamic_xml: Callback for letting GDB get the dynamic XML. * @cpu_exec_enter: Callback for cpu_exec preparation. * @cpu_exec_exit: Callback for cpu_exec cleanup. * @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec. @@ -197,7 +202,9 @@ typedef struct CPUClass { const struct VMStateDescription *vmsd; const char *gdb_core_xml_file; gchar * (*gdb_arch_name)(CPUState *cpu); - + bool gdb_has_dynamic_xml; + void (*register_gdb_regs_for_features)(CPUState *cpu); + char *(*gdb_get_dynamic_xml)(CPUState *cpu); void (*cpu_exec_enter)(CPUState *cpu); void (*cpu_exec_exit)(CPUState *cpu); bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 1b3ae62..04c4d04 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1781,6 +1781,9 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_num_core_regs =3D 26; cc->gdb_core_xml_file =3D "arm-core.xml"; cc->gdb_arch_name =3D arm_gdb_arch_name; + cc->gdb_has_dynamic_xml =3D true; + cc->register_gdb_regs_for_features =3D arm_register_gdb_regs_for_featu= res; + cc->gdb_get_dynamic_xml =3D arm_gdb_get_dynamic_xml; cc->gdb_stop_before_watchpoint =3D true; cc->debug_excp_handler =3D arm_debug_excp_handler; cc->debug_check_watchpoint =3D arm_debug_check_watchpoint; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 92cfe4c..0e35f64 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -133,6 +133,19 @@ enum { s<2n+1> maps to the most significant half of d */ =20 +/** + * DynamicGDBXMLInfo: + * @desc: Contains the XML descriptions. + * @num_cpregs: Number of the Coprocessor registers seen by GDB. + * @cpregs_keys: Array that contains the corresponding Key of + * a given cpreg with the same order of the cpreg in the XML description. + */ +typedef struct DynamicGDBXMLInfo { + char *desc; + int num_cpregs; + uint32_t *cpregs_keys; +} DynamicGDBXMLInfo; + /* CPU state for each instance of a generic timer (in cp15 c14) */ typedef struct ARMGenericTimer { uint64_t cval; /* Timer CompareValue register */ @@ -671,6 +684,8 @@ struct ARMCPU { uint64_t *cpreg_vmstate_values; int32_t cpreg_vmstate_array_len; =20 + DynamicGDBXMLInfo dyn_xml; + /* Timers used by the generic (architected) timer */ QEMUTimer *gt_timer[NUM_GTIMERS]; /* GPIO outputs for generic timer */ @@ -835,6 +850,8 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu,= vaddr addr, =20 int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); +void arm_register_gdb_regs_for_features(CPUState *cpu); +char *arm_gdb_get_dynamic_xml(CPUState *cpu); =20 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, int cpuid, void *opaque); diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 04c1208..e08ad79 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -101,3 +101,100 @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t = *mem_buf, int n) /* Unknown register. */ return 0; } + +static void arm_gen_one_xml_reg_tag(DynamicGDBXMLInfo *dyn_xml, + ARMCPRegInfo *ri, uint32_t ri_key, + bool is64) +{ + GString *s =3D g_string_new(dyn_xml->desc); + + g_string_append_printf(s, "name); + g_string_append_printf(s, " bitsize=3D\"%s\"", is64 ? "64" : "32"); + g_string_append_printf(s, " group=3D\"cp_regs\"/>"); + dyn_xml->desc =3D g_string_free(s, false); + dyn_xml->num_cpregs++; + dyn_xml->cpregs_keys =3D g_renew(uint32_t, + dyn_xml->cpregs_keys, + dyn_xml->num_cpregs); + dyn_xml->cpregs_keys[dyn_xml->num_cpregs - 1] =3D ri_key; +} + +static void arm_register_sysreg_for_xml(gpointer key, gpointer value, + gpointer cs) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + ARMCPRegInfo *ri =3D value; + uint32_t ri_key =3D *(uint32_t *)key; + + if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_NO_GDB))) { + if (env->aarch64) { + if (ri->state =3D=3D ARM_CP_STATE_AA64) { + arm_gen_one_xml_reg_tag(&cpu->dyn_xml, ri, ri_key, 1); + } + } else { + if (ri->state =3D=3D ARM_CP_STATE_AA32) { + if (!arm_feature(env, ARM_FEATURE_EL3) && + (ri->secure & ARM_CP_SECSTATE_S)) { + return; + } + if (ri->type & ARM_CP_64BIT) { + arm_gen_one_xml_reg_tag(&cpu->dyn_xml, ri, ri_key, 1); + } else { + arm_gen_one_xml_reg_tag(&cpu->dyn_xml, ri, ri_key, 0); + } + } + } + } +} + +static int arm_gen_dynamic_xml(CPUState *cs) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + GString *s =3D g_string_new(NULL); + + cpu->dyn_xml.num_cpregs =3D 0; + g_string_printf(s, ""); + g_string_append_printf(s, "= "); + g_string_append_printf(s, ""); + cpu->dyn_xml.desc =3D g_string_free(s, false); + g_hash_table_foreach(cpu->cp_regs, arm_register_sysreg_for_xml, cs); + s =3D g_string_new(cpu->dyn_xml.desc); + g_string_append_printf(s, ""); + cpu->dyn_xml.desc =3D g_string_free(s, false); + return cpu->dyn_xml.num_cpregs; +} + +static int arm_gdb_get_sysreg(CPUARMState *env, uint8_t *buf, int reg) +{ + ARMCPU *cpu =3D arm_env_get_cpu(env); + const ARMCPRegInfo *ri; + uint32_t key; + + key =3D cpu->dyn_xml.cpregs_keys[reg]; + ri =3D get_arm_cp_reginfo(cpu->cp_regs, key); + if (ri) { + if (cpreg_field_is_64bit(ri)) { + return gdb_get_reg64(buf, (uint64_t)read_raw_cp_reg(env, ri)); + } else { + return gdb_get_reg32(buf, (uint32_t)read_raw_cp_reg(env, ri)); + } + } + return 0; +} + +void arm_register_gdb_regs_for_features(CPUState *cs) +{ + int n; + + n =3D arm_gen_dynamic_xml(cs); + gdb_register_coprocessor(cs, arm_gdb_get_sysreg, NULL, + n, "system-registers.xml", 0); + +} + +char *arm_gdb_get_dynamic_xml(CPUState *cs) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + return cpu->dyn_xml.desc; +} --=20 2.7.4 From nobody Fri Oct 24 09:57:35 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519815942663125.00681715213716; Wed, 28 Feb 2018 03:05:42 -0800 (PST) Received: from localhost ([::1]:43308 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eqzYL-0005pd-F5 for importer@patchew.org; Wed, 28 Feb 2018 06:05:41 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40213) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eqzV8-0003dY-Lv for qemu-devel@nongnu.org; Wed, 28 Feb 2018 06:02:29 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eqzV4-0007Nl-NS for qemu-devel@nongnu.org; Wed, 28 Feb 2018 06:02:22 -0500 Received: from smtp1.lauterbach.com ([62.154.241.196]:53912) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eqzV4-0007GH-Cm for qemu-devel@nongnu.org; Wed, 28 Feb 2018 06:02:18 -0500 Received: (qmail 1098 invoked by uid 484); 28 Feb 2018 11:02:01 -0000 Received: from unknown (HELO localhost.localdomain) (Authenticated_SSL:abouassida@[41.224.44.126]) (envelope-sender ) by smtp1.lauterbach.com (qmail-ldap-1.03) with ECDHE-RSA-AES256-SHA encrypted SMTP for ; 28 Feb 2018 11:02:00 -0000 X-Qmail-Scanner-Diagnostics: from 41.224.44.126 by smtp1.lauterbach.com (envelope-from , uid 484) with qmail-scanner-2.11 (mhr: 1.0. clamdscan: 0.99/21437. spamassassin: 3.4.0. Clear:RC:1(41.224.44.126):. Processed in 0.052075 secs); 28 Feb 2018 11:02:01 -0000 From: Abdallah Bouassida To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Wed, 28 Feb 2018 12:01:25 +0100 Message-Id: <1519815685-29200-5-git-send-email-abdallah.bouassida@lauterbach.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1519815685-29200-1-git-send-email-abdallah.bouassida@lauterbach.com> References: <1519815685-29200-1-git-send-email-abdallah.bouassida@lauterbach.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 62.154.241.196 Subject: [Qemu-devel] [PATCH v3 4/4] target/arm: Add arm_gdb_set_sysreg() callback X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: khaled.jmal@lauterbach.com, qemu-arm@nongnu.org, Abdallah Bouassida Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 This is a callback to set the cp-regs registered by the dynamic XML. Signed-off-by: Abdallah Bouassida --- >> Some of our customers need to connect to Qemu using our tool TRACE32=C2= =AE=20 >> via GDB, >> and for some use case they need to have write access to some particular=20 >> cpregs. >> So, it will be nice to have this capability! >> Usually, a user won't modify these registers unless he knows what he is=20 >> doing! > I also still don't really like using write_raw_cp_reg() here -- > it will bypass some behaviour you want and in some cases will > just break the emulation because invariants we assume will > hold no longer hold. It would be a lot lot safer to not > provide write access at all, only read access. Adding to that our customers may need this write access, our tool TRACE32= =C2=AE needs this also in some particular cases. For example: temporary disabling = MMU to do a physical memory access. target/arm/cpu.h | 2 ++ target/arm/gdbstub.c | 21 ++++++++++++++++++++- target/arm/helper.c | 2 +- 3 files changed, 23 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0e35f64..f4fea98 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2120,6 +2120,8 @@ static inline bool cp_access_ok(int current_el, /* Raw read of a coprocessor register (as needed for migration, etc) */ uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); =20 +void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= ); + /** * write_list_to_cpustate * @cpu: ARMCPU diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index e08ad79..57bd418 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -183,12 +183,31 @@ static int arm_gdb_get_sysreg(CPUARMState *env, uint8= _t *buf, int reg) return 0; } =20 +static int arm_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg) +{ + ARMCPU *cpu =3D arm_env_get_cpu(env); + const ARMCPRegInfo *ri; + uint32_t key; + uint32_t tmp; + + tmp =3D ldl_p(buf); + key =3D cpu->dyn_xml.cpregs_keys[reg]; + ri =3D get_arm_cp_reginfo(arm_env_get_cpu(env)->cp_regs, key); + if (ri) { + if (!(ri->type & ARM_CP_CONST)) { + write_raw_cp_reg(env, ri, tmp); + return cpreg_field_is_64bit(ri) ? 8 : 4; + } + } + return 0; +} + void arm_register_gdb_regs_for_features(CPUState *cs) { int n; =20 n =3D arm_gen_dynamic_xml(cs); - gdb_register_coprocessor(cs, arm_gdb_get_sysreg, NULL, + gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg, n, "system-registers.xml", 0); =20 } diff --git a/target/arm/helper.c b/target/arm/helper.c index 1594ec45..4a4afbf 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -200,7 +200,7 @@ uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPR= egInfo *ri) } } =20 -static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, +void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v) { /* Raw write of a coprocessor register (as needed for migration, etc). --=20 2.7.4