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[125.237.39.90]) by smtp.gmail.com with ESMTPSA id n14sm13592702pfj.154.2018.02.26.14.20.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 26 Feb 2018 14:20:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ekNgtByIR97NLBAk4alx/lWTIR9EO1F99UlAaIfy5fI=; b=j0zMj0MS7YbOZqdvbOQX8tnP62P3nZFJl5sR8LAbX+IOX4TeGubMU8HODJ3zyxApZn Q9Sphgm8sk2eCkBkdWAmlYxoz4TMO3PrLFuX9AeVGJIUBDCrWN7yU6OQrytYIiJ5N3C3 Dd0MH964rZV3CWHMdmi7XKxeW1/W9K6OT/RDnh0lzare3LLZVrQH5qSDHEi/Tqj52TSA d7KAGccH9JMkSbMu1whguZ3LvJvhRnxwVID3F1ynx8HVz+uNKCmGQoId3wf7MLtbbfaO YkVTMch5s8EjQPPtxRaoU1dCtnmWutR9jYXIvipECQad5sho311MiMiyVDgIOG6cZWhe srmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ekNgtByIR97NLBAk4alx/lWTIR9EO1F99UlAaIfy5fI=; b=mA9M6CiZaeKN+ZnNNq2uXbyRzh7o8Ta/mZUZaT6cymotYAJwuaSiimWMwllfkiwG7Y weY+PSI/uKCHu6jEEziY6GGRTKYSsRwGrHVmqx91WK7NX4VlTuLH3uoDLxj6TfI+Sz3m 5ROQTotATUD5LrjUj/VrM2bx7fkOm6C652RcKoBF/+vYcqgWLfa4I3y3WJfgdL0wf5lb 32ZpObu13Uovc5J/PETvuKLnOTS8kX7yew9D/6rJr4fjJWGoyhM7BS0Jtvg4dPT+IxTO hIrcYNUoiXWLHoN57a6RmRB3//y3n1KWeGPHg5S8eTjbLyWYRrccqgMoqnOfyBXAcUum SJIw== X-Gm-Message-State: APf1xPD96W4qrPmvkoM9/BlaCEaCupfCoHMFJ9El/d8s21w8ykT8zvU+ OzI9ML1hsSko1zTgwihkcHSWsH9LUv0= X-Google-Smtp-Source: AH8x224nqLZlNfD1hAiFc1ddT2nHRUSfEmV5qj4kZdYfqhsYw9/rA6XxtOgat7PaXmfSZPZfEZDtSw== X-Received: by 10.99.124.25 with SMTP id x25mr9659108pgc.372.1519683622667; Mon, 26 Feb 2018 14:20:22 -0800 (PST) From: Michael Clark To: qemu-devel@nongnu.org Date: Tue, 27 Feb 2018 11:17:57 +1300 Message-Id: <1519683480-33201-21-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1519683480-33201-1-git-send-email-mjc@sifive.com> References: <1519683480-33201-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH v7 20/23] SiFive RISC-V PRCI Block X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Michael Clark , Palmer Dabbelt , Sagar Karandikar , RISC-V Patches Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Simple model of the PRCI (Power, Reset, Clock, Interrupt) to emulate register reads made by the SDK BSP. Acked-by: Richard Henderson Signed-off-by: Michael Clark --- hw/riscv/sifive_prci.c | 89 ++++++++++++++++++++++++++++++++++++++= ++++ include/hw/riscv/sifive_prci.h | 37 ++++++++++++++++++ 2 files changed, 126 insertions(+) create mode 100644 hw/riscv/sifive_prci.c create mode 100644 include/hw/riscv/sifive_prci.h diff --git a/hw/riscv/sifive_prci.c b/hw/riscv/sifive_prci.c new file mode 100644 index 0000000..0910ea3 --- /dev/null +++ b/hw/riscv/sifive_prci.c @@ -0,0 +1,89 @@ +/* + * QEMU SiFive PRCI (Power, Reset, Clock, Interrupt) + * + * Copyright (c) 2017 SiFive, Inc. + * + * Simple model of the PRCI to emulate register reads made by the SDK BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "target/riscv/cpu.h" +#include "hw/riscv/sifive_prci.h" + +/* currently implements enough to mock freedom-e-sdk BSP clock programming= */ + +static uint64_t sifive_prci_read(void *opaque, hwaddr addr, unsigned int s= ize) +{ + if (addr =3D=3D 0 /* PRCI_HFROSCCFG */) { + return 1 << 31; /* ROSC_RDY */ + } + if (addr =3D=3D 8 /* PRCI_PLLCFG */) { + return 1 << 31; /* PLL_LOCK */ + } + hw_error("%s: read: addr=3D0x%x\n", __func__, (int)addr); + return 0; +} + +static void sifive_prci_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + /* discard writes */ +} + +static const MemoryRegionOps sifive_prci_ops =3D { + .read =3D sifive_prci_read, + .write =3D sifive_prci_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4 + } +}; + +static void sifive_prci_init(Object *obj) +{ + SiFivePRCIState *s =3D SIFIVE_PRCI(obj); + + memory_region_init_io(&s->mmio, obj, &sifive_prci_ops, s, + TYPE_SIFIVE_PRCI, 0x8000); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); +} + +static const TypeInfo sifive_prci_info =3D { + .name =3D TYPE_SIFIVE_PRCI, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(SiFivePRCIState), + .instance_init =3D sifive_prci_init, +}; + +static void sifive_prci_register_types(void) +{ + type_register_static(&sifive_prci_info); +} + +type_init(sifive_prci_register_types) + + +/* + * Create PRCI device. + */ +DeviceState *sifive_prci_create(hwaddr addr) +{ + DeviceState *dev =3D qdev_create(NULL, TYPE_SIFIVE_PRCI); + qdev_init_nofail(dev); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); + return dev; +} diff --git a/include/hw/riscv/sifive_prci.h b/include/hw/riscv/sifive_prci.h new file mode 100644 index 0000000..b6f4c48 --- /dev/null +++ b/include/hw/riscv/sifive_prci.h @@ -0,0 +1,37 @@ +/* + * QEMU SiFive PRCI (Power, Reset, Clock, Interrupt) interface + * + * Copyright (c) 2017 SiFive, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#ifndef HW_SIFIVE_PRCI_H +#define HW_SIFIVE_PRCI_H + +#define TYPE_SIFIVE_PRCI "riscv.sifive.prci" + +#define SIFIVE_PRCI(obj) \ + OBJECT_CHECK(SiFivePRCIState, (obj), TYPE_SIFIVE_PRCI) + +typedef struct SiFivePRCIState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion mmio; +} SiFivePRCIState; + +DeviceState *sifive_prci_create(hwaddr addr); + +#endif --=20 2.7.0