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[125.237.39.90]) by smtp.gmail.com with ESMTPSA id u9sm1769551pgb.11.2018.02.22.16.14.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 22 Feb 2018 16:14:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VRHjSv6yQ544qnPsfLQ7LMEdK6nuZMg6j1k8FEh/Vu8=; b=gc/G0rm+KUVFCiwPEenCwVHNu4H2Sy7zayNiqrTJ+0tYxDTry3996sYrme/efLj+U8 yjyweghtcVQmEkhObXCqXtzkNHrruMDSHxC3uk3m3xb7PiZyA9IM4cvS86hWnzyBIXQb 47BHxqOyt5VFVXyb5s6356iKmREDhBbsG3c+9TDfyjLjFW/xThhaDKsq4NqW/R4XtQRx kqRJtcMDUs1u4nKwEWQk4tOXQKvbrOjC9MOVhB6PlChDyg7BhNsS0MCiTBMIAkVHveo6 nMWUQcF4h4JLgI7SwqkAeUzhtpp2IEJiaIs+/aTfXQPKN20FGGAgq/UjNYY0IRMC7/cJ jfkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VRHjSv6yQ544qnPsfLQ7LMEdK6nuZMg6j1k8FEh/Vu8=; b=PLjrFEe+aJ7cn+eX9XwlYATeHII7nkx1aS1p5+AU3FcY57mfmU8gIhYEi9LuD9/mb0 AZ8FOzFnW4YVTTmpkncGJhFmEd20KqNMDpZf3YF8uv8FN7YK3QGDpcYR8TFqEojAyBq4 A24foTzHWC0DQolTQCClAFOg0zSH5T9uoGlPnr3Sz6/uCOb55fKNkQTu3oGF3X7nQhp2 a6oCD7Q9APxYy04odHGXjAIeLhHMvCRbTKtgKYcEkRr7JikdleRQUmqEM6J8AvzwuVxH InEeUxwU0tELuCNi6spNxbOSXE73Cn+5ic40tVmAMAD7l/9DkgVuILm1zbrEo608IvTs 3hBw== X-Gm-Message-State: APf1xPC+GeqFsH+zr5jgg4/pOCIoSmXZpnjTNU9jrgklZF0u2AAjucjm 8bY+Vtub7ZgO74y1F7Y0HnevD8yvE58= X-Google-Smtp-Source: AH8x227DKEqtx+2WEoEopq2ABS82Fs0IeVMLng0k0J3MmX/KDbuGxiw+84WPDil2Se+QQL8rA+kn6g== X-Received: by 10.99.145.194 with SMTP id l185mr6841691pge.394.1519344876835; Thu, 22 Feb 2018 16:14:36 -0800 (PST) From: Michael Clark To: qemu-devel@nongnu.org Date: Fri, 23 Feb 2018 13:12:04 +1300 Message-Id: <1519344729-73482-19-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1519344729-73482-1-git-send-email-mjc@sifive.com> References: <1519344729-73482-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH v6 18/23] SiFive RISC-V UART Device X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Michael Clark , Palmer Dabbelt , Sagar Karandikar , RISC-V Patches Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" QEMU model of the UART on the SiFive E300 and U500 series SOCs. BBL supports the SiFive UART for early console access via the SBI (Supervisor Binary Interface) and the linux kernel SBI console. The SiFive UART implements the pre qom legacy interface consistent with the 16550a UART in 'hw/char/serial.c'. Signed-off-by: Michael Clark --- hw/riscv/sifive_uart.c | 182 +++++++++++++++++++++++++++++++++++++= ++++ include/hw/riscv/sifive_uart.h | 76 +++++++++++++++++ 2 files changed, 258 insertions(+) create mode 100644 hw/riscv/sifive_uart.c create mode 100644 include/hw/riscv/sifive_uart.h diff --git a/hw/riscv/sifive_uart.c b/hw/riscv/sifive_uart.c new file mode 100644 index 0000000..0e73df6 --- /dev/null +++ b/hw/riscv/sifive_uart.c @@ -0,0 +1,182 @@ +/* + * QEMU model of the UART on the SiFive E300 and U500 series SOCs. + * + * Copyright (c) 2016 Stefan O'Rear + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/sysbus.h" +#include "chardev/char.h" +#include "chardev/char-fe.h" +#include "target/riscv/cpu.h" +#include "hw/riscv/sifive_uart.h" + +/* + * Not yet implemented: + * + * Transmit FIFO using "qemu/fifo8.h" + * SIFIVE_UART_IE_TXWM interrupts + * SIFIVE_UART_IE_RXWM interrupts must honor fifo watermark + * Rx FIFO watermark interrupt trigger threshold + * Tx FIFO watermark interrupt trigger threshold. + */ + +static void update_irq(SiFiveUARTState *s) +{ + int cond =3D 0; + if ((s->ie & SIFIVE_UART_IE_RXWM) && s->rx_fifo_len) { + cond =3D 1; + } + if (cond) { + qemu_irq_raise(s->irq); + } else { + qemu_irq_lower(s->irq); + } +} + +static uint64_t +uart_read(void *opaque, hwaddr addr, unsigned int size) +{ + SiFiveUARTState *s =3D opaque; + unsigned char r; + switch (addr) { + case SIFIVE_UART_RXFIFO: + if (s->rx_fifo_len) { + r =3D s->rx_fifo[0]; + memmove(s->rx_fifo, s->rx_fifo + 1, s->rx_fifo_len - 1); + s->rx_fifo_len--; + qemu_chr_fe_accept_input(&s->chr); + update_irq(s); + return r; + } + return 0x80000000; + + case SIFIVE_UART_TXFIFO: + return 0; /* Should check tx fifo */ + case SIFIVE_UART_IE: + return s->ie; + case SIFIVE_UART_IP: + return s->rx_fifo_len ? SIFIVE_UART_IP_RXWM : 0; + case SIFIVE_UART_TXCTRL: + return s->txctrl; + case SIFIVE_UART_RXCTRL: + return s->rxctrl; + case SIFIVE_UART_DIV: + return s->div; + } + + hw_error("%s: bad read: addr=3D0x%x\n", + __func__, (int)addr); + return 0; +} + +static void +uart_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + SiFiveUARTState *s =3D opaque; + uint32_t value =3D val64; + unsigned char ch =3D value; + + switch (addr) { + case SIFIVE_UART_TXFIFO: + qemu_chr_fe_write(&s->chr, &ch, 1); + return; + case SIFIVE_UART_IE: + s->ie =3D val64; + update_irq(s); + return; + case SIFIVE_UART_TXCTRL: + s->txctrl =3D val64; + return; + case SIFIVE_UART_RXCTRL: + s->rxctrl =3D val64; + return; + case SIFIVE_UART_DIV: + s->div =3D val64; + return; + } + hw_error("%s: bad write: addr=3D0x%x v=3D0x%x\n", + __func__, (int)addr, (int)value); +} + +static const MemoryRegionOps uart_ops =3D { + .read =3D uart_read, + .write =3D uart_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4 + } +}; + +static void uart_rx(void *opaque, const uint8_t *buf, int size) +{ + SiFiveUARTState *s =3D opaque; + + /* Got a byte. */ + if (s->rx_fifo_len >=3D sizeof(s->rx_fifo)) { + printf("WARNING: UART dropped char.\n"); + return; + } + s->rx_fifo[s->rx_fifo_len++] =3D *buf; + + update_irq(s); +} + +static int uart_can_rx(void *opaque) +{ + SiFiveUARTState *s =3D opaque; + + return s->rx_fifo_len < sizeof(s->rx_fifo); +} + +static void uart_event(void *opaque, int event) +{ +} + +static int uart_be_change(void *opaque) +{ + SiFiveUARTState *s =3D opaque; + + qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event, + uart_be_change, s, NULL, true); + + return 0; +} + +/* + * Create UART device. + */ +SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr ba= se, + Chardev *chr, qemu_irq irq) +{ + SiFiveUARTState *s =3D g_malloc0(sizeof(SiFiveUARTState)); + s->irq =3D irq; + qemu_chr_fe_init(&s->chr, chr, &error_abort); + qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event, + uart_be_change, s, NULL, true); + memory_region_init_io(&s->mmio, NULL, &uart_ops, s, + TYPE_SIFIVE_UART, SIFIVE_UART_MAX); + memory_region_add_subregion(address_space, base, &s->mmio); + return s; +} diff --git a/include/hw/riscv/sifive_uart.h b/include/hw/riscv/sifive_uart.h new file mode 100644 index 0000000..1ab0106 --- /dev/null +++ b/include/hw/riscv/sifive_uart.h @@ -0,0 +1,76 @@ +/* + * SiFive UART interface + * + * Copyright (c) 2017 SiFive, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef HW_SIFIVE_UART_H +#define HW_SIFIVE_UART_H + +enum { + SIFIVE_UART_TXFIFO =3D 0, + SIFIVE_UART_RXFIFO =3D 4, + SIFIVE_UART_TXCTRL =3D 8, + SIFIVE_UART_TXMARK =3D 10, + SIFIVE_UART_RXCTRL =3D 12, + SIFIVE_UART_RXMARK =3D 14, + SIFIVE_UART_IE =3D 16, + SIFIVE_UART_IP =3D 20, + SIFIVE_UART_DIV =3D 24, + SIFIVE_UART_MAX =3D 32 +}; + +enum { + SIFIVE_UART_IE_TXWM =3D 1, /* Transmit watermark interrupt enabl= e */ + SIFIVE_UART_IE_RXWM =3D 2 /* Receive watermark interrupt enable= */ +}; + +enum { + SIFIVE_UART_IP_TXWM =3D 1, /* Transmit watermark interrupt pendi= ng */ + SIFIVE_UART_IP_RXWM =3D 2 /* Receive watermark interrupt pendin= g */ +}; + +#define TYPE_SIFIVE_UART "riscv.sifive.uart" + +#define SIFIVE_UART(obj) \ + OBJECT_CHECK(SiFiveUARTState, (obj), TYPE_SIFIVE_UART) + +typedef struct SiFiveUARTState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + qemu_irq irq; + MemoryRegion mmio; + CharBackend chr; + uint8_t rx_fifo[8]; + unsigned int rx_fifo_len; + uint32_t ie; + uint32_t ip; + uint32_t txctrl; + uint32_t rxctrl; + uint32_t div; +} SiFiveUARTState; + +SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr ba= se, + Chardev *chr, qemu_irq irq); + +#endif --=20 2.7.0