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[125.237.39.90]) by smtp.gmail.com with ESMTPSA id u9sm1769551pgb.11.2018.02.22.16.14.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 22 Feb 2018 16:14:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lvnbHddGecvC4BX4f2fGvF4S7aoEjc1sXb8FTdoxG+o=; b=f9qwASsXn3S41HJib2ziZJKZlvplccRZjL4IDOHrkC5MMnQuizbaQwGuCW+QYHj4SC SzLu2FZRJyuovWs/FupeVTFAgJByDHdgztyXKtvuzxoNDBh3uYCA6S7p7BcQix4W93sw 68+VhxoWusODRWX03Wi2Tz3Fwl/2efaNPS2Ywy2/2A+LKkYyCTlIWKyzDIgzYmvcigtQ 7LG1c0ovH5pDDSFCC3eVwns6bVYrpkt/yt3AtucQCZpLmPISObby6F4uGxh65vXW1Ipj 7qYH0of3l0sFidTvJgv356hJPikKLTcfmk6goSKRdgZwepU2egFWv7gbEdSLboSt4KkL GOAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lvnbHddGecvC4BX4f2fGvF4S7aoEjc1sXb8FTdoxG+o=; b=czHKLgU4rVeZB6ALt+i8Y1emnoGvR2soR91/txtim3itznGXTzoqDdaVsoDE8mh2vh qB/rYtSObQLwAP+LfOZ6f1bI1gvWhYVNoznx1hLinEC9WPZsPj87uZDo0llNAQyTLB7l QuIrlREEOFfsTCpAqjApzwHr3CaCWrNds3dCJ7d4WklAoi9rEm/F3aniWbPK7ihRKlbN DzupIZ3Hsw3XH8Gnmmh+II2KLZGt71UUcjvpuQerqJYPQZ91NxEZ6AXEZr00vNisdo8i Bcun0KYYZr2s38lALVXSh1Qw9ko7le506E7JoShlsTDNrgK4MiucPZFh9Zbv4leJh7vt O66A== X-Gm-Message-State: APf1xPBqmSh87YiQ4qSFGGU7/GBSG/FKJNZb765QWTa0H8Pq2l+z92BM WXuVuF9/KraZ9pIYdlhj+SNyMazagfE= X-Google-Smtp-Source: AH8x226X9//s5neMWvIO4NLTFLKCo7CXvNXFvnAH0DGgh3FMRMBBiCz6zOP7H4IVlhZEQE8vjWRx1A== X-Received: by 10.99.94.67 with SMTP id s64mr6852095pgb.379.1519344859752; Thu, 22 Feb 2018 16:14:19 -0800 (PST) From: Michael Clark To: qemu-devel@nongnu.org Date: Fri, 23 Feb 2018 13:11:59 +1300 Message-Id: <1519344729-73482-14-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1519344729-73482-1-git-send-email-mjc@sifive.com> References: <1519344729-73482-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22f Subject: [Qemu-devel] [PATCH v6 13/23] RISC-V HART Array X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Michael Clark , Palmer Dabbelt , Sagar Karandikar , RISC-V Patches Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Holds the state of a heterogenous array of RISC-V hardware threads. Reviewed-by: Richard Henderson Signed-off-by: Michael Clark --- hw/riscv/riscv_hart.c | 95 +++++++++++++++++++++++++++++++++++++++= ++++ include/hw/riscv/riscv_hart.h | 45 ++++++++++++++++++++ 2 files changed, 140 insertions(+) create mode 100644 hw/riscv/riscv_hart.c create mode 100644 include/hw/riscv/riscv_hart.h diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c new file mode 100644 index 0000000..88d5836 --- /dev/null +++ b/hw/riscv/riscv_hart.c @@ -0,0 +1,95 @@ +/* + * QEMU RISCV Hart Array + * + * Copyright (c) 2017 SiFive, Inc. + * + * Holds the state of a heterogenous array of RISC-V harts + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/sysbus.h" +#include "target/riscv/cpu.h" +#include "hw/riscv/riscv_hart.h" + +static Property riscv_harts_props[] =3D { + DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1), + DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type), + DEFINE_PROP_END_OF_LIST(), +}; + +static void riscv_harts_cpu_reset(void *opaque) +{ + RISCVCPU *cpu =3D opaque; + cpu_reset(CPU(cpu)); +} + +static void riscv_harts_realize(DeviceState *dev, Error **errp) +{ + RISCVHartArrayState *s =3D RISCV_HART_ARRAY(dev); + Error *err =3D NULL; + int n; + + s->harts =3D g_new0(RISCVCPU, s->num_harts); + + for (n =3D 0; n < s->num_harts; n++) { + + object_initialize(&s->harts[n], sizeof(RISCVCPU), s->cpu_type); + s->harts[n].env.mhartid =3D n; + object_property_add_child(OBJECT(s), "harts[*]", OBJECT(&s->harts[= n]), + &error_abort); + qemu_register_reset(riscv_harts_cpu_reset, &s->harts[n]); + object_property_set_bool(OBJECT(&s->harts[n]), true, + "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + } +} + +static void riscv_harts_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->props =3D riscv_harts_props; + dc->realize =3D riscv_harts_realize; +} + +static void riscv_harts_init(Object *obj) +{ + /* RISCVHartArrayState *s =3D SIFIVE_COREPLEX(obj); */ +} + +static const TypeInfo riscv_harts_info =3D { + .name =3D TYPE_RISCV_HART_ARRAY, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(RISCVHartArrayState), + .instance_init =3D riscv_harts_init, + .class_init =3D riscv_harts_class_init, +}; + +static void riscv_harts_register_types(void) +{ + type_register_static(&riscv_harts_info); +} + +type_init(riscv_harts_register_types) diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h new file mode 100644 index 0000000..39acb0f --- /dev/null +++ b/include/hw/riscv/riscv_hart.h @@ -0,0 +1,45 @@ +/* + * QEMU RISC-V Hart Array interface + * + * Copyright (c) 2017 SiFive, Inc. + * + * Holds the state of a heterogenous array of RISC-V harts + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef HW_RISCV_HART_H +#define HW_RISCV_HART_H + +#define TYPE_RISCV_HART_ARRAY "riscv.hart_array" + +#define RISCV_HART_ARRAY(obj) \ + OBJECT_CHECK(RISCVHartArrayState, (obj), TYPE_RISCV_HART_ARRAY) + +typedef struct RISCVHartArrayState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + uint32_t num_harts; + char *cpu_type; + RISCVCPU *harts; +} RISCVHartArrayState; + +#endif --=20 2.7.0