From nobody Wed Oct 22 13:03:25 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519324631414900.4922193184158; Thu, 22 Feb 2018 10:37:11 -0800 (PST) Received: from localhost ([::1]:40399 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eovjy-00089Q-KH for importer@patchew.org; Thu, 22 Feb 2018 13:37:10 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49295) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eovfW-0004eK-Ow for qemu-devel@nongnu.org; Thu, 22 Feb 2018 13:32:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eovfT-0005tE-MH for qemu-devel@nongnu.org; Thu, 22 Feb 2018 13:32:34 -0500 Received: from mx2.rt-rk.com ([89.216.37.149]:35078 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eovfT-0005Pd-2y for qemu-devel@nongnu.org; Thu, 22 Feb 2018 13:32:31 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 649091A2201; Thu, 22 Feb 2018 19:32:06 +0100 (CET) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 3E9121A226E; Thu, 22 Feb 2018 19:32:06 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 22 Feb 2018 19:31:38 +0100 Message-Id: <1519324303-5674-2-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1519324303-5674-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1519324303-5674-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v2 1/6] target/mips: compare virtual addresses in LL/SC sequence X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Petar Jovanovic , Fam Zheng , Aleksandar Markovic , Raghu Gandham , Yongbok Kim , Riku Voipio , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Gerd Hoffmann , Goran Ferenc , Paolo Bonzini , Miodrag Dinic , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Leon Alrae Do only virtual addresses comaprisons in LL/SC sequence emulations. Until this patch, physical addresses had been compared in SC part of LL/SC sequence, even though such comparisons could be avoided. Getting rid of them allows throwing away SC helpers and having common SC implementations in user and system mode, avoiding the need for two separate implementations selected by #ifdef CONFIG_USER_ONLY. Correct guest software should not rely on LL/SC if they accesses the same physical address via different virtual addresses or if page mapping gets changed between LL/SC due to manipulating TLB entries. MIPS Instruction Set Manual clearly says that an RMW sequence must use the same address in the LL and SC (virtual address, physical address, cacheability and coherency attributes must be identical). Otherwise, the result of the SC is not predictable. This patch takes advantage of this fact and removes the virtual->physical address translation from SC helper. lladdr served as Coprocessor 0 LLAddr register which captures physical address of the most recent LL instruction, and also lladdr was used for comparison with following SC physical address. This patch changes the meaning of lladdr - now it will only keep the virtual address of the most recent LL. Additionally, CP0_LLAddr field is introduced which is the actual Coperocessor 0 LLAddr register that guest can access. Signed-off-by: Leon Alrae Signed-off-by: Miodrag Dinic Signed-off-by: Aleksandar Markovic Acked-by: Alex Benn=C3=A9e --- target/mips/cpu.h | 3 ++- target/mips/machine.c | 7 ++++--- target/mips/op_helper.c | 29 +++++++++++++++++------------ target/mips/translate.c | 4 ++-- 4 files changed, 25 insertions(+), 18 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 7f8ba5f..57ca861 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -480,10 +480,11 @@ struct CPUMIPSState { #define CP0C5_NFExists 0 int32_t CP0_Config6; int32_t CP0_Config7; + uint64_t CP0_LLAddr; uint64_t CP0_MAAR[MIPS_MAAR_MAX]; int32_t CP0_MAARI; /* XXX: Maybe make LLAddr per-TC? */ - uint64_t lladdr; + target_ulong lladdr; /* LL virtual address compared against SC */ target_ulong llval; target_ulong llnewval; target_ulong llreg; diff --git a/target/mips/machine.c b/target/mips/machine.c index 20100d5..155170c 100644 --- a/target/mips/machine.c +++ b/target/mips/machine.c @@ -212,8 +212,8 @@ const VMStateDescription vmstate_tlb =3D { =20 const VMStateDescription vmstate_mips_cpu =3D { .name =3D "cpu", - .version_id =3D 10, - .minimum_version_id =3D 10, + .version_id =3D 11, + .minimum_version_id =3D 11, .post_load =3D cpu_post_load, .fields =3D (VMStateField[]) { /* Active TC */ @@ -283,9 +283,10 @@ const VMStateDescription vmstate_mips_cpu =3D { VMSTATE_INT32(env.CP0_Config3, MIPSCPU), VMSTATE_INT32(env.CP0_Config6, MIPSCPU), VMSTATE_INT32(env.CP0_Config7, MIPSCPU), + VMSTATE_UINT64(env.CP0_LLAddr, MIPSCPU), VMSTATE_UINT64_ARRAY(env.CP0_MAAR, MIPSCPU, MIPS_MAAR_MAX), VMSTATE_INT32(env.CP0_MAARI, MIPSCPU), - VMSTATE_UINT64(env.lladdr, MIPSCPU), + VMSTATE_UINTTL(env.lladdr, MIPSCPU), VMSTATE_UINTTL_ARRAY(env.CP0_WatchLo, MIPSCPU, 8), VMSTATE_INT32_ARRAY(env.CP0_WatchHi, MIPSCPU, 8), VMSTATE_UINTTL(env.CP0_XContext, MIPSCPU), diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 798cdad..cc5cd4e 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -255,15 +255,15 @@ static inline hwaddr do_translate_address(CPUMIPSStat= e *env, target_ulong address, int rw, uintptr_t re= taddr) { - hwaddr lladdr; + hwaddr paddr; CPUState *cs =3D CPU(mips_env_get_cpu(env)); =20 - lladdr =3D cpu_mips_translate_address(env, address, rw); + paddr =3D cpu_mips_translate_address(env, address, rw); =20 - if (lladdr =3D=3D -1LL) { + if (paddr =3D=3D -1LL) { cpu_loop_exit_restore(cs, retaddr); } else { - return lladdr; + return paddr; } } =20 @@ -274,7 +274,8 @@ target_ulong helper_##name(CPUMIPSState *env, target_ul= ong arg, int mem_idx) \ env->CP0_BadVAddr =3D arg; = \ do_raise_exception(env, EXCP_AdEL, GETPC()); = \ } = \ - env->lladdr =3D do_translate_address(env, arg, 0, GETPC()); = \ + env->CP0_LLAddr =3D do_translate_address(env, arg, 0, GETPC()); = \ + env->lladdr =3D arg; = \ env->llval =3D do_##insn(env, arg, mem_idx, GETPC()); = \ return env->llval; = \ } @@ -294,7 +295,7 @@ target_ulong helper_##name(CPUMIPSState *env, target_ul= ong arg1, \ env->CP0_BadVAddr =3D arg2; = \ do_raise_exception(env, EXCP_AdES, GETPC()); = \ } = \ - if (do_translate_address(env, arg2, 1, GETPC()) =3D=3D env->lladdr) { = \ + if (arg2 =3D=3D env->lladdr) { = \ tmp =3D do_##ld_insn(env, arg2, mem_idx, GETPC()); = \ if (tmp =3D=3D env->llval) { = \ do_##st_insn(env, arg2, arg1, mem_idx, GETPC()); = \ @@ -873,7 +874,7 @@ target_ulong helper_mftc0_status(CPUMIPSState *env) =20 target_ulong helper_mfc0_lladdr(CPUMIPSState *env) { - return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift); + return (int32_t)(env->CP0_LLAddr >> env->CP0_LLAddr_shift); } =20 target_ulong helper_mfc0_maar(CPUMIPSState *env) @@ -949,7 +950,7 @@ target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env) =20 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env) { - return env->lladdr >> env->CP0_LLAddr_shift; + return env->CP0_LLAddr >> env->CP0_LLAddr_shift; } =20 target_ulong helper_dmfc0_maar(CPUMIPSState *env) @@ -1177,7 +1178,8 @@ void helper_mtc0_tcrestart(CPUMIPSState *env, target_= ulong arg1) { env->active_tc.PC =3D arg1; env->active_tc.CP0_TCStatus &=3D ~(1 << CP0TCSt_TDS); - env->lladdr =3D 0ULL; + env->CP0_LLAddr =3D 0; + env->lladdr =3D 0; /* MIPS16 not implemented. */ } =20 @@ -1189,12 +1191,14 @@ void helper_mttc0_tcrestart(CPUMIPSState *env, targ= et_ulong arg1) if (other_tc =3D=3D other->current_tc) { other->active_tc.PC =3D arg1; other->active_tc.CP0_TCStatus &=3D ~(1 << CP0TCSt_TDS); - other->lladdr =3D 0ULL; + other->CP0_LLAddr =3D 0; + other->lladdr =3D 0; /* MIPS16 not implemented. */ } else { other->tcs[other_tc].PC =3D arg1; other->tcs[other_tc].CP0_TCStatus &=3D ~(1 << CP0TCSt_TDS); - other->lladdr =3D 0ULL; + other->CP0_LLAddr =3D 0; + other->lladdr =3D 0; /* MIPS16 not implemented. */ } } @@ -1620,7 +1624,7 @@ void helper_mtc0_lladdr(CPUMIPSState *env, target_ulo= ng arg1) { target_long mask =3D env->CP0_LLAddr_rw_bitmask; arg1 =3D arg1 << env->CP0_LLAddr_shift; - env->lladdr =3D (env->lladdr & ~mask) | (arg1 & mask); + env->CP0_LLAddr =3D (env->CP0_LLAddr & ~mask) | (arg1 & mask); } =20 #define MTC0_MAAR_MASK(env) \ @@ -2318,6 +2322,7 @@ static inline void exception_return(CPUMIPSState *env) void helper_eret(CPUMIPSState *env) { exception_return(env); + env->CP0_LLAddr =3D 1; env->lladdr =3D 1; } =20 diff --git a/target/mips/translate.c b/target/mips/translate.c index d05ee67..c9104a7 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -4913,7 +4913,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) case 17: switch (sel) { case 0: - gen_mfhc0_load64(arg, offsetof(CPUMIPSState, lladdr), + gen_mfhc0_load64(arg, offsetof(CPUMIPSState, CP0_LLAddr), ctx->CP0_LLAddr_shift); rn =3D "LLAddr"; break; @@ -20440,7 +20440,7 @@ void mips_cpu_dump_state(CPUState *cs, FILE *f, fpr= intf_function cpu_fprintf, env->CP0_Status, env->CP0_Cause, env->CP0_EPC); cpu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%016" PRIx64 "\n", - env->CP0_Config0, env->CP0_Config1, env->lladdr); + env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr); cpu_fprintf(f, " Config2 0x%08x Config3 0x%08x\n", env->CP0_Config2, env->CP0_Config3); cpu_fprintf(f, " Config4 0x%08x Config5 0x%08x\n", --=20 2.7.4 From nobody Wed Oct 22 13:03:25 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519324504513369.7266681881051; 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Thu, 22 Feb 2018 19:32:06 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 22 Feb 2018 19:31:39 +0100 Message-Id: <1519324303-5674-3-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1519324303-5674-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1519324303-5674-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v2 2/6] target/mips: reimplement SC instruction emulation and use cmpxchg X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Petar Jovanovic , Fam Zheng , Aleksandar Markovic , Raghu Gandham , Yongbok Kim , Riku Voipio , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Gerd Hoffmann , Goran Ferenc , Paolo Bonzini , Miodrag Dinic , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Leon Alrae Completely rewrite conditional stores handling. Use cmpxchg. This eliminates need for separate implementations of SC instruction emulation for user and system emulation. Signed-off-by: Leon Alrae Signed-off-by: Miodrag Dinic Signed-off-by: Aleksandar Markovic Reviewed-by: Richard Henderson Acked-by: Alex Benn=C3=A9e Tested-by: Emilio G. Cota --- linux-user/main.c | 58 ------------------------ target/mips/cpu.h | 4 -- target/mips/helper.c | 6 +-- target/mips/helper.h | 2 - target/mips/op_helper.c | 25 ----------- target/mips/translate.c | 114 ++++++++++++++++----------------------------= ---- 6 files changed, 39 insertions(+), 170 deletions(-) diff --git a/linux-user/main.c b/linux-user/main.c index fd79006..cef076f 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -2160,55 +2160,6 @@ static const uint8_t mips_syscall_args[] =3D { # undef MIPS_SYS # endif /* O32 */ =20 -static int do_store_exclusive(CPUMIPSState *env) -{ - target_ulong addr; - target_ulong page_addr; - target_ulong val; - int flags; - int segv =3D 0; - int reg; - int d; - - addr =3D env->lladdr; - page_addr =3D addr & TARGET_PAGE_MASK; - start_exclusive(); - mmap_lock(); - flags =3D page_get_flags(page_addr); - if ((flags & PAGE_READ) =3D=3D 0) { - segv =3D 1; - } else { - reg =3D env->llreg & 0x1f; - d =3D (env->llreg & 0x20) !=3D 0; - if (d) { - segv =3D get_user_s64(val, addr); - } else { - segv =3D get_user_s32(val, addr); - } - if (!segv) { - if (val !=3D env->llval) { - env->active_tc.gpr[reg] =3D 0; - } else { - if (d) { - segv =3D put_user_u64(env->llnewval, addr); - } else { - segv =3D put_user_u32(env->llnewval, addr); - } - if (!segv) { - env->active_tc.gpr[reg] =3D 1; - } - } - } - } - env->lladdr =3D -1; - if (!segv) { - env->active_tc.PC +=3D 4; - } - mmap_unlock(); - end_exclusive(); - return segv; -} - /* Break codes */ enum { BRK_OVERFLOW =3D 6, @@ -2358,15 +2309,6 @@ done_syscall: } } break; - case EXCP_SC: - if (do_store_exclusive(env)) { - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - info.si_code =3D TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr =3D env->active_tc.PC; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; case EXCP_DSPDIS: info.si_signo =3D TARGET_SIGILL; info.si_errno =3D 0; diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 57ca861..3fa85b0 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -486,8 +486,6 @@ struct CPUMIPSState { /* XXX: Maybe make LLAddr per-TC? */ target_ulong lladdr; /* LL virtual address compared against SC */ target_ulong llval; - target_ulong llnewval; - target_ulong llreg; uint64_t CP0_LLAddr_rw_bitmask; int CP0_LLAddr_shift; target_ulong CP0_WatchLo[8]; @@ -727,8 +725,6 @@ enum { =20 EXCP_LAST =3D EXCP_TLBRI, }; -/* Dummy exception for conditional stores. */ -#define EXCP_SC 0x100 =20 /* * This is an internally generated WAKE request line. diff --git a/target/mips/helper.c b/target/mips/helper.c index 8cf91ce..5002eb2 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -1084,10 +1084,8 @@ void QEMU_NORETURN do_raise_exception_err(CPUMIPSSta= te *env, { CPUState *cs =3D CPU(mips_env_get_cpu(env)); =20 - if (exception < EXCP_SC) { - qemu_log_mask(CPU_LOG_INT, "%s: %d %d\n", - __func__, exception, error_code); - } + qemu_log_mask(CPU_LOG_INT, "%s: %d %d\n", + __func__, exception, error_code); cs->exception_index =3D exception; env->error_code =3D error_code; =20 diff --git a/target/mips/helper.h b/target/mips/helper.h index 5f49234..04c36e9 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -13,10 +13,8 @@ DEF_HELPER_4(swr, void, env, tl, tl, int) =20 #ifndef CONFIG_USER_ONLY DEF_HELPER_3(ll, tl, env, tl, int) -DEF_HELPER_4(sc, tl, env, tl, tl, int) #ifdef TARGET_MIPS64 DEF_HELPER_3(lld, tl, env, tl, int) -DEF_HELPER_4(scd, tl, env, tl, tl, int) #endif #endif =20 diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index cc5cd4e..44a9b06 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -284,31 +284,6 @@ HELPER_LD_ATOMIC(ll, lw, 0x3) HELPER_LD_ATOMIC(lld, ld, 0x7) #endif #undef HELPER_LD_ATOMIC - -#define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) = \ -target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1, = \ - target_ulong arg2, int mem_idx) = \ -{ = \ - target_long tmp; = \ - = \ - if (arg2 & almask) { = \ - env->CP0_BadVAddr =3D arg2; = \ - do_raise_exception(env, EXCP_AdES, GETPC()); = \ - } = \ - if (arg2 =3D=3D env->lladdr) { = \ - tmp =3D do_##ld_insn(env, arg2, mem_idx, GETPC()); = \ - if (tmp =3D=3D env->llval) { = \ - do_##st_insn(env, arg2, arg1, mem_idx, GETPC()); = \ - return 1; = \ - } = \ - } = \ - return 0; = \ -} -HELPER_ST_ATOMIC(sc, lw, sw, 0x3) -#ifdef TARGET_MIPS64 -HELPER_ST_ATOMIC(scd, ld, sd, 0x7) -#endif -#undef HELPER_ST_ATOMIC #endif =20 #ifdef TARGET_WORDS_BIGENDIAN diff --git a/target/mips/translate.c b/target/mips/translate.c index c9104a7..f851d41 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1383,6 +1383,7 @@ static TCGv_i32 hflags; static TCGv_i32 fpu_fcr0, fpu_fcr31; static TCGv_i64 fpu_f64[32]; static TCGv_i64 msa_wr_d[64]; +static TCGv cpu_lladdr, cpu_llval; =20 #include "exec/gen-icount.h" =20 @@ -2073,48 +2074,6 @@ OP_LD_ATOMIC(lld,ld64); #endif #undef OP_LD_ATOMIC =20 -#ifdef CONFIG_USER_ONLY -#define OP_ST_ATOMIC(insn,fname,ldname,almask) = \ -static inline void op_st_##insn(TCGv arg1, TCGv arg2, int rt, int mem_idx,= \ - DisasContext *ctx) = \ -{ = \ - TCGv t0 =3D tcg_temp_new(); = \ - TCGLabel *l1 =3D gen_new_label(); = \ - TCGLabel *l2 =3D gen_new_label(); = \ - = \ - tcg_gen_andi_tl(t0, arg2, almask); = \ - tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); = \ - tcg_gen_st_tl(arg2, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr)); = \ - generate_exception(ctx, EXCP_AdES); = \ - gen_set_label(l1); = \ - tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUMIPSState, lladdr)); = \ - tcg_gen_brcond_tl(TCG_COND_NE, arg2, t0, l2); = \ - tcg_gen_movi_tl(t0, rt | ((almask << 3) & 0x20)); = \ - tcg_gen_st_tl(t0, cpu_env, offsetof(CPUMIPSState, llreg)); = \ - tcg_gen_st_tl(arg1, cpu_env, offsetof(CPUMIPSState, llnewval)); = \ - generate_exception_end(ctx, EXCP_SC); = \ - gen_set_label(l2); = \ - tcg_gen_movi_tl(t0, 0); = \ - gen_store_gpr(t0, rt); = \ - tcg_temp_free(t0); = \ -} -#else -#define OP_ST_ATOMIC(insn,fname,ldname,almask) = \ -static inline void op_st_##insn(TCGv arg1, TCGv arg2, int rt, int mem_idx,= \ - DisasContext *ctx) = \ -{ = \ - TCGv t0 =3D tcg_temp_new(); = \ - gen_helper_1e2i(insn, t0, arg1, arg2, mem_idx); = \ - gen_store_gpr(t0, rt); = \ - tcg_temp_free(t0); = \ -} -#endif -OP_ST_ATOMIC(sc,st32,ld32s,0x3); -#if defined(TARGET_MIPS64) -OP_ST_ATOMIC(scd,st64,ld64,0x7); -#endif -#undef OP_ST_ATOMIC - static void gen_base_offset_addr (DisasContext *ctx, TCGv addr, int base, int16_t offset) { @@ -2401,37 +2360,34 @@ static void gen_st (DisasContext *ctx, uint32_t opc= , int rt, =20 =20 /* Store conditional */ -static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt, - int base, int16_t offset) +static void gen_st_cond(DisasContext *ctx, int rt, int base, int offset, + TCGMemOp tcg_mo) { - TCGv t0, t1; - int mem_idx =3D ctx->mem_idx; + TCGv addr, t0, val; + TCGLabel *l1 =3D gen_new_label(); + TCGLabel *done =3D gen_new_label(); + + t0 =3D tcg_temp_new(); + addr =3D tcg_temp_new(); + /* compare the address against that of the preceeding LL */ + gen_base_offset_addr(ctx, addr, base, offset); + tcg_gen_brcond_tl(TCG_COND_EQ, addr, cpu_lladdr, l1); + tcg_temp_free(addr); + tcg_gen_movi_tl(t0, 0); + gen_store_gpr(t0, rt); + tcg_gen_br(done); =20 -#ifdef CONFIG_USER_ONLY - t0 =3D tcg_temp_local_new(); - t1 =3D tcg_temp_local_new(); -#else - t0 =3D tcg_temp_new(); - t1 =3D tcg_temp_new(); -#endif - gen_base_offset_addr(ctx, t0, base, offset); - gen_load_gpr(t1, rt); - switch (opc) { -#if defined(TARGET_MIPS64) - case OPC_SCD: - case R6_OPC_SCD: - op_st_scd(t1, t0, rt, mem_idx, ctx); - break; -#endif - case OPC_SCE: - mem_idx =3D MIPS_HFLAG_UM; - /* fall through */ - case OPC_SC: - case R6_OPC_SC: - op_st_sc(t1, t0, rt, mem_idx, ctx); - break; - } - tcg_temp_free(t1); + gen_set_label(l1); + /* generate cmpxchg */ + val =3D tcg_temp_new(); + gen_load_gpr(val, rt); + tcg_gen_atomic_cmpxchg_tl(t0, cpu_lladdr, cpu_llval, val, + ctx->mem_idx, tcg_mo); + tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_llval); + gen_store_gpr(t0, rt); + tcg_temp_free(val); + + gen_set_label(done); tcg_temp_free(t0); } =20 @@ -14889,13 +14845,13 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) gen_st(ctx, mips32_op, rt, rs, offset); break; case SC: - gen_st_cond(ctx, OPC_SC, rt, rs, offset); + gen_st_cond(ctx, rt, rs, offset, MO_TESL); break; #if defined(TARGET_MIPS64) case SCD: check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); - gen_st_cond(ctx, OPC_SCD, rt, rs, offset); + gen_st_cond(ctx, rt, rs, offset, MO_TEQ); break; #endif case LD_EVA: @@ -17695,7 +17651,7 @@ static void decode_opc_special3_r6(CPUMIPSState *en= v, DisasContext *ctx) } break; case R6_OPC_SC: - gen_st_cond(ctx, op1, rt, rs, imm); + gen_st_cond(ctx, rt, rs, imm, MO_TESL); break; case R6_OPC_LL: gen_ld(ctx, op1, rt, rs, imm); @@ -17719,7 +17675,7 @@ static void decode_opc_special3_r6(CPUMIPSState *en= v, DisasContext *ctx) break; #if defined(TARGET_MIPS64) case R6_OPC_SCD: - gen_st_cond(ctx, op1, rt, rs, imm); + gen_st_cond(ctx, rt, rs, imm, MO_TEQ); break; case R6_OPC_LLD: gen_ld(ctx, op1, rt, rs, imm); @@ -19844,7 +19800,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_SC: check_insn(ctx, ISA_MIPS2); check_insn_opc_removed(ctx, ISA_MIPS32R6); - gen_st_cond(ctx, op, rt, rs, imm); + gen_st_cond(ctx, rt, rs, imm, MO_TESL); break; case OPC_CACHE: check_insn_opc_removed(ctx, ISA_MIPS32R6); @@ -20130,7 +20086,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) check_insn_opc_removed(ctx, ISA_MIPS32R6); check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); - gen_st_cond(ctx, op, rt, rs, imm); + gen_st_cond(ctx, rt, rs, imm, MO_TEQ); break; case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC, OPC_DADDI */ if (ctx->insn_flags & ISA_MIPS32R6) { @@ -20497,6 +20453,10 @@ void mips_tcg_init(void) fpu_fcr31 =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUMIPSState, active_fpu.f= cr31), "fcr31"); + cpu_lladdr =3D tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, llad= dr), + "lladdr"); + cpu_llval =3D tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, llval= ), + "llval"); } =20 #include "translate_init.c" --=20 2.7.4 From nobody Wed Oct 22 13:03:25 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 15193245045581.6555280713197362; Thu, 22 Feb 2018 10:35:04 -0800 (PST) Received: from localhost ([::1]:40372 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eovhm-0005zc-Ft for importer@patchew.org; Thu, 22 Feb 2018 13:34:54 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49298) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eovfW-0004eN-RC for qemu-devel@nongnu.org; Thu, 22 Feb 2018 13:32:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eovfT-0005tM-Mw for qemu-devel@nongnu.org; Thu, 22 Feb 2018 13:32:34 -0500 Received: from mx2.rt-rk.com ([89.216.37.149]:35097 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eovfT-0005QG-3s for qemu-devel@nongnu.org; Thu, 22 Feb 2018 13:32:31 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 975421A229D; Thu, 22 Feb 2018 19:32:06 +0100 (CET) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 6FD2B1A226E; Thu, 22 Feb 2018 19:32:06 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 22 Feb 2018 19:31:40 +0100 Message-Id: <1519324303-5674-4-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1519324303-5674-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1519324303-5674-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v2 3/6] hw/mips_int: hold BQL for all interrupt requests X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Petar Jovanovic , Fam Zheng , Aleksandar Markovic , Raghu Gandham , Yongbok Kim , Riku Voipio , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Gerd Hoffmann , Goran Ferenc , Paolo Bonzini , Miodrag Dinic , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Make sure BQL is held for all interrupt requests. For MTTCG-enabled configurations, handling soft and hard interrupts between vCPUs must be properly locked. By acquiring BQL, make sure all paths triggering an IRQ are synchronized. Signed-off-by: Miodrag Dinic Signed-off-by: Aleksandar Markovic Acked-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e --- hw/mips/mips_int.c | 12 ++++++++++++ target/mips/op_helper.c | 21 +++------------------ 2 files changed, 15 insertions(+), 18 deletions(-) diff --git a/hw/mips/mips_int.c b/hw/mips/mips_int.c index 48192d2..5ddeb15 100644 --- a/hw/mips/mips_int.c +++ b/hw/mips/mips_int.c @@ -21,6 +21,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/main-loop.h" #include "hw/hw.h" #include "hw/mips/cpudevs.h" #include "cpu.h" @@ -32,10 +33,17 @@ static void cpu_mips_irq_request(void *opaque, int irq,= int level) MIPSCPU *cpu =3D opaque; CPUMIPSState *env =3D &cpu->env; CPUState *cs =3D CPU(cpu); + bool locked =3D false; =20 if (irq < 0 || irq > 7) return; =20 + /* Make sure locking works even if BQL is already held by the caller */ + if (!qemu_mutex_iothread_locked()) { + locked =3D true; + qemu_mutex_lock_iothread(); + } + if (level) { env->CP0_Cause |=3D 1 << (irq + CP0Ca_IP); =20 @@ -56,6 +64,10 @@ static void cpu_mips_irq_request(void *opaque, int irq, = int level) } else { cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); } + + if (locked) { + qemu_mutex_unlock_iothread(); + } } =20 void cpu_mips_irq_init_cpu(MIPSCPU *cpu) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 44a9b06..6bd8e59 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -17,7 +17,6 @@ * License along with this library; if not, see . */ #include "qemu/osdep.h" -#include "qemu/main-loop.h" #include "cpu.h" #include "internal.h" #include "qemu/host-utils.h" @@ -809,11 +808,7 @@ target_ulong helper_mftc0_tcschefback(CPUMIPSState *en= v) =20 target_ulong helper_mfc0_count(CPUMIPSState *env) { - int32_t count; - qemu_mutex_lock_iothread(); - count =3D (int32_t) cpu_mips_get_count(env); - qemu_mutex_unlock_iothread(); - return count; + return (int32_t)cpu_mips_get_count(env); } =20 target_ulong helper_mftc0_entryhi(CPUMIPSState *env) @@ -1388,9 +1383,7 @@ void helper_mtc0_hwrena(CPUMIPSState *env, target_ulo= ng arg1) =20 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1) { - qemu_mutex_lock_iothread(); cpu_mips_store_count(env, arg1); - qemu_mutex_unlock_iothread(); } =20 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1) @@ -1439,9 +1432,7 @@ void helper_mttc0_entryhi(CPUMIPSState *env, target_u= long arg1) =20 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1) { - qemu_mutex_lock_iothread(); cpu_mips_store_compare(env, arg1); - qemu_mutex_unlock_iothread(); } =20 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1) @@ -1495,9 +1486,7 @@ void helper_mtc0_srsctl(CPUMIPSState *env, target_ulo= ng arg1) =20 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1) { - qemu_mutex_lock_iothread(); cpu_mips_store_cause(env, arg1); - qemu_mutex_unlock_iothread(); } =20 void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1) @@ -2339,16 +2328,12 @@ target_ulong helper_rdhwr_synci_step(CPUMIPSState *= env) =20 target_ulong helper_rdhwr_cc(CPUMIPSState *env) { - int32_t count; check_hwrena(env, 2, GETPC()); #ifdef CONFIG_USER_ONLY - count =3D env->CP0_Count; + return env->CP0_Count; #else - qemu_mutex_lock_iothread(); - count =3D (int32_t)cpu_mips_get_count(env); - qemu_mutex_unlock_iothread(); + return (int32_t)cpu_mips_get_count(env); #endif - return count; } =20 target_ulong helper_rdhwr_ccres(CPUMIPSState *env) --=20 2.7.4 From nobody Wed Oct 22 13:03:25 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519324632913911.8394447307082; Thu, 22 Feb 2018 10:37:12 -0800 (PST) Received: from localhost ([::1]:40400 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eovk0-0008A2-5v for importer@patchew.org; Thu, 22 Feb 2018 13:37:12 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49300) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eovfW-0004eP-RG for qemu-devel@nongnu.org; Thu, 22 Feb 2018 13:32:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eovfT-0005sR-Ay for qemu-devel@nongnu.org; Thu, 22 Feb 2018 13:32:34 -0500 Received: from mx2.rt-rk.com ([89.216.37.149]:35107 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eovfT-0005Qb-2I for qemu-devel@nongnu.org; Thu, 22 Feb 2018 13:32:31 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id ACEA91A229F; Thu, 22 Feb 2018 19:32:06 +0100 (CET) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 87D721A22A1; Thu, 22 Feb 2018 19:32:06 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 22 Feb 2018 19:31:41 +0100 Message-Id: <1519324303-5674-5-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1519324303-5674-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1519324303-5674-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v2 4/6] target/mips: hold BQL in mips_vpe_wake() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Petar Jovanovic , Fam Zheng , Aleksandar Markovic , Raghu Gandham , Yongbok Kim , Riku Voipio , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Gerd Hoffmann , Goran Ferenc , Paolo Bonzini , Miodrag Dinic , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Goran Ferenc Hold BQL whenever mips_vpe_wake() is invoked. Without this patch, MIPS MT with MTTCG enabled triggers an abort in tcg_handle_interrupt() due to an unlocked access to cpu_interrupt(). This patch makes sure that the BQL is held in this case. Signed-off-by: Goran Ferenc Signed-off-by: Miodrag Dinic Signed-off-by: Aleksandar Markovic Acked-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e --- target/mips/op_helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 6bd8e59..d71d916 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -17,6 +17,7 @@ * License along with this library; if not, see . */ #include "qemu/osdep.h" +#include "qemu/main-loop.h" #include "cpu.h" #include "internal.h" #include "qemu/host-utils.h" @@ -542,7 +543,9 @@ static inline void mips_vpe_wake(MIPSCPU *c) /* Don't set ->halted =3D 0 directly, let it be done via cpu_has_work because there might be other conditions that state that c should be sleeping. */ + qemu_mutex_lock_iothread(); cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE); + qemu_mutex_unlock_iothread(); } =20 static inline void mips_vpe_sleep(MIPSCPU *cpu) --=20 2.7.4 From nobody Wed Oct 22 13:03:25 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519324504514344.82308526739916; Thu, 22 Feb 2018 10:35:04 -0800 (PST) Received: from localhost ([::1]:40371 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eovhl-0005zH-Dq for importer@patchew.org; Thu, 22 Feb 2018 13:34:53 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49296) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eovfW-0004eM-Q2 for qemu-devel@nongnu.org; Thu, 22 Feb 2018 13:32:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eovfU-0005v4-Jv for qemu-devel@nongnu.org; Thu, 22 Feb 2018 13:32:34 -0500 Received: from mx2.rt-rk.com ([89.216.37.149]:36837 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eovfU-0005ss-CR for qemu-devel@nongnu.org; Thu, 22 Feb 2018 13:32:32 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id C2B4E1A22A2; Thu, 22 Feb 2018 19:32:06 +0100 (CET) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 9E8401A226E; Thu, 22 Feb 2018 19:32:06 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 22 Feb 2018 19:31:42 +0100 Message-Id: <1519324303-5674-6-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1519324303-5674-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1519324303-5674-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v2 5/6] hw/mips_cpc: kick a VP when putting it into Run state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Petar Jovanovic , Fam Zheng , Aleksandar Markovic , Raghu Gandham , Yongbok Kim , Riku Voipio , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Gerd Hoffmann , Goran Ferenc , Paolo Bonzini , Miodrag Dinic , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Miodrag Dinic While testing mttcg VP0 could get stuck in a loop waiting for other VPs to come up (which never actually happens). To fix this, kick VPs while they are being powered up by Cluster Power Controller in an async task which is triggered once the host thread is being spawned. Signed-off-by: Miodrag Dinic Signed-off-by: Leon Alrae Signed-off-by: Aleksandar Markovic Acked-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e --- hw/misc/mips_cpc.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/hw/misc/mips_cpc.c b/hw/misc/mips_cpc.c index 6d34574..712d842 100644 --- a/hw/misc/mips_cpc.c +++ b/hw/misc/mips_cpc.c @@ -30,6 +30,14 @@ static inline uint64_t cpc_vp_run_mask(MIPSCPCState *cpc) return (1ULL << cpc->num_vp) - 1; } =20 +static void mips_cpu_reset_async_work(CPUState *cs, run_on_cpu_data data) +{ + MIPSCPCState *cpc =3D (MIPSCPCState *) data.host_ptr; + + cpu_reset(cs); + cpc->vp_running |=3D 1ULL << cs->cpu_index; +} + static void cpc_run_vp(MIPSCPCState *cpc, uint64_t vp_run) { CPUState *cs =3D first_cpu; @@ -37,8 +45,13 @@ static void cpc_run_vp(MIPSCPCState *cpc, uint64_t vp_ru= n) CPU_FOREACH(cs) { uint64_t i =3D 1ULL << cs->cpu_index; if (i & vp_run & ~cpc->vp_running) { - cpu_reset(cs); - cpc->vp_running |=3D i; + /* + * To avoid racing with a CPU we are just kicking off. + * We do the final bit of preparation for the work in + * the target CPUs context. + */ + async_safe_run_on_cpu(cs, mips_cpu_reset_async_work, + RUN_ON_CPU_HOST_PTR(cpc)); } } } --=20 2.7.4 From nobody Wed Oct 22 13:03:25 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 151932450313646.86854283450725; Thu, 22 Feb 2018 10:35:03 -0800 (PST) Received: from localhost ([::1]:40373 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eovhn-00060h-9L for importer@patchew.org; Thu, 22 Feb 2018 13:34:55 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49299) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eovfW-0004eO-RN for qemu-devel@nongnu.org; Thu, 22 Feb 2018 13:32:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eovfU-0005up-IW for qemu-devel@nongnu.org; Thu, 22 Feb 2018 13:32:34 -0500 Received: from mx2.rt-rk.com ([89.216.37.149]:36826 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eovfU-0005sp-9q for qemu-devel@nongnu.org; Thu, 22 Feb 2018 13:32:32 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id DAD851A226E; Thu, 22 Feb 2018 19:32:06 +0100 (CET) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id B50D11A22A1; Thu, 22 Feb 2018 19:32:06 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 22 Feb 2018 19:31:43 +0100 Message-Id: <1519324303-5674-7-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1519324303-5674-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1519324303-5674-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v2 6/6] target/mips: introduce MTTCG-enabled builds X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Petar Jovanovic , Fam Zheng , Aleksandar Markovic , Raghu Gandham , Yongbok Kim , Riku Voipio , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Gerd Hoffmann , Goran Ferenc , Paolo Bonzini , Miodrag Dinic , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Introduce MTTCG-enabled QEMU builds for mips32, mipsn32, and mips64. Signed-off-by: Miodrag Dinic Signed-off-by: Aleksandar Markovic Acked-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e --- configure | 3 +++ target/mips/cpu.h | 2 ++ 2 files changed, 5 insertions(+) diff --git a/configure b/configure index ed45a3c..9b338dd 100755 --- a/configure +++ b/configure @@ -6735,16 +6735,19 @@ case "$target_name" in bflt=3D"yes" ;; mips|mipsel) + mttcg=3D"yes" TARGET_ARCH=3Dmips echo "TARGET_ABI_MIPSO32=3Dy" >> $config_target_mak ;; mipsn32|mipsn32el) + mttcg=3D"yes" TARGET_ARCH=3Dmips64 TARGET_BASE_ARCH=3Dmips echo "TARGET_ABI_MIPSN32=3Dy" >> $config_target_mak echo "TARGET_ABI32=3Dy" >> $config_target_mak ;; mips64|mips64el) + mttcg=3D"yes" TARGET_ARCH=3Dmips64 TARGET_BASE_ARCH=3Dmips echo "TARGET_ABI_MIPSN64=3Dy" >> $config_target_mak diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 3fa85b0..8f41952 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -11,6 +11,8 @@ #include "exec/cpu-defs.h" #include "fpu/softfloat.h" =20 +#define TCG_GUEST_DEFAULT_MO (0) + struct CPUMIPSState; =20 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext; --=20 2.7.4