From nobody Fri Oct 24 09:56:51 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519246744546373.89561775191794; Wed, 21 Feb 2018 12:59:04 -0800 (PST) Received: from localhost ([::1]:34751 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eobTj-00007J-Ee for importer@patchew.org; Wed, 21 Feb 2018 15:59:03 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55624) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eobRJ-0007gw-Ut for qemu-devel@nongnu.org; Wed, 21 Feb 2018 15:57:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eobQF-0004dh-Vo for qemu-devel@nongnu.org; Wed, 21 Feb 2018 15:56:33 -0500 Received: from out4-smtp.messagingengine.com ([66.111.4.28]:57089) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eobQF-0004c8-B2 for qemu-devel@nongnu.org; Wed, 21 Feb 2018 15:55:27 -0500 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 69FF720EC2; Wed, 21 Feb 2018 15:55:26 -0500 (EST) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Wed, 21 Feb 2018 15:55:26 -0500 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 1FC2E24519; Wed, 21 Feb 2018 15:55:26 -0500 (EST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc; s=mesmtp; bh=hfZKOD6VAiKVRL qonf4+YQNBu+EYajku5PXBnkc0HUg=; b=cTuMlpWVMHuVe6D9qtESsWQbaA+nWL L9LP65WHM00y+kaRLwPZGC+5Mf3sMZyuac2/1japYVpYWQsELFJlP7OBgJQX9eq8 RpMtJH9WfYMpD4qRMoSGEXpXTCCflCHX93zX+fSfZ1rFVp0cu5Wbrib9+pClrW6W 2HHrTB/zUirxc= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc; s= fm2; bh=hfZKOD6VAiKVRLqonf4+YQNBu+EYajku5PXBnkc0HUg=; b=l09doJaU 1ZrBydQF/ylHYjM6+YSVvAZ+m6P06RJLQga7zL+4qotfYg4QrGi86tuE4FSzZwzv lN3kOW1NgPJlFhKzw1s2Fmn0kYx1GbYjK0BkG6ccLxOl79IVHZzfIJA1scp6yVZ9 h0cDCK1b89ZTi/BG9mqvVa0j03LRnZAd/ma5uMjw5RD1lHjNfuH/efxXo1n2K4v9 GmOr04xyUXzPTGdtDWpDeUkrK4XM4NO/1c6hGFlFUM8t0LScqd9xskYfpyNgeZ2W D7TVHFS5rgVlYu4UM6t3/EbvGf3JysCMp2c4NDDQi/4lKcsXx7A3OouxJquy6yR2 Os5x9d8cokl+NQ== X-ME-Sender: From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 21 Feb 2018 15:55:08 -0500 Message-Id: <1519246509-4022-2-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1519246509-4022-1-git-send-email-cota@braap.org> References: <1519246509-4022-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.28 Subject: [Qemu-devel] [PATCHv3 1/2] translator: merge max_insns into DisasContextBase X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" While at it, use int for both num_insns and max_insns to make sure we have same-type comparisons. Signed-off-by: Emilio G. Cota Reviewed-by: Richard Henderson --- accel/tcg/translator.c | 21 ++++++++++----------- include/exec/translator.h | 8 ++++---- target/alpha/translate.c | 6 ++---- target/arm/translate-a64.c | 8 +++----- target/arm/translate.c | 9 +++------ target/hppa/translate.c | 7 ++----- target/i386/translate.c | 5 +---- target/ppc/translate.c | 5 ++--- 8 files changed, 27 insertions(+), 42 deletions(-) diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 23c6602..0f9dca9 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -34,8 +34,6 @@ void translator_loop_temp_check(DisasContextBase *db) void translator_loop(const TranslatorOps *ops, DisasContextBase *db, CPUState *cpu, TranslationBlock *tb) { - int max_insns; - /* Initialize DisasContext */ db->tb =3D tb; db->pc_first =3D tb->pc; @@ -45,18 +43,18 @@ void translator_loop(const TranslatorOps *ops, DisasCon= textBase *db, db->singlestep_enabled =3D cpu->singlestep_enabled; =20 /* Instruction counting */ - max_insns =3D tb_cflags(db->tb) & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; + db->max_insns =3D tb_cflags(db->tb) & CF_COUNT_MASK; + if (db->max_insns =3D=3D 0) { + db->max_insns =3D CF_COUNT_MASK; } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; + if (db->max_insns > TCG_MAX_INSNS) { + db->max_insns =3D TCG_MAX_INSNS; } if (db->singlestep_enabled || singlestep) { - max_insns =3D 1; + db->max_insns =3D 1; } =20 - max_insns =3D ops->init_disas_context(db, cpu, max_insns); + ops->init_disas_context(db, cpu); tcg_debug_assert(db->is_jmp =3D=3D DISAS_NEXT); /* no early exit */ =20 /* Reset the temp count so that we can identify leaks */ @@ -95,7 +93,8 @@ void translator_loop(const TranslatorOps *ops, DisasConte= xtBase *db, update db->pc_next and db->is_jmp to indicate what should be done next -- either exiting this loop or locate the start of the next instruction. */ - if (db->num_insns =3D=3D max_insns && (tb_cflags(db->tb) & CF_LAST= _IO)) { + if (db->num_insns =3D=3D db->max_insns + && (tb_cflags(db->tb) & CF_LAST_IO)) { /* Accept I/O on the last instruction. */ gen_io_start(); ops->translate_insn(db, cpu); @@ -111,7 +110,7 @@ void translator_loop(const TranslatorOps *ops, DisasCon= textBase *db, =20 /* Stop translation if the output buffer is full, or we have executed all of the allowed instructions. */ - if (tcg_op_buf_full() || db->num_insns >=3D max_insns) { + if (tcg_op_buf_full() || db->num_insns >=3D db->max_insns) { db->is_jmp =3D DISAS_TOO_MANY; break; } diff --git a/include/exec/translator.h b/include/exec/translator.h index e2dc2a0..71e7b2c 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -58,6 +58,7 @@ typedef enum DisasJumpType { * disassembly). * @is_jmp: What instruction to disassemble next. * @num_insns: Number of translated instructions (including current). + * @max_insns: Maximum number of instructions to be translated in this TB. * @singlestep_enabled: "Hardware" single stepping enabled. * * Architecture-agnostic disassembly context. @@ -67,7 +68,8 @@ typedef struct DisasContextBase { target_ulong pc_first; target_ulong pc_next; DisasJumpType is_jmp; - unsigned int num_insns; + int num_insns; + int max_insns; bool singlestep_enabled; } DisasContextBase; =20 @@ -76,7 +78,6 @@ typedef struct DisasContextBase { * @init_disas_context: * Initialize the target-specific portions of DisasContext struct. * The generic DisasContextBase has already been initialized. - * Return max_insns, modified as necessary by db->tb->flags. * * @tb_start: * Emit any code required before the start of the main loop, @@ -106,8 +107,7 @@ typedef struct DisasContextBase { * Print instruction disassembly to log. */ typedef struct TranslatorOps { - int (*init_disas_context)(DisasContextBase *db, CPUState *cpu, - int max_insns); + void (*init_disas_context)(DisasContextBase *db, CPUState *cpu); void (*tb_start)(DisasContextBase *db, CPUState *cpu); void (*insn_start)(DisasContextBase *db, CPUState *cpu); bool (*breakpoint_check)(DisasContextBase *db, CPUState *cpu, diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 73a1b5e..15eca71 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -2919,8 +2919,7 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) return ret; } =20 -static int alpha_tr_init_disas_context(DisasContextBase *dcbase, - CPUState *cpu, int max_insns) +static void alpha_tr_init_disas_context(DisasContextBase *dcbase, CPUState= *cpu) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); CPUAlphaState *env =3D cpu->env_ptr; @@ -2959,8 +2958,7 @@ static int alpha_tr_init_disas_context(DisasContextBa= se *dcbase, mask =3D TARGET_PAGE_MASK; } bound =3D -(ctx->base.pc_first | mask) / 4; - - return MIN(max_insns, bound); + ctx->base.max_insns =3D MIN(ctx->base.max_insns, bound); } =20 static void alpha_tr_tb_start(DisasContextBase *db, CPUState *cpu) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 1c88539..55f00a6 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -12009,8 +12009,8 @@ static void disas_a64_insn(CPUARMState *env, DisasC= ontext *s) free_tmp_a64(s); } =20 -static int aarch64_tr_init_disas_context(DisasContextBase *dcbase, - CPUState *cpu, int max_insns) +static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, + CPUState *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); CPUARMState *env =3D cpu->env_ptr; @@ -12073,11 +12073,9 @@ static int aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, if (dc->ss_active) { bound =3D 1; } - max_insns =3D MIN(max_insns, bound); + dc->base.max_insns =3D MIN(dc->base.max_insns, bound); =20 init_tmp_a64_array(dc); - - return max_insns; } =20 static void aarch64_tr_tb_start(DisasContextBase *db, CPUState *cpu) diff --git a/target/arm/translate.c b/target/arm/translate.c index 1270022..9284975 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11975,8 +11975,7 @@ static bool insn_crosses_page(CPUARMState *env, Dis= asContext *s) return !thumb_insn_is_16bit(s, insn); } =20 -static int arm_tr_init_disas_context(DisasContextBase *dcbase, - CPUState *cs, int max_insns) +static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *= cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); CPUARMState *env =3D cs->env_ptr; @@ -12038,14 +12037,14 @@ static int arm_tr_init_disas_context(DisasContext= Base *dcbase, =20 /* If architectural single step active, limit to 1. */ if (is_singlestepping(dc)) { - max_insns =3D 1; + dc->base.max_insns =3D 1; } =20 /* ARM is a fixed-length ISA. Bound the number of insns to execute to those left on the page. */ if (!dc->thumb) { int bound =3D (dc->next_page_start - dc->base.pc_first) / 4; - max_insns =3D MIN(max_insns, bound); + dc->base.max_insns =3D MIN(dc->base.max_insns, bound); } =20 cpu_F0s =3D tcg_temp_new_i32(); @@ -12056,8 +12055,6 @@ static int arm_tr_init_disas_context(DisasContextBa= se *dcbase, cpu_V1 =3D cpu_F1d; /* FIXME: cpu_M0 can probably be the same as cpu_V0. */ cpu_M0 =3D tcg_temp_new_i64(); - - return max_insns; } =20 static void arm_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 6499b39..1afca76 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -4685,8 +4685,7 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) return gen_illegal(ctx); } =20 -static int hppa_tr_init_disas_context(DisasContextBase *dcbase, - CPUState *cs, int max_insns) +static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState = *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); int bound; @@ -4716,14 +4715,12 @@ static int hppa_tr_init_disas_context(DisasContextB= ase *dcbase, =20 /* Bound the number of instructions by those left on the page. */ bound =3D -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; - bound =3D MIN(max_insns, bound); + ctx->base.max_insns =3D MIN(ctx->base.max_insns, bound); =20 ctx->ntempr =3D 0; ctx->ntempl =3D 0; memset(ctx->tempr, 0, sizeof(ctx->tempr)); memset(ctx->templ, 0, sizeof(ctx->templ)); - - return bound; } =20 static void hppa_tr_tb_start(DisasContextBase *dcbase, CPUState *cs) diff --git a/target/i386/translate.c b/target/i386/translate.c index 0135415..a462913 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8400,8 +8400,7 @@ void tcg_x86_init(void) } } =20 -static int i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *= cpu, - int max_insns) +static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState = *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); CPUX86State *env =3D cpu->env_ptr; @@ -8468,8 +8467,6 @@ static int i386_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cpu, cpu_ptr0 =3D tcg_temp_new_ptr(); cpu_ptr1 =3D tcg_temp_new_ptr(); cpu_cc_srcT =3D tcg_temp_local_new(); - - return max_insns; } =20 static void i386_tr_tb_start(DisasContextBase *db, CPUState *cpu) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 0a0c090..b5a0dd7 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7207,8 +7207,7 @@ void ppc_cpu_dump_statistics(CPUState *cs, FILE*f, #endif } =20 -static int ppc_tr_init_disas_context(DisasContextBase *dcbase, - CPUState *cs, int max_insns) +static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *= cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); CPUPPCState *env =3D cs->env_ptr; @@ -7274,7 +7273,7 @@ static int ppc_tr_init_disas_context(DisasContextBase= *dcbase, #endif =20 bound =3D -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; - return MIN(max_insns, bound); + ctx->base.max_insns =3D MIN(ctx->base.max_insns, bound); } =20 static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) --=20 2.7.4 From nobody Fri Oct 24 09:56:51 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519246927378867.0830387340238; Wed, 21 Feb 2018 13:02:07 -0800 (PST) Received: from localhost ([::1]:34772 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eobWg-0002AV-Jz for importer@patchew.org; Wed, 21 Feb 2018 16:02:06 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60291) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eobTy-0000YZ-8w for qemu-devel@nongnu.org; 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Cota" To: qemu-devel@nongnu.org Date: Wed, 21 Feb 2018 15:55:09 -0500 Message-Id: <1519246509-4022-3-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1519246509-4022-1-git-send-email-cota@braap.org> References: <1519246509-4022-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.28 Subject: [Qemu-devel] [PATCHv3 2/2] target/sh4: convert to TranslatorOps X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This was fairly straightforward since it had already been converted to DisasContextBase; just had to add TARGET_TOO_MANY to the switch in tb_stop. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- target/sh4/translate.c | 171 +++++++++++++++++++++++++--------------------= ---- 1 file changed, 86 insertions(+), 85 deletions(-) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 012156b..58bdfeb 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -2258,126 +2258,127 @@ static int decode_gusa(DisasContext *ctx, CPUSH4S= tate *env, int *pmax_insns) } #endif =20 -void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) +static void sh4_tr_init_disas_context(DisasContextBase *dcbase, CPUState *= cs) { + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); CPUSH4State *env =3D cs->env_ptr; - DisasContext ctx; - target_ulong pc_start; - int num_insns; - int max_insns; - - pc_start =3D tb->pc; - ctx.base.pc_next =3D pc_start; - ctx.tbflags =3D (uint32_t)tb->flags; - ctx.envflags =3D tb->flags & TB_FLAG_ENVFLAGS_MASK; - ctx.base.is_jmp =3D DISAS_NEXT; - ctx.memidx =3D (ctx.tbflags & (1u << SR_MD)) =3D=3D 0 ? 1 : 0; + int bound; + + ctx->tbflags =3D (uint32_t)ctx->base.tb->flags; + ctx->envflags =3D ctx->base.tb->flags & TB_FLAG_ENVFLAGS_MASK; + ctx->memidx =3D (ctx->tbflags & (1u << SR_MD)) =3D=3D 0 ? 1 : 0; /* We don't know if the delayed pc came from a dynamic or static branc= h, so assume it is a dynamic branch. */ - ctx.delayed_pc =3D -1; /* use delayed pc from env pointer */ - ctx.base.tb =3D tb; - ctx.base.singlestep_enabled =3D cs->singlestep_enabled; - ctx.features =3D env->features; - ctx.has_movcal =3D (ctx.tbflags & TB_FLAG_PENDING_MOVCA); - ctx.gbank =3D ((ctx.tbflags & (1 << SR_MD)) && - (ctx.tbflags & (1 << SR_RB))) * 0x10; - ctx.fbank =3D ctx.tbflags & FPSCR_FR ? 0x10 : 0; - - max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - max_insns =3D MIN(max_insns, TCG_MAX_INSNS); + ctx->delayed_pc =3D -1; /* use delayed pc from env pointer */ + ctx->features =3D env->features; + ctx->has_movcal =3D (ctx->tbflags & TB_FLAG_PENDING_MOVCA); + ctx->gbank =3D ((ctx->tbflags & (1 << SR_MD)) && + (ctx->tbflags & (1 << SR_RB))) * 0x10; + ctx->fbank =3D ctx->tbflags & FPSCR_FR ? 0x10 : 0; =20 /* Since the ISA is fixed-width, we can bound by the number of instructions remaining on the page. */ - num_insns =3D -(ctx.base.pc_next | TARGET_PAGE_MASK) / 2; - max_insns =3D MIN(max_insns, num_insns); - - /* Single stepping means just that. */ - if (ctx.base.singlestep_enabled || singlestep) { - max_insns =3D 1; - } - - gen_tb_start(tb); - num_insns =3D 0; + bound =3D -(ctx->base.pc_next | TARGET_PAGE_MASK) / 2; + ctx->base.max_insns =3D MIN(ctx->base.max_insns, bound); +} =20 +static void sh4_tr_tb_start(DisasContextBase *dcbase, CPUState *cs) +{ #ifdef CONFIG_USER_ONLY - if (ctx.tbflags & GUSA_MASK) { - num_insns =3D decode_gusa(&ctx, env, &max_insns); + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); + CPUSH4State *env =3D cs->env_ptr; + + if (ctx->tbflags & GUSA_MASK) { + ctx->base.num_insns =3D decode_gusa(ctx, env, &ctx->base.max_insns= ); } #endif +} =20 - while (ctx.base.is_jmp =3D=3D DISAS_NEXT - && num_insns < max_insns - && !tcg_op_buf_full()) { - tcg_gen_insn_start(ctx.base.pc_next, ctx.envflags); - num_insns++; +static void sh4_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - if (unlikely(cpu_breakpoint_test(cs, ctx.base.pc_next, BP_ANY))) { - /* We have hit a breakpoint - make sure PC is up-to-date */ - gen_save_cpu_state(&ctx, true); - gen_helper_debug(cpu_env); - ctx.base.is_jmp =3D DISAS_NORETURN; - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - ctx.base.pc_next +=3D 2; - break; - } + tcg_gen_insn_start(ctx->base.pc_next, ctx->envflags); +} =20 - if (num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAST_IO)) { - gen_io_start(); - } +static bool sh4_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, + const CPUBreakpoint *bp) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - ctx.opcode =3D cpu_lduw_code(env, ctx.base.pc_next); - decode_opc(&ctx); - ctx.base.pc_next +=3D 2; - } - if (tb_cflags(tb) & CF_LAST_IO) { - gen_io_end(); - } + /* We have hit a breakpoint - make sure PC is up-to-date */ + gen_save_cpu_state(ctx, true); + gen_helper_debug(cpu_env); + ctx->base.is_jmp =3D DISAS_NORETURN; + /* The address covered by the breakpoint must be included in + [tb->pc, tb->pc + tb->size) in order to for it to be + properly cleared -- thus we increment the PC here so that + the logic setting tb->size below does the right thing. */ + ctx->base.pc_next +=3D 2; + return true; +} + +static void sh4_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) +{ + CPUSH4State *env =3D cs->env_ptr; + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - if (ctx.tbflags & GUSA_EXCLUSIVE) { + ctx->opcode =3D cpu_lduw_code(env, ctx->base.pc_next); + decode_opc(ctx); + ctx->base.pc_next +=3D 2; +} + +static void sh4_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); + + if (ctx->tbflags & GUSA_EXCLUSIVE) { /* Ending the region of exclusivity. Clear the bits. */ - ctx.envflags &=3D ~GUSA_MASK; + ctx->envflags &=3D ~GUSA_MASK; } =20 - switch (ctx.base.is_jmp) { + switch (ctx->base.is_jmp) { case DISAS_STOP: - gen_save_cpu_state(&ctx, true); - if (ctx.base.singlestep_enabled) { + gen_save_cpu_state(ctx, true); + if (ctx->base.singlestep_enabled) { gen_helper_debug(cpu_env); } else { tcg_gen_exit_tb(0); } break; case DISAS_NEXT: - gen_save_cpu_state(&ctx, false); - gen_goto_tb(&ctx, 0, ctx.base.pc_next); + case DISAS_TOO_MANY: + gen_save_cpu_state(ctx, false); + gen_goto_tb(ctx, 0, ctx->base.pc_next); break; case DISAS_NORETURN: break; default: g_assert_not_reached(); } +} =20 - gen_tb_end(tb, num_insns); +static void sh4_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) +{ + qemu_log("IN:\n"); /* , lookup_symbol(dcbase->pc_first)); */ + log_target_disas(cs, dcbase->pc_first, dcbase->tb->size); +} =20 - tb->size =3D ctx.base.pc_next - pc_start; - tb->icount =3D num_insns; +static const TranslatorOps sh4_tr_ops =3D { + .init_disas_context =3D sh4_tr_init_disas_context, + .tb_start =3D sh4_tr_tb_start, + .insn_start =3D sh4_tr_insn_start, + .breakpoint_check =3D sh4_tr_breakpoint_check, + .translate_insn =3D sh4_tr_translate_insn, + .tb_stop =3D sh4_tr_tb_stop, + .disas_log =3D sh4_tr_disas_log, +}; + +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +{ + DisasContext ctx; =20 -#ifdef DEBUG_DISAS - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(pc_start)) { - qemu_log_lock(); - qemu_log("IN:\n"); /* , lookup_symbol(pc_start)); */ - log_target_disas(cs, pc_start, ctx.base.pc_next - pc_start); - qemu_log("\n"); - qemu_log_unlock(); - } -#endif + translator_loop(&sh4_tr_ops, &ctx.base, cs, tb); } =20 void restore_state_to_opc(CPUSH4State *env, TranslationBlock *tb, --=20 2.7.4