From nobody Fri Oct 24 22:17:01 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519093726467977.7291764479857; Mon, 19 Feb 2018 18:28:46 -0800 (PST) Received: from localhost ([::1]:53241 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1enxfY-0008RS-QH for importer@patchew.org; Mon, 19 Feb 2018 21:28:36 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42162) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1enxe9-0007nn-0j for qemu-devel@nongnu.org; Mon, 19 Feb 2018 21:27:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1enxe4-0000GT-Cp for qemu-devel@nongnu.org; Mon, 19 Feb 2018 21:27:08 -0500 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:50941) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1enxe4-0000G9-7P for qemu-devel@nongnu.org; Mon, 19 Feb 2018 21:27:04 -0500 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id E308820F3A; Mon, 19 Feb 2018 21:27:03 -0500 (EST) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Mon, 19 Feb 2018 21:27:03 -0500 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id A20B27E140; Mon, 19 Feb 2018 21:27:03 -0500 (EST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc; s=mesmtp; bh=YEvDenJIZAcY0U 3488595+BIfSnfd4L5vbx9mKhFahY=; b=M+YJAK268NNn79oT1CHYdDT05RxLpn 6BhDi4zTt7scFRwdYP+kXKScfSuzf1Q825k48OkQSZm1cCypfZnmBj0j/iO/nfYM Kj+r5W4CrDAZScap3UfDT3u2RY6j+wq33DVI/E1dQBuv9B7ZuHmcAP6lxn+oA0+/ 5jmfWctzAXV5c= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc; s= fm2; bh=YEvDenJIZAcY0U3488595+BIfSnfd4L5vbx9mKhFahY=; b=DVETe9PO sTJIXrLYPAmUEiUsQoi0RmdkhEs6sKBBCKg+BfZ9qUtlDoL8ONPUs/W+nA99MyFE 2uimnp39OPvHl9dnUNNbWZNwTCZXvUwhKROyvR0hz7xwdgfvlQmudQqt+PNhGFK5 y5AUshmXMbJIUUrMIN5bnusrDrRPLfW9lRs4dd7pWeflYotSN0Sv3jX6ITqSa86T 0SmpFfflkRv7GMkmQfCz3SV9L2H+9kIFTlgTbPHJfXmQARiqz5/RQ7gbYwQUM1HZ pJS8rDArvEh7JT/7nTwggHQNLHj3H/3ZEEjxcRlOIp25KqOBZk0TuoiEOwmVX6R/ d1N1bFtsiob36w== X-ME-Sender: From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Mon, 19 Feb 2018 21:26:56 -0500 Message-Id: <1519093616-10563-3-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1519093616-10563-1-git-send-email-cota@braap.org> References: <1519093616-10563-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCHv2 2/2] target/sh4: convert to TranslatorOps X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This was fairly straightforward since it had already been converted to DisasContextBase; just had to add TARGET_TOO_MANY to the switch in tb_stop. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- target/sh4/translate.c | 171 +++++++++++++++++++++++++--------------------= ---- 1 file changed, 86 insertions(+), 85 deletions(-) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 012156b..58bdfeb 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -2258,126 +2258,127 @@ static int decode_gusa(DisasContext *ctx, CPUSH4S= tate *env, int *pmax_insns) } #endif =20 -void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) +static void sh4_tr_init_disas_context(DisasContextBase *dcbase, CPUState *= cs) { + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); CPUSH4State *env =3D cs->env_ptr; - DisasContext ctx; - target_ulong pc_start; - int num_insns; - int max_insns; - - pc_start =3D tb->pc; - ctx.base.pc_next =3D pc_start; - ctx.tbflags =3D (uint32_t)tb->flags; - ctx.envflags =3D tb->flags & TB_FLAG_ENVFLAGS_MASK; - ctx.base.is_jmp =3D DISAS_NEXT; - ctx.memidx =3D (ctx.tbflags & (1u << SR_MD)) =3D=3D 0 ? 1 : 0; + int bound; + + ctx->tbflags =3D (uint32_t)ctx->base.tb->flags; + ctx->envflags =3D ctx->base.tb->flags & TB_FLAG_ENVFLAGS_MASK; + ctx->memidx =3D (ctx->tbflags & (1u << SR_MD)) =3D=3D 0 ? 1 : 0; /* We don't know if the delayed pc came from a dynamic or static branc= h, so assume it is a dynamic branch. */ - ctx.delayed_pc =3D -1; /* use delayed pc from env pointer */ - ctx.base.tb =3D tb; - ctx.base.singlestep_enabled =3D cs->singlestep_enabled; - ctx.features =3D env->features; - ctx.has_movcal =3D (ctx.tbflags & TB_FLAG_PENDING_MOVCA); - ctx.gbank =3D ((ctx.tbflags & (1 << SR_MD)) && - (ctx.tbflags & (1 << SR_RB))) * 0x10; - ctx.fbank =3D ctx.tbflags & FPSCR_FR ? 0x10 : 0; - - max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - max_insns =3D MIN(max_insns, TCG_MAX_INSNS); + ctx->delayed_pc =3D -1; /* use delayed pc from env pointer */ + ctx->features =3D env->features; + ctx->has_movcal =3D (ctx->tbflags & TB_FLAG_PENDING_MOVCA); + ctx->gbank =3D ((ctx->tbflags & (1 << SR_MD)) && + (ctx->tbflags & (1 << SR_RB))) * 0x10; + ctx->fbank =3D ctx->tbflags & FPSCR_FR ? 0x10 : 0; =20 /* Since the ISA is fixed-width, we can bound by the number of instructions remaining on the page. */ - num_insns =3D -(ctx.base.pc_next | TARGET_PAGE_MASK) / 2; - max_insns =3D MIN(max_insns, num_insns); - - /* Single stepping means just that. */ - if (ctx.base.singlestep_enabled || singlestep) { - max_insns =3D 1; - } - - gen_tb_start(tb); - num_insns =3D 0; + bound =3D -(ctx->base.pc_next | TARGET_PAGE_MASK) / 2; + ctx->base.max_insns =3D MIN(ctx->base.max_insns, bound); +} =20 +static void sh4_tr_tb_start(DisasContextBase *dcbase, CPUState *cs) +{ #ifdef CONFIG_USER_ONLY - if (ctx.tbflags & GUSA_MASK) { - num_insns =3D decode_gusa(&ctx, env, &max_insns); + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); + CPUSH4State *env =3D cs->env_ptr; + + if (ctx->tbflags & GUSA_MASK) { + ctx->base.num_insns =3D decode_gusa(ctx, env, &ctx->base.max_insns= ); } #endif +} =20 - while (ctx.base.is_jmp =3D=3D DISAS_NEXT - && num_insns < max_insns - && !tcg_op_buf_full()) { - tcg_gen_insn_start(ctx.base.pc_next, ctx.envflags); - num_insns++; +static void sh4_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - if (unlikely(cpu_breakpoint_test(cs, ctx.base.pc_next, BP_ANY))) { - /* We have hit a breakpoint - make sure PC is up-to-date */ - gen_save_cpu_state(&ctx, true); - gen_helper_debug(cpu_env); - ctx.base.is_jmp =3D DISAS_NORETURN; - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - ctx.base.pc_next +=3D 2; - break; - } + tcg_gen_insn_start(ctx->base.pc_next, ctx->envflags); +} =20 - if (num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAST_IO)) { - gen_io_start(); - } +static bool sh4_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, + const CPUBreakpoint *bp) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - ctx.opcode =3D cpu_lduw_code(env, ctx.base.pc_next); - decode_opc(&ctx); - ctx.base.pc_next +=3D 2; - } - if (tb_cflags(tb) & CF_LAST_IO) { - gen_io_end(); - } + /* We have hit a breakpoint - make sure PC is up-to-date */ + gen_save_cpu_state(ctx, true); + gen_helper_debug(cpu_env); + ctx->base.is_jmp =3D DISAS_NORETURN; + /* The address covered by the breakpoint must be included in + [tb->pc, tb->pc + tb->size) in order to for it to be + properly cleared -- thus we increment the PC here so that + the logic setting tb->size below does the right thing. */ + ctx->base.pc_next +=3D 2; + return true; +} + +static void sh4_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) +{ + CPUSH4State *env =3D cs->env_ptr; + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - if (ctx.tbflags & GUSA_EXCLUSIVE) { + ctx->opcode =3D cpu_lduw_code(env, ctx->base.pc_next); + decode_opc(ctx); + ctx->base.pc_next +=3D 2; +} + +static void sh4_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); + + if (ctx->tbflags & GUSA_EXCLUSIVE) { /* Ending the region of exclusivity. Clear the bits. */ - ctx.envflags &=3D ~GUSA_MASK; + ctx->envflags &=3D ~GUSA_MASK; } =20 - switch (ctx.base.is_jmp) { + switch (ctx->base.is_jmp) { case DISAS_STOP: - gen_save_cpu_state(&ctx, true); - if (ctx.base.singlestep_enabled) { + gen_save_cpu_state(ctx, true); + if (ctx->base.singlestep_enabled) { gen_helper_debug(cpu_env); } else { tcg_gen_exit_tb(0); } break; case DISAS_NEXT: - gen_save_cpu_state(&ctx, false); - gen_goto_tb(&ctx, 0, ctx.base.pc_next); + case DISAS_TOO_MANY: + gen_save_cpu_state(ctx, false); + gen_goto_tb(ctx, 0, ctx->base.pc_next); break; case DISAS_NORETURN: break; default: g_assert_not_reached(); } +} =20 - gen_tb_end(tb, num_insns); +static void sh4_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) +{ + qemu_log("IN:\n"); /* , lookup_symbol(dcbase->pc_first)); */ + log_target_disas(cs, dcbase->pc_first, dcbase->tb->size); +} =20 - tb->size =3D ctx.base.pc_next - pc_start; - tb->icount =3D num_insns; +static const TranslatorOps sh4_tr_ops =3D { + .init_disas_context =3D sh4_tr_init_disas_context, + .tb_start =3D sh4_tr_tb_start, + .insn_start =3D sh4_tr_insn_start, + .breakpoint_check =3D sh4_tr_breakpoint_check, + .translate_insn =3D sh4_tr_translate_insn, + .tb_stop =3D sh4_tr_tb_stop, + .disas_log =3D sh4_tr_disas_log, +}; + +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +{ + DisasContext ctx; =20 -#ifdef DEBUG_DISAS - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(pc_start)) { - qemu_log_lock(); - qemu_log("IN:\n"); /* , lookup_symbol(pc_start)); */ - log_target_disas(cs, pc_start, ctx.base.pc_next - pc_start); - qemu_log("\n"); - qemu_log_unlock(); - } -#endif + translator_loop(&sh4_tr_ops, &ctx.base, cs, tb); } =20 void restore_state_to_opc(CPUSH4State *env, TranslationBlock *tb, --=20 2.7.4