From nobody Fri Oct 24 09:33:45 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1518917702589480.2534605474598; Sat, 17 Feb 2018 17:35:02 -0800 (PST) Received: from localhost ([::1]:60456 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1enDsX-0004IK-Oj for importer@patchew.org; Sat, 17 Feb 2018 20:34:57 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34157) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1enDqT-0003A2-17 for qemu-devel@nongnu.org; Sat, 17 Feb 2018 20:32:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1enDqP-0006Lg-OO for qemu-devel@nongnu.org; Sat, 17 Feb 2018 20:32:49 -0500 Received: from out5-smtp.messagingengine.com ([66.111.4.29]:32975) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1enDqP-0006H5-Io for qemu-devel@nongnu.org; Sat, 17 Feb 2018 20:32:45 -0500 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id DC5A020D1D; Sat, 17 Feb 2018 20:32:43 -0500 (EST) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Sat, 17 Feb 2018 20:32:43 -0500 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 9950F24547; Sat, 17 Feb 2018 20:32:43 -0500 (EST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc; s=mesmtp; bh=owAbwAIk1Y06Ic w79x5Hi1rITvkqqsFMaJgkp5fKbHk=; b=LK6SGLhIEKljl281ISo/VrIfTmzKXo EWRdFMkaFMPdM5DDYj9B2MgppLLEo1myda+haKazqEPyA8aJKsTc6n37sT04knRC oYTcuhRGEZeg6LqEdBiGMBQOlz273RQ1FXoLQlb7o6jo1dM/RJr7XAiBEvDjEKjT b6PMSd4GOg5Tw= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc; s= fm2; bh=owAbwAIk1Y06Icw79x5Hi1rITvkqqsFMaJgkp5fKbHk=; b=A53PjZ6I 0lNBcG1t1DXcY8caBXFZxxXCGYkFRwbyn2frRpT0RfPb0j89AW/5SmXsr0+aE4yJ tidb69jHh4pW2cdCR6Nx3jPf9Ar5w0uqEevdquOWN9gbOUwYsJDztGwjfc/WQcEF GfJcQVI6HAhx+Oa9PPIw0E0p5sJ2iqiqsJh86M8VO3+2IzDUyr6ktdPE4It74+5f 7gOLj1FibTb01sPYeO/z1eXUb2kxxV9/bm1H+E8LGNDhFc04ytL97f35jdT3SSA4 05oqeL2duD6bTKuYf87t4OopMoCXa1ZZF5+9e93EfvOkE+rFJqFnsb9a3TofNUm3 hG8FZzHaHh7Euw== X-ME-Sender: From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sat, 17 Feb 2018 20:32:36 -0500 Message-Id: <1518917557-12063-2-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1518917557-12063-1-git-send-email-cota@braap.org> References: <1518917557-12063-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.29 Subject: [Qemu-devel] [PATCH 1/2] target/openrisc: convert to DisasContextBase X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Emilio G. Cota --- target/openrisc/translate.c | 87 ++++++++++++++++++++++-------------------= ---- 1 file changed, 43 insertions(+), 44 deletions(-) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 2747b24..0450144 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -36,7 +36,8 @@ #include "exec/log.h" =20 #define LOG_DIS(str, ...) \ - qemu_log_mask(CPU_LOG_TB_IN_ASM, "%08x: " str, dc->pc, ## __VA_ARGS__) + qemu_log_mask(CPU_LOG_TB_IN_ASM, "%08x: " str, dc->base.pc_next, \ + ## __VA_ARGS__) =20 /* is_jmp field values */ #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ @@ -44,13 +45,10 @@ #define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ =20 typedef struct DisasContext { - TranslationBlock *tb; - target_ulong pc; - uint32_t is_jmp; + DisasContextBase base; uint32_t mem_idx; uint32_t tb_flags; uint32_t delayed_branch; - bool singlestep_enabled; } DisasContext; =20 static TCGv cpu_sr; @@ -126,9 +124,9 @@ static void gen_exception(DisasContext *dc, unsigned in= t excp) =20 static void gen_illegal_exception(DisasContext *dc) { - tcg_gen_movi_tl(cpu_pc, dc->pc); + tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); gen_exception(dc, EXCP_ILLEGAL); - dc->is_jmp =3D DISAS_UPDATE; + dc->base.is_jmp =3D DISAS_UPDATE; } =20 /* not used yet, open it when we need or64. */ @@ -166,12 +164,12 @@ static void check_ov64s(DisasContext *dc) =20 static inline bool use_goto_tb(DisasContext *dc, target_ulong dest) { - if (unlikely(dc->singlestep_enabled)) { + if (unlikely(dc->base.singlestep_enabled)) { return false; } =20 #ifndef CONFIG_USER_ONLY - return (dc->tb->pc & TARGET_PAGE_MASK) =3D=3D (dest & TARGET_PAGE_MASK= ); + return (dc->base.tb->pc & TARGET_PAGE_MASK) =3D=3D (dest & TARGET_PAGE= _MASK); #else return true; #endif @@ -182,10 +180,10 @@ static void gen_goto_tb(DisasContext *dc, int n, targ= et_ulong dest) if (use_goto_tb(dc, dest)) { tcg_gen_movi_tl(cpu_pc, dest); tcg_gen_goto_tb(n); - tcg_gen_exit_tb((uintptr_t)dc->tb + n); + tcg_gen_exit_tb((uintptr_t)dc->base.tb + n); } else { tcg_gen_movi_tl(cpu_pc, dest); - if (dc->singlestep_enabled) { + if (dc->base.singlestep_enabled) { gen_exception(dc, EXCP_DEBUG); } tcg_gen_exit_tb(0); @@ -194,16 +192,16 @@ static void gen_goto_tb(DisasContext *dc, int n, targ= et_ulong dest) =20 static void gen_jump(DisasContext *dc, int32_t n26, uint32_t reg, uint32_t= op0) { - target_ulong tmp_pc =3D dc->pc + n26 * 4; + target_ulong tmp_pc =3D dc->base.pc_next + n26 * 4; =20 switch (op0) { case 0x00: /* l.j */ tcg_gen_movi_tl(jmp_pc, tmp_pc); break; case 0x01: /* l.jal */ - tcg_gen_movi_tl(cpu_R[9], dc->pc + 8); + tcg_gen_movi_tl(cpu_R[9], dc->base.pc_next + 8); /* Optimize jal being used to load the PC for PIC. */ - if (tmp_pc =3D=3D dc->pc + 8) { + if (tmp_pc =3D=3D dc->base.pc_next + 8) { return; } tcg_gen_movi_tl(jmp_pc, tmp_pc); @@ -211,7 +209,7 @@ static void gen_jump(DisasContext *dc, int32_t n26, uin= t32_t reg, uint32_t op0) case 0x03: /* l.bnf */ case 0x04: /* l.bf */ { - TCGv t_next =3D tcg_const_tl(dc->pc + 8); + TCGv t_next =3D tcg_const_tl(dc->base.pc_next + 8); TCGv t_true =3D tcg_const_tl(tmp_pc); TCGv t_zero =3D tcg_const_tl(0); =20 @@ -227,7 +225,7 @@ static void gen_jump(DisasContext *dc, int32_t n26, uin= t32_t reg, uint32_t op0) tcg_gen_mov_tl(jmp_pc, cpu_R[reg]); break; case 0x12: /* l.jalr */ - tcg_gen_movi_tl(cpu_R[9], (dc->pc + 8)); + tcg_gen_movi_tl(cpu_R[9], (dc->base.pc_next + 8)); tcg_gen_mov_tl(jmp_pc, cpu_R[reg]); break; default: @@ -795,7 +793,7 @@ static void dec_misc(DisasContext *dc, uint32_t insn) return; } gen_helper_rfe(cpu_env); - dc->is_jmp =3D DISAS_UPDATE; + dc->base.is_jmp =3D DISAS_UPDATE; #endif } break; @@ -1254,14 +1252,14 @@ static void dec_sys(DisasContext *dc, uint32_t insn) switch (op0) { case 0x000: /* l.sys */ LOG_DIS("l.sys %d\n", K16); - tcg_gen_movi_tl(cpu_pc, dc->pc); + tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); gen_exception(dc, EXCP_SYSCALL); - dc->is_jmp =3D DISAS_UPDATE; + dc->base.is_jmp =3D DISAS_UPDATE; break; =20 case 0x100: /* l.trap */ LOG_DIS("l.trap %d\n", K16); - tcg_gen_movi_tl(cpu_pc, dc->pc); + tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); gen_exception(dc, EXCP_TRAP); break; =20 @@ -1479,7 +1477,7 @@ static void disas_openrisc_insn(DisasContext *dc, Ope= nRISCCPU *cpu) { uint32_t op0; uint32_t insn; - insn =3D cpu_ldl_code(&cpu->env, dc->pc); + insn =3D cpu_ldl_code(&cpu->env, dc->base.pc_next); op0 =3D extract32(insn, 26, 6); =20 switch (op0) { @@ -1532,14 +1530,15 @@ void gen_intermediate_code(CPUState *cs, struct Tra= nslationBlock *tb) int max_insns; =20 pc_start =3D tb->pc; - dc->tb =3D tb; =20 - dc->is_jmp =3D DISAS_NEXT; - dc->pc =3D pc_start; + dc->base.tb =3D tb; + dc->base.singlestep_enabled =3D cs->singlestep_enabled; + dc->base.pc_next =3D pc_start; + dc->base.is_jmp =3D DISAS_NEXT; + dc->mem_idx =3D cpu_mmu_index(&cpu->env, false); - dc->tb_flags =3D tb->flags; + dc->tb_flags =3D dc->base.tb->flags; dc->delayed_branch =3D (dc->tb_flags & TB_FLAGS_DFLAG) !=3D 0; - dc->singlestep_enabled =3D cs->singlestep_enabled; =20 next_page_start =3D (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; num_insns =3D 0; @@ -1570,19 +1569,19 @@ void gen_intermediate_code(CPUState *cs, struct Tra= nslationBlock *tb) } =20 do { - tcg_gen_insn_start(dc->pc, (dc->delayed_branch ? 1 : 0) + tcg_gen_insn_start(dc->base.pc_next, (dc->delayed_branch ? 1 : 0) | (num_insns ? 2 : 0)); num_insns++; =20 - if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { - tcg_gen_movi_tl(cpu_pc, dc->pc); + if (unlikely(cpu_breakpoint_test(cs, dc->base.pc_next, BP_ANY))) { + tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); gen_exception(dc, EXCP_DEBUG); - dc->is_jmp =3D DISAS_UPDATE; + dc->base.is_jmp =3D DISAS_UPDATE; /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that the logic setting tb->size below does the right thing. */ - dc->pc +=3D 4; + dc->base.pc_next +=3D 4; break; } =20 @@ -1590,7 +1589,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) gen_io_start(); } disas_openrisc_insn(dc, cpu); - dc->pc =3D dc->pc + 4; + dc->base.pc_next +=3D 4; =20 /* delay slot */ if (dc->delayed_branch) { @@ -1598,15 +1597,15 @@ void gen_intermediate_code(CPUState *cs, struct Tra= nslationBlock *tb) if (!dc->delayed_branch) { tcg_gen_mov_tl(cpu_pc, jmp_pc); tcg_gen_discard_tl(jmp_pc); - dc->is_jmp =3D DISAS_UPDATE; + dc->base.is_jmp =3D DISAS_UPDATE; break; } } - } while (!dc->is_jmp + } while (!dc->base.is_jmp && !tcg_op_buf_full() - && !cs->singlestep_enabled + && !dc->base.singlestep_enabled && !singlestep - && (dc->pc < next_page_start) + && (dc->base.pc_next < next_page_start) && num_insns < max_insns); =20 if (tb_cflags(tb) & CF_LAST_IO) { @@ -1617,17 +1616,17 @@ void gen_intermediate_code(CPUState *cs, struct Tra= nslationBlock *tb) tcg_gen_movi_i32(cpu_dflag, dc->delayed_branch !=3D 0); } =20 - tcg_gen_movi_tl(cpu_ppc, dc->pc - 4); - if (dc->is_jmp =3D=3D DISAS_NEXT) { - dc->is_jmp =3D DISAS_UPDATE; - tcg_gen_movi_tl(cpu_pc, dc->pc); + tcg_gen_movi_tl(cpu_ppc, dc->base.pc_next - 4); + if (dc->base.is_jmp =3D=3D DISAS_NEXT) { + dc->base.is_jmp =3D DISAS_UPDATE; + tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); } - if (unlikely(cs->singlestep_enabled)) { + if (unlikely(dc->base.singlestep_enabled)) { gen_exception(dc, EXCP_DEBUG); } else { - switch (dc->is_jmp) { + switch (dc->base.is_jmp) { case DISAS_NEXT: - gen_goto_tb(dc, 0, dc->pc); + gen_goto_tb(dc, 0, dc->base.pc_next); break; default: case DISAS_JUMP: @@ -1645,7 +1644,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) =20 gen_tb_end(tb, num_insns); =20 - tb->size =3D dc->pc - pc_start; + tb->size =3D dc->base.pc_next - pc_start; tb->icount =3D num_insns; =20 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) --=20 2.7.4 From nobody Fri Oct 24 09:33:45 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1518917702914644.294978170607; Sat, 17 Feb 2018 17:35:02 -0800 (PST) Received: from localhost ([::1]:60454 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1enDsU-0004GS-V5 for importer@patchew.org; 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Cota" To: qemu-devel@nongnu.org Date: Sat, 17 Feb 2018 20:32:37 -0500 Message-Id: <1518917557-12063-3-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1518917557-12063-1-git-send-email-cota@braap.org> References: <1518917557-12063-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.29 Subject: [Qemu-devel] [PATCH 2/2] target/openrisc: convert to TranslatorOps X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Notes: - Changed the num_insns test in tb_start to check for dc->base.num_insns > 1, since when tb_start is first called in a TB, base.num_insns is already set to 1. - Removed DISAS_NEXT from the switch on tb_stop; use DISAS_TOO_MANY instead. - Added an assert_not_reached on tb_stop for DISAS_NEXT and the default case. - Merged the two separate log_target_disas calls into the disas_log op. Signed-off-by: Emilio G. Cota --- target/openrisc/translate.c | 168 ++++++++++++++++++++++------------------= ---- 1 file changed, 85 insertions(+), 83 deletions(-) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 0450144..4af4569 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -49,6 +49,7 @@ typedef struct DisasContext { uint32_t mem_idx; uint32_t tb_flags; uint32_t delayed_branch; + uint32_t next_page_start; } DisasContext; =20 static TCGv cpu_sr; @@ -1519,46 +1520,23 @@ static void disas_openrisc_insn(DisasContext *dc, O= penRISCCPU *cpu) } } =20 -void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) +static int openrisc_tr_init_disas_context(DisasContextBase *dcbase, + CPUState *cs, int max_insns) { + DisasContext *dc =3D container_of(dcbase, DisasContext, base); CPUOpenRISCState *env =3D cs->env_ptr; - OpenRISCCPU *cpu =3D openrisc_env_get_cpu(env); - struct DisasContext ctx, *dc =3D &ctx; - uint32_t pc_start; - uint32_t next_page_start; - int num_insns; - int max_insns; =20 - pc_start =3D tb->pc; - - dc->base.tb =3D tb; - dc->base.singlestep_enabled =3D cs->singlestep_enabled; - dc->base.pc_next =3D pc_start; - dc->base.is_jmp =3D DISAS_NEXT; - - dc->mem_idx =3D cpu_mmu_index(&cpu->env, false); + dc->mem_idx =3D cpu_mmu_index(env, false); dc->tb_flags =3D dc->base.tb->flags; dc->delayed_branch =3D (dc->tb_flags & TB_FLAGS_DFLAG) !=3D 0; + dc->next_page_start =3D (dc->base.pc_first & TARGET_PAGE_MASK) + + TARGET_PAGE_SIZE; + return max_insns; +} =20 - next_page_start =3D (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; - num_insns =3D 0; - max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; - - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } - - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(pc_start)) { - qemu_log_lock(); - qemu_log("----------------\n"); - qemu_log("IN: %s\n", lookup_symbol(pc_start)); - } - - gen_tb_start(tb); +static void openrisc_tr_tb_start(DisasContextBase *db, CPUState *cs) +{ + DisasContext *dc =3D container_of(db, DisasContext, base); =20 /* Allow the TCG optimizer to see that R0 =3D=3D 0, when it's true, which is the common case. */ @@ -1567,50 +1545,60 @@ void gen_intermediate_code(CPUState *cs, struct Tra= nslationBlock *tb) } else { cpu_R[0] =3D cpu_R0; } +} + +static void openrisc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); =20 - do { - tcg_gen_insn_start(dc->base.pc_next, (dc->delayed_branch ? 1 : 0) - | (num_insns ? 2 : 0)); - num_insns++; + tcg_gen_insn_start(dc->base.pc_next, (dc->delayed_branch ? 1 : 0) + | (dc->base.num_insns > 1 ? 2 : 0)); +} =20 - if (unlikely(cpu_breakpoint_test(cs, dc->base.pc_next, BP_ANY))) { - tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); - gen_exception(dc, EXCP_DEBUG); +static bool openrisc_tr_breakpoint_check(DisasContextBase *dcbase, CPUStat= e *cs, + const CPUBreakpoint *bp) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); + gen_exception(dc, EXCP_DEBUG); + dc->base.is_jmp =3D DISAS_UPDATE; + /* The address covered by the breakpoint must be included in + [tb->pc, tb->pc + tb->size) in order to for it to be + properly cleared -- thus we increment the PC here so that + the logic setting tb->size below does the right thing. */ + dc->base.pc_next +=3D 4; + return true; +} + +static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState = *cs) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); + + disas_openrisc_insn(dc, cpu); + dc->base.pc_next +=3D 4; + + /* delay slot */ + if (dc->delayed_branch) { + dc->delayed_branch--; + if (!dc->delayed_branch) { + tcg_gen_mov_tl(cpu_pc, jmp_pc); + tcg_gen_discard_tl(jmp_pc); dc->base.is_jmp =3D DISAS_UPDATE; - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - dc->base.pc_next +=3D 4; - break; + return; } + } =20 - if (num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAST_IO)) { - gen_io_start(); - } - disas_openrisc_insn(dc, cpu); - dc->base.pc_next +=3D 4; - - /* delay slot */ - if (dc->delayed_branch) { - dc->delayed_branch--; - if (!dc->delayed_branch) { - tcg_gen_mov_tl(cpu_pc, jmp_pc); - tcg_gen_discard_tl(jmp_pc); - dc->base.is_jmp =3D DISAS_UPDATE; - break; - } - } - } while (!dc->base.is_jmp - && !tcg_op_buf_full() - && !dc->base.singlestep_enabled - && !singlestep - && (dc->base.pc_next < next_page_start) - && num_insns < max_insns); - - if (tb_cflags(tb) & CF_LAST_IO) { - gen_io_end(); + if (dc->base.is_jmp =3D=3D DISAS_NEXT && + dc->base.pc_next >=3D dc->next_page_start) { + dc->base.is_jmp =3D DISAS_TOO_MANY; } +} + +static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); =20 if ((dc->tb_flags & TB_FLAGS_DFLAG ? 1 : 0) !=3D (dc->delayed_branch != =3D 0)) { tcg_gen_movi_i32(cpu_dflag, dc->delayed_branch !=3D 0); @@ -1625,10 +1613,9 @@ void gen_intermediate_code(CPUState *cs, struct Tran= slationBlock *tb) gen_exception(dc, EXCP_DEBUG); } else { switch (dc->base.is_jmp) { - case DISAS_NEXT: + case DISAS_TOO_MANY: gen_goto_tb(dc, 0, dc->base.pc_next); break; - default: case DISAS_JUMP: break; case DISAS_UPDATE: @@ -1639,20 +1626,35 @@ void gen_intermediate_code(CPUState *cs, struct Tra= nslationBlock *tb) case DISAS_TB_JUMP: /* nothing more to generate */ break; + default: + g_assert_not_reached(); } } +} + +static void openrisc_tr_disas_log(const DisasContextBase *dcbase, CPUState= *cs) +{ + DisasContext *s =3D container_of(dcbase, DisasContext, base); =20 - gen_tb_end(tb, num_insns); + qemu_log("IN: %s\n", lookup_symbol(s->base.pc_first)); + log_target_disas(cs, s->base.pc_first, s->base.tb->size); +} =20 - tb->size =3D dc->base.pc_next - pc_start; - tb->icount =3D num_insns; +static const TranslatorOps openrisc_tr_ops =3D { + .init_disas_context =3D openrisc_tr_init_disas_context, + .tb_start =3D openrisc_tr_tb_start, + .insn_start =3D openrisc_tr_insn_start, + .breakpoint_check =3D openrisc_tr_breakpoint_check, + .translate_insn =3D openrisc_tr_translate_insn, + .tb_stop =3D openrisc_tr_tb_stop, + .disas_log =3D openrisc_tr_disas_log, +}; =20 - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(pc_start)) { - log_target_disas(cs, pc_start, tb->size); - qemu_log("\n"); - qemu_log_unlock(); - } +void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) +{ + DisasContext ctx; + + translator_loop(&openrisc_tr_ops, &ctx.base, cs, tb); } =20 void openrisc_cpu_dump_state(CPUState *cs, FILE *f, --=20 2.7.4