From nobody Fri Dec 19 04:08:04 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1518896909076377.5709938034739; Sat, 17 Feb 2018 11:48:29 -0800 (PST) Received: from localhost ([::1]:54636 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1en8TE-0000zK-Bz for importer@patchew.org; Sat, 17 Feb 2018 14:48:28 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45078) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1en7WM-0003a8-0N for qemu-devel@nongnu.org; Sat, 17 Feb 2018 13:47:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1en7WG-0001zE-VG for qemu-devel@nongnu.org; Sat, 17 Feb 2018 13:47:38 -0500 Received: from mx3-rdu2.redhat.com ([66.187.233.73]:36094 helo=mx1.redhat.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1en7WA-0001WJ-UP; Sat, 17 Feb 2018 13:47:27 -0500 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.rdu2.redhat.com [10.11.54.4]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 617DCEAE83; Sat, 17 Feb 2018 18:47:26 +0000 (UTC) Received: from localhost.localdomain.com (ovpn-116-21.ams2.redhat.com [10.36.116.21]) by smtp.corp.redhat.com (Postfix) with ESMTP id C49152024CA2; Sat, 17 Feb 2018 18:47:23 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, peter.maydell@linaro.org, qemu-arm@nongnu.org, qemu-devel@nongnu.org, prem.mallappa@gmail.com, alex.williamson@redhat.com Date: Sat, 17 Feb 2018 19:46:49 +0100 Message-Id: <1518893216-9983-8-git-send-email-eric.auger@redhat.com> In-Reply-To: <1518893216-9983-1-git-send-email-eric.auger@redhat.com> References: <1518893216-9983-1-git-send-email-eric.auger@redhat.com> X-Scanned-By: MIMEDefang 2.78 on 10.11.54.4 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.1]); Sat, 17 Feb 2018 18:47:26 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.1]); Sat, 17 Feb 2018 18:47:26 +0000 (UTC) for IP:'10.11.54.4' DOMAIN:'int-mx04.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'eric.auger@redhat.com' RCPT:'' X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.187.233.73 Subject: [Qemu-devel] [PATCH v9 07/14] hw/arm/smmuv3: Implement MMIO write operations X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com, jean-philippe.brucker@arm.com, tn@semihalf.com, peterx@redhat.com, edgar.iglesias@gmail.com, linuc.decode@gmail.com, bharat.bhushan@nxp.com, christoffer.dall@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Now we have relevant helpers for queue and irq management, let's implement MMIO write operations. Signed-off-by: Eric Auger --- v7 -> v8: - precise in the commit message invalidation commands are not yet treated. - use new queue helpers - do not decode unhandled commands at this stage --- hw/arm/smmuv3-internal.h | 24 +++++++--- hw/arm/smmuv3.c | 111 +++++++++++++++++++++++++++++++++++++++++++= ++-- hw/arm/trace-events | 6 +++ 3 files changed, 132 insertions(+), 9 deletions(-) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index c0771ce..5af97ae 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -152,6 +152,25 @@ static inline uint64_t smmu_read64(uint64_t r, unsigne= d offset, return extract64(r, offset << 3, 32); } =20 +static inline void smmu_write64(uint64_t *r, unsigned offset, + unsigned size, uint64_t value) +{ + if (size =3D=3D 8 && !offset) { + *r =3D value; + } + + /* 32 bit access */ + + if (offset && offset !=3D 4) { + qemu_log_mask(LOG_GUEST_ERROR, + "SMMUv3 MMIO write: bad offset/size %u/%u\n", + offset, size); + return ; + } + + *r =3D deposit64(*r, offset << 3, 32, value); +} + /* Interrupts */ =20 #define smmuv3_eventq_irq_enabled(s) \ @@ -159,9 +178,6 @@ static inline uint64_t smmu_read64(uint64_t r, unsigned= offset, #define smmuv3_gerror_irq_enabled(s) \ (FIELD_EX32(s->irq_ctrl, IRQ_CTRL, GERROR_IRQEN)) =20 -void smmuv3_trigger_irq(SMMUv3State *s, SMMUIrq irq, uint32_t gerror_mask); -void smmuv3_write_gerrorn(SMMUv3State *s, uint32_t gerrorn); - /* Queue Handling */ =20 #define LOG2SIZE(q) extract64((q)->base, 0, 5) @@ -310,6 +326,4 @@ enum { /* Command completion notification */ addr; \ }) =20 -int smmuv3_cmdq_consume(SMMUv3State *s); - #endif diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 0b57215..fcfdbb0 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -37,7 +37,8 @@ * @irq: irq type * @gerror_mask: mask of gerrors to toggle (relevant if @irq is GERROR) */ -void smmuv3_trigger_irq(SMMUv3State *s, SMMUIrq irq, uint32_t gerror_mask) +static void smmuv3_trigger_irq(SMMUv3State *s, SMMUIrq irq, + uint32_t gerror_mask) { =20 bool pulse =3D false; @@ -75,7 +76,7 @@ void smmuv3_trigger_irq(SMMUv3State *s, SMMUIrq irq, uint= 32_t gerror_mask) } } =20 -void smmuv3_write_gerrorn(SMMUv3State *s, uint32_t new_gerrorn) +static void smmuv3_write_gerrorn(SMMUv3State *s, uint32_t new_gerrorn) { uint32_t pending =3D s->gerror ^ s->gerrorn; uint32_t toggled =3D s->gerrorn ^ new_gerrorn; @@ -199,7 +200,7 @@ static void smmuv3_init_regs(SMMUv3State *s) s->sid_split =3D 0; } =20 -int smmuv3_cmdq_consume(SMMUv3State *s) +static int smmuv3_cmdq_consume(SMMUv3State *s) { SMMUCmdError cmd_error =3D SMMU_CERROR_NONE; SMMUQueue *q =3D &s->cmdq; @@ -298,7 +299,109 @@ int smmuv3_cmdq_consume(SMMUv3State *s) static void smmu_write_mmio(void *opaque, hwaddr addr, uint64_t val, unsigned size) { - /* not yet implemented */ + SMMUState *sys =3D opaque; + SMMUv3State *s =3D ARM_SMMUV3(sys); + + /* CONSTRAINED UNPREDICTABLE choice to have page0/1 be exact aliases */ + addr &=3D ~0x10000; + + if (size !=3D 4 && size !=3D 8) { + qemu_log_mask(LOG_GUEST_ERROR, + "SMMUv3 MMIO write: bad size %u\n", size); + } + + trace_smmuv3_write_mmio(addr, val, size); + + switch (addr) { + case A_CR0: + s->cr[0] =3D val; + s->cr0ack =3D val; + /* in case the command queue has been enabled */ + smmuv3_cmdq_consume(s); + return; + case A_CR1: + s->cr[1] =3D val; + return; + case A_CR2: + s->cr[2] =3D val; + return; + case A_IRQ_CTRL: + s->irq_ctrl =3D val; + return; + case A_GERRORN: + smmuv3_write_gerrorn(s, val); + /* + * By acknowledging the CMDQ_ERR, SW may notify cmds can + * be processed again + */ + smmuv3_cmdq_consume(s); + return; + case A_GERROR_IRQ_CFG0: /* 64b */ + smmu_write64(&s->gerror_irq_cfg0, 0, size, val); + return; + case A_GERROR_IRQ_CFG0 + 4: + smmu_write64(&s->gerror_irq_cfg0, 4, size, val); + return; + case A_GERROR_IRQ_CFG1: + s->gerror_irq_cfg1 =3D val; + return; + case A_GERROR_IRQ_CFG2: + s->gerror_irq_cfg2 =3D val; + return; + case A_STRTAB_BASE: /* 64b */ + smmu_write64(&s->strtab_base, 0, size, val); + return; + case A_STRTAB_BASE + 4: + smmu_write64(&s->strtab_base, 4, size, val); + return; + case A_STRTAB_BASE_CFG: + s->strtab_base_cfg =3D val; + if (FIELD_EX32(val, STRTAB_BASE_CFG, FMT) =3D=3D 1) { + s->sid_split =3D FIELD_EX32(val, STRTAB_BASE_CFG, SPLIT); + s->features |=3D SMMU_FEATURE_2LVL_STE; + } + return; + case A_CMDQ_BASE: /* 64b */ + smmu_write64(&s->cmdq.base, 0, size, val); + return; + case A_CMDQ_BASE + 4: /* 64b */ + smmu_write64(&s->cmdq.base, 4, size, val); + return; + case A_CMDQ_PROD: + s->cmdq.prod =3D val; + smmuv3_cmdq_consume(s); + return; + case A_CMDQ_CONS: + s->cmdq.cons =3D val; + return; + case A_EVENTQ_BASE: /* 64b */ + smmu_write64(&s->eventq.base, 0, size, val); + return; + case A_EVENTQ_BASE + 4: + smmu_write64(&s->eventq.base, 4, size, val); + return; + case A_EVENTQ_PROD: + s->eventq.prod =3D val; + return; + case A_EVENTQ_CONS: + s->eventq.cons =3D val; + return; + case A_EVENTQ_IRQ_CFG0: /* 64b */ + s->eventq.prod =3D val; + smmu_write64(&s->eventq_irq_cfg0, 0, size, val); + return; + case A_EVENTQ_IRQ_CFG0 + 4: + smmu_write64(&s->eventq_irq_cfg0, 4, size, val); + return; + case A_EVENTQ_IRQ_CFG1: + s->eventq_irq_cfg1 =3D val; + return; + case A_EVENTQ_IRQ_CFG2: + s->eventq_irq_cfg2 =3D val; + return; + default: + error_report("%s unhandled access at 0x%"PRIx64, __func__, addr); + } } =20 static uint64_t smmu_read_mmio(void *opaque, hwaddr addr, unsigned size) diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 1c5105d..ed5dce0 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -22,3 +22,9 @@ smmuv3_unhandled_cmd(uint32_t type) "Unhandled command ty= pe=3D%d" smmuv3_cmdq_consume(uint32_t prod, uint32_t cons, uint8_t prod_wrap, uint8= _t cons_wrap) "prod=3D%d cons=3D%d prod.wrap=3D%d cons.wrap=3D%d" smmuv3_cmdq_opcode(const char *opcode) "<--- %s" smmuv3_cmdq_consume_out(uint32_t prod, uint32_t cons, uint8_t prod_wrap, u= int8_t cons_wrap) "prod:%d, cons:%d, prod_wrap:%d, cons_wrap:%d " +smmuv3_update(bool is_empty, uint32_t prod, uint32_t cons, uint8_t prod_wr= ap, uint8_t cons_wrap) "q empty:%d prod:%d cons:%d p.wrap:%d p.cons:%d" +smmuv3_update_check_cmd(int error) "cmdq not enabled or error :0x%x" +smmuv3_write_mmio(hwaddr addr, uint64_t val, unsigned size) "addr: 0x%"PRI= x64" val:0x%"PRIx64" size: 0x%x" +smmuv3_write_mmio_idr(hwaddr addr, uint64_t val) "write to RO/Unimpl reg 0= x%lx val64:0x%lx" +smmuv3_write_mmio_evtq_cons_bef_clear(uint32_t prod, uint32_t cons, uint8_= t prod_wrap, uint8_t cons_wrap) "Before clearing interrupt prod:0x%x cons:0= x%x prod.w:%d cons.w:%d" +smmuv3_write_mmio_evtq_cons_after_clear(uint32_t prod, uint32_t cons, uint= 8_t prod_wrap, uint8_t cons_wrap) "after clearing interrupt prod:0x%x cons:= 0x%x prod.w:%d cons.w:%d" --=20 2.5.5