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Cota" To: qemu-devel@nongnu.org Date: Thu, 15 Feb 2018 21:02:51 -0500 Message-Id: <1518746572-14747-4-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1518746572-14747-1-git-send-email-cota@braap.org> References: <1518746572-14747-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.29 Subject: [Qemu-devel] [PATCH 3/4] target/mips: use *ctx for DisasContext X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yongbok Kim , Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" No changes to the logic here; this is just to make the diff that follows easier to read. While at it, remove the unnecessary 'struct' in 'struct TranslationBlock'. Note that checkpatch complains with a false positive: ERROR: space prohibited after that '&' (ctx:WxW) #75: FILE: target/mips/translate.c:20220: + ctx->kscrexist =3D (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff; ^ Signed-off-by: Emilio G. Cota --- target/mips/translate.c | 166 ++++++++++++++++++++++++--------------------= ---- 1 file changed, 84 insertions(+), 82 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index aefd729..08bd140 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -20194,55 +20194,57 @@ static void decode_opc(CPUMIPSState *env, DisasCo= ntext *ctx) } } =20 -void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { CPUMIPSState *env =3D cs->env_ptr; - DisasContext ctx; + DisasContext ctx1; + DisasContext *ctx =3D &ctx1; target_ulong next_page_start; int max_insns; int insn_bytes; int is_slot; =20 - ctx.base.tb =3D tb; - ctx.base.pc_first =3D tb->pc; - ctx.base.pc_next =3D tb->pc; - ctx.base.is_jmp =3D DISAS_NEXT; - ctx.base.singlestep_enabled =3D cs->singlestep_enabled; - ctx.base.num_insns =3D 0; - - next_page_start =3D (ctx.base.pc_first & TARGET_PAGE_MASK) + TARGET_PA= GE_SIZE; - ctx.saved_pc =3D -1; - ctx.insn_flags =3D env->insn_flags; - ctx.CP0_Config1 =3D env->CP0_Config1; - ctx.btarget =3D 0; - ctx.kscrexist =3D (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff; - ctx.rxi =3D (env->CP0_Config3 >> CP0C3_RXI) & 1; - ctx.ie =3D (env->CP0_Config4 >> CP0C4_IE) & 3; - ctx.bi =3D (env->CP0_Config3 >> CP0C3_BI) & 1; - ctx.bp =3D (env->CP0_Config3 >> CP0C3_BP) & 1; - ctx.PAMask =3D env->PAMask; - ctx.mvh =3D (env->CP0_Config5 >> CP0C5_MVH) & 1; - ctx.eva =3D (env->CP0_Config5 >> CP0C5_EVA) & 1; - ctx.sc =3D (env->CP0_Config3 >> CP0C3_SC) & 1; - ctx.CP0_LLAddr_shift =3D env->CP0_LLAddr_shift; - ctx.cmgcr =3D (env->CP0_Config3 >> CP0C3_CMGCR) & 1; + ctx->base.tb =3D tb; + ctx->base.pc_first =3D tb->pc; + ctx->base.pc_next =3D tb->pc; + ctx->base.is_jmp =3D DISAS_NEXT; + ctx->base.singlestep_enabled =3D cs->singlestep_enabled; + ctx->base.num_insns =3D 0; + + next_page_start =3D (ctx->base.pc_first & TARGET_PAGE_MASK) + + TARGET_PAGE_SIZE; + ctx->saved_pc =3D -1; + ctx->insn_flags =3D env->insn_flags; + ctx->CP0_Config1 =3D env->CP0_Config1; + ctx->btarget =3D 0; + ctx->kscrexist =3D (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff; + ctx->rxi =3D (env->CP0_Config3 >> CP0C3_RXI) & 1; + ctx->ie =3D (env->CP0_Config4 >> CP0C4_IE) & 3; + ctx->bi =3D (env->CP0_Config3 >> CP0C3_BI) & 1; + ctx->bp =3D (env->CP0_Config3 >> CP0C3_BP) & 1; + ctx->PAMask =3D env->PAMask; + ctx->mvh =3D (env->CP0_Config5 >> CP0C5_MVH) & 1; + ctx->eva =3D (env->CP0_Config5 >> CP0C5_EVA) & 1; + ctx->sc =3D (env->CP0_Config3 >> CP0C3_SC) & 1; + ctx->CP0_LLAddr_shift =3D env->CP0_LLAddr_shift; + ctx->cmgcr =3D (env->CP0_Config3 >> CP0C3_CMGCR) & 1; /* Restore delay slot state from the tb context. */ - ctx.hflags =3D (uint32_t)ctx.base.tb->flags; /* FIXME: maybe use 64 bi= ts? */ - ctx.ulri =3D (env->CP0_Config3 >> CP0C3_ULRI) & 1; - ctx.ps =3D ((env->active_fpu.fcr0 >> FCR0_PS) & 1) || + ctx->hflags =3D (uint32_t)ctx->base.tb->flags; /* FIXME: maybe use 64 = bits? */ + ctx->ulri =3D (env->CP0_Config3 >> CP0C3_ULRI) & 1; + ctx->ps =3D ((env->active_fpu.fcr0 >> FCR0_PS) & 1) || (env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)); - ctx.vp =3D (env->CP0_Config5 >> CP0C5_VP) & 1; - ctx.mrp =3D (env->CP0_Config5 >> CP0C5_MRP) & 1; - ctx.nan2008 =3D (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1; - ctx.abs2008 =3D (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1; - restore_cpu_state(env, &ctx); + ctx->vp =3D (env->CP0_Config5 >> CP0C5_VP) & 1; + ctx->mrp =3D (env->CP0_Config5 >> CP0C5_MRP) & 1; + ctx->nan2008 =3D (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1; + ctx->abs2008 =3D (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1; + restore_cpu_state(env, ctx); #ifdef CONFIG_USER_ONLY - ctx.mem_idx =3D MIPS_HFLAG_UM; + ctx->mem_idx =3D MIPS_HFLAG_UM; #else - ctx.mem_idx =3D hflags_mmu_index(ctx.hflags); + ctx->mem_idx =3D hflags_mmu_index(ctx->hflags); #endif - ctx.default_tcg_memop_mask =3D (ctx.insn_flags & ISA_MIPS32R6) ? - MO_UNALN : MO_ALIGN; + ctx->default_tcg_memop_mask =3D (ctx->insn_flags & ISA_MIPS32R6) ? + MO_UNALN : MO_ALIGN; max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; @@ -20251,74 +20253,74 @@ void gen_intermediate_code(CPUState *cs, struct T= ranslationBlock *tb) max_insns =3D TCG_MAX_INSNS; } =20 - LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx.mem_idx, ctx.hflags); + LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx->mem_idx, ctx->hflag= s); gen_tb_start(tb); - while (ctx.base.is_jmp =3D=3D DISAS_NEXT) { - tcg_gen_insn_start(ctx.base.pc_next, ctx.hflags & MIPS_HFLAG_BMASK, - ctx.btarget); - ctx.base.num_insns++; - - if (unlikely(cpu_breakpoint_test(cs, ctx.base.pc_next, BP_ANY))) { - save_cpu_state(&ctx, 1); - ctx.base.is_jmp =3D DISAS_NORETURN; + while (ctx->base.is_jmp =3D=3D DISAS_NEXT) { + tcg_gen_insn_start(ctx->base.pc_next, ctx->hflags & MIPS_HFLAG_BMA= SK, + ctx->btarget); + ctx->base.num_insns++; + + if (unlikely(cpu_breakpoint_test(cs, ctx->base.pc_next, BP_ANY))) { + save_cpu_state(ctx, 1); + ctx->base.is_jmp =3D DISAS_NORETURN; gen_helper_raise_exception_debug(cpu_env); /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that the logic setting tb->size below does the right thing. */ - ctx.base.pc_next +=3D 4; + ctx->base.pc_next +=3D 4; goto done_generating; } =20 - if (ctx.base.num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAS= T_IO)) { + if (ctx->base.num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LA= ST_IO)) { gen_io_start(); } =20 - is_slot =3D ctx.hflags & MIPS_HFLAG_BMASK; - if (!(ctx.hflags & MIPS_HFLAG_M16)) { - ctx.opcode =3D cpu_ldl_code(env, ctx.base.pc_next); + is_slot =3D ctx->hflags & MIPS_HFLAG_BMASK; + if (!(ctx->hflags & MIPS_HFLAG_M16)) { + ctx->opcode =3D cpu_ldl_code(env, ctx->base.pc_next); insn_bytes =3D 4; - decode_opc(env, &ctx); - } else if (ctx.insn_flags & ASE_MICROMIPS) { - ctx.opcode =3D cpu_lduw_code(env, ctx.base.pc_next); - insn_bytes =3D decode_micromips_opc(env, &ctx); - } else if (ctx.insn_flags & ASE_MIPS16) { - ctx.opcode =3D cpu_lduw_code(env, ctx.base.pc_next); - insn_bytes =3D decode_mips16_opc(env, &ctx); + decode_opc(env, ctx); + } else if (ctx->insn_flags & ASE_MICROMIPS) { + ctx->opcode =3D cpu_lduw_code(env, ctx->base.pc_next); + insn_bytes =3D decode_micromips_opc(env, ctx); + } else if (ctx->insn_flags & ASE_MIPS16) { + ctx->opcode =3D cpu_lduw_code(env, ctx->base.pc_next); + insn_bytes =3D decode_mips16_opc(env, ctx); } else { - generate_exception_end(&ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } =20 - if (ctx.hflags & MIPS_HFLAG_BMASK) { - if (!(ctx.hflags & (MIPS_HFLAG_BDS16 | MIPS_HFLAG_BDS32 | + if (ctx->hflags & MIPS_HFLAG_BMASK) { + if (!(ctx->hflags & (MIPS_HFLAG_BDS16 | MIPS_HFLAG_BDS32 | MIPS_HFLAG_FBNSLOT))) { /* force to generate branch as there is neither delay nor forbidden slot */ is_slot =3D 1; } - if ((ctx.hflags & MIPS_HFLAG_M16) && - (ctx.hflags & MIPS_HFLAG_FBNSLOT)) { + if ((ctx->hflags & MIPS_HFLAG_M16) && + (ctx->hflags & MIPS_HFLAG_FBNSLOT)) { /* Force to generate branch as microMIPS R6 doesn't restri= ct branches in the forbidden slot. */ is_slot =3D 1; } } if (is_slot) { - gen_branch(&ctx, insn_bytes); + gen_branch(ctx, insn_bytes); } - ctx.base.pc_next +=3D insn_bytes; + ctx->base.pc_next +=3D insn_bytes; =20 /* Execute a branch and its delay slot as a single instruction. This is what GDB expects and is consistent with what the hardware does (e.g. if a delay slot instruction faults, the reported PC is the PC of the branch). */ - if (ctx.base.singlestep_enabled && - (ctx.hflags & MIPS_HFLAG_BMASK) =3D=3D 0) { + if (ctx->base.singlestep_enabled && + (ctx->hflags & MIPS_HFLAG_BMASK) =3D=3D 0) { break; } =20 - if (ctx.base.pc_next >=3D next_page_start) { + if (ctx->base.pc_next >=3D next_page_start) { break; } =20 @@ -20326,7 +20328,7 @@ void gen_intermediate_code(CPUState *cs, struct Tra= nslationBlock *tb) break; } =20 - if (ctx.base.num_insns >=3D max_insns) { + if (ctx->base.num_insns >=3D max_insns) { break; } =20 @@ -20336,17 +20338,17 @@ void gen_intermediate_code(CPUState *cs, struct T= ranslationBlock *tb) if (tb_cflags(tb) & CF_LAST_IO) { gen_io_end(); } - if (ctx.base.singlestep_enabled && ctx.base.is_jmp !=3D DISAS_NORETURN= ) { - save_cpu_state(&ctx, ctx.base.is_jmp !=3D DISAS_EXCP); + if (ctx->base.singlestep_enabled && ctx->base.is_jmp !=3D DISAS_NORETU= RN) { + save_cpu_state(ctx, ctx->base.is_jmp !=3D DISAS_EXCP); gen_helper_raise_exception_debug(cpu_env); } else { - switch (ctx.base.is_jmp) { + switch (ctx->base.is_jmp) { case DISAS_STOP: - gen_goto_tb(&ctx, 0, ctx.base.pc_next); + gen_goto_tb(ctx, 0, ctx->base.pc_next); break; case DISAS_NEXT: - save_cpu_state(&ctx, 0); - gen_goto_tb(&ctx, 0, ctx.base.pc_next); + save_cpu_state(ctx, 0); + gen_goto_tb(ctx, 0, ctx->base.pc_next); break; case DISAS_EXCP: tcg_gen_exit_tb(0); @@ -20357,19 +20359,19 @@ void gen_intermediate_code(CPUState *cs, struct T= ranslationBlock *tb) } } done_generating: - gen_tb_end(tb, ctx.base.num_insns); + gen_tb_end(tb, ctx->base.num_insns); =20 - tb->size =3D ctx.base.pc_next - ctx.base.pc_first; - tb->icount =3D ctx.base.num_insns; + tb->size =3D ctx->base.pc_next - ctx->base.pc_first; + tb->icount =3D ctx->base.num_insns; =20 #ifdef DEBUG_DISAS LOG_DISAS("\n"); if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(ctx.base.pc_first)) { + && qemu_log_in_addr_range(ctx->base.pc_first)) { qemu_log_lock(); - qemu_log("IN: %s\n", lookup_symbol(ctx.base.pc_first)); - log_target_disas(cs, ctx.base.pc_first, - ctx.base.pc_next - ctx.base.pc_first); + qemu_log("IN: %s\n", lookup_symbol(ctx->base.pc_first)); + log_target_disas(cs, ctx->base.pc_first, + ctx->base.pc_next - ctx->base.pc_first); qemu_log("\n"); qemu_log_unlock(); } --=20 2.7.4