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Cota" To: qemu-devel@nongnu.org Date: Thu, 15 Feb 2018 21:02:49 -0500 Message-Id: <1518746572-14747-2-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1518746572-14747-1-git-send-email-cota@braap.org> References: <1518746572-14747-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.29 Subject: [Qemu-devel] [PATCH 1/4] target/mips: convert to DisasJumpType X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yongbok Kim , Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Emilio G. Cota --- target/mips/translate.c | 186 +++++++++++++++++++++++---------------------= ---- 1 file changed, 91 insertions(+), 95 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index d05ee67..a133205 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -36,6 +36,7 @@ =20 #include "target/mips/trace.h" #include "trace-tcg.h" +#include "exec/translator.h" #include "exec/log.h" =20 #define MIPS_DEBUG_DISAS 0 @@ -1439,7 +1440,7 @@ typedef struct DisasContext { int mem_idx; TCGMemOp default_tcg_memop_mask; uint32_t hflags, saved_hflags; - int bstate; + DisasJumpType is_jmp; target_ulong btarget; bool ulri; int kscrexist; @@ -1460,13 +1461,8 @@ typedef struct DisasContext { bool abs2008; } DisasContext; =20 -enum { - BS_NONE =3D 0, /* We go out of the TB without reaching a branch or= an - * exception condition */ - BS_STOP =3D 1, /* We want to stop translation for any reason */ - BS_BRANCH =3D 2, /* We reached a branch condition */ - BS_EXCP =3D 3, /* We reached an exception condition */ -}; +#define DISAS_STOP DISAS_TARGET_0 +#define DISAS_EXCP DISAS_TARGET_1 =20 static const char * const regnames[] =3D { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3", @@ -1639,7 +1635,7 @@ static inline void generate_exception_err(DisasContex= t *ctx, int excp, int err) gen_helper_raise_exception_err(cpu_env, texcp, terr); tcg_temp_free_i32(terr); tcg_temp_free_i32(texcp); - ctx->bstate =3D BS_EXCP; + ctx->is_jmp =3D DISAS_EXCP; } =20 static inline void generate_exception(DisasContext *ctx, int excp) @@ -5334,10 +5330,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) gen_io_end(); } /* Break the TB to be able to take timer interrupts immediately - after reading count. BS_STOP isn't sufficient, we need to e= nsure - we break completely out of translated code. */ + after reading count. DISAS_STOP isn't sufficient, we need to + ensure we break completely out of translated code. */ gen_save_pc(ctx->pc + 4); - ctx->bstate =3D BS_EXCP; + ctx->is_jmp =3D DISAS_EXCP; rn =3D "Count"; break; /* 6,7 are implementation dependent */ @@ -5905,7 +5901,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_pagegrain(cpu_env, arg); rn =3D "PageGrain"; - ctx->bstate =3D BS_STOP; + ctx->is_jmp =3D DISAS_STOP; break; case 2: CP0_CHECK(ctx->sc); @@ -5966,7 +5962,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case 0: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_hwrena(cpu_env, arg); - ctx->bstate =3D BS_STOP; + ctx->is_jmp =3D DISAS_STOP; rn =3D "HWREna"; break; default: @@ -6028,30 +6024,30 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) case 0: save_cpu_state(ctx, 1); gen_helper_mtc0_status(cpu_env, arg); - /* BS_STOP isn't good enough here, hflags may have changed. */ + /* DISAS_STOP isn't good enough here, hflags may have changed.= */ gen_save_pc(ctx->pc + 4); - ctx->bstate =3D BS_EXCP; + ctx->is_jmp =3D DISAS_EXCP; rn =3D "Status"; break; case 1: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_intctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode= */ - ctx->bstate =3D BS_STOP; + ctx->is_jmp =3D DISAS_STOP; rn =3D "IntCtl"; break; case 2: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode= */ - ctx->bstate =3D BS_STOP; + ctx->is_jmp =3D DISAS_STOP; rn =3D "SRSCtl"; break; case 3: check_insn(ctx, ISA_MIPS32R2); gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); /* Stop translation as we may have switched the execution mode= */ - ctx->bstate =3D BS_STOP; + ctx->is_jmp =3D DISAS_STOP; rn =3D "SRSMap"; break; default: @@ -6063,11 +6059,11 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) case 0: save_cpu_state(ctx, 1); gen_helper_mtc0_cause(cpu_env, arg); - /* Stop translation as we may have triggered an interrupt. BS_= STOP - * isn't sufficient, we need to ensure we break out of transla= ted - * code to check for pending interrupts. */ + /* Stop translation as we may have triggered an interrupt. + * DISAS_STOP isn't sufficient, we need to ensure we break out= of + * translated code to check for pending interrupts. */ gen_save_pc(ctx->pc + 4); - ctx->bstate =3D BS_EXCP; + ctx->is_jmp =3D DISAS_EXCP; rn =3D "Cause"; break; default: @@ -6105,7 +6101,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) gen_helper_mtc0_config0(cpu_env, arg); rn =3D "Config"; /* Stop translation as we may have switched the execution mode= */ - ctx->bstate =3D BS_STOP; + ctx->is_jmp =3D DISAS_STOP; break; case 1: /* ignored, read only */ @@ -6115,24 +6111,24 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) gen_helper_mtc0_config2(cpu_env, arg); rn =3D "Config2"; /* Stop translation as we may have switched the execution mode= */ - ctx->bstate =3D BS_STOP; + ctx->is_jmp =3D DISAS_STOP; break; case 3: gen_helper_mtc0_config3(cpu_env, arg); rn =3D "Config3"; /* Stop translation as we may have switched the execution mode= */ - ctx->bstate =3D BS_STOP; + ctx->is_jmp =3D DISAS_STOP; break; case 4: gen_helper_mtc0_config4(cpu_env, arg); rn =3D "Config4"; - ctx->bstate =3D BS_STOP; + ctx->is_jmp =3D DISAS_STOP; break; case 5: gen_helper_mtc0_config5(cpu_env, arg); rn =3D "Config5"; /* Stop translation as we may have switched the execution mode= */ - ctx->bstate =3D BS_STOP; + ctx->is_jmp =3D DISAS_STOP; break; /* 6,7 are implementation dependent */ case 6: @@ -6221,35 +6217,35 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) switch (sel) { case 0: gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */ - /* BS_STOP isn't good enough here, hflags may have changed. */ + /* DISAS_STOP isn't good enough here, hflags may have changed.= */ gen_save_pc(ctx->pc + 4); - ctx->bstate =3D BS_EXCP; + ctx->is_jmp =3D DISAS_EXCP; rn =3D "Debug"; break; case 1: // gen_helper_mtc0_tracecontrol(cpu_env, arg); /* PDtrace suppo= rt */ rn =3D "TraceControl"; /* Stop translation as we may have switched the execution mode= */ - ctx->bstate =3D BS_STOP; + ctx->is_jmp =3D DISAS_STOP; goto cp0_unimplemented; case 2: // gen_helper_mtc0_tracecontrol2(cpu_env, arg); /* PDtrace supp= ort */ rn =3D "TraceControl2"; /* Stop translation as we may have switched the execution mode= */ - ctx->bstate =3D BS_STOP; + ctx->is_jmp =3D DISAS_STOP; goto cp0_unimplemented; case 3: /* Stop translation as we may have switched the execution mode= */ - ctx->bstate =3D BS_STOP; + ctx->is_jmp =3D DISAS_STOP; // gen_helper_mtc0_usertracedata(cpu_env, arg); /* PDtrace supp= ort */ rn =3D "UserTraceData"; /* Stop translation as we may have switched the execution mode= */ - ctx->bstate =3D BS_STOP; + ctx->is_jmp =3D DISAS_STOP; goto cp0_unimplemented; case 4: // gen_helper_mtc0_tracebpc(cpu_env, arg); /* PDtrace support */ /* Stop translation as we may have switched the execution mode= */ - ctx->bstate =3D BS_STOP; + ctx->is_jmp =3D DISAS_STOP; rn =3D "TraceBPC"; goto cp0_unimplemented; default: @@ -6309,7 +6305,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) switch (sel) { case 0: gen_helper_mtc0_errctl(cpu_env, arg); - ctx->bstate =3D BS_STOP; + ctx->is_jmp =3D DISAS_STOP; rn =3D "ErrCtl"; break; default: @@ -6402,10 +6398,10 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) /* For simplicity assume that all writes can cause interrupts. */ if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_end(); - /* BS_STOP isn't sufficient, we need to ensure we break out of + /* DISAS_STOP isn't sufficient, we need to ensure we break out of * translated code to check for pending interrupts. */ gen_save_pc(ctx->pc + 4); - ctx->bstate =3D BS_EXCP; + ctx->is_jmp =3D DISAS_EXCP; } return; =20 @@ -6686,10 +6682,10 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) gen_io_end(); } /* Break the TB to be able to take timer interrupts immediately - after reading count. BS_STOP isn't sufficient, we need to e= nsure - we break completely out of translated code. */ + after reading count. DISAS_STOP isn't sufficient, we need to + ensure we break completely out of translated code. */ gen_save_pc(ctx->pc + 4); - ctx->bstate =3D BS_EXCP; + ctx->is_jmp =3D DISAS_EXCP; rn =3D "Count"; break; /* 6,7 are implementation dependent */ @@ -7301,7 +7297,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) case 0: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_hwrena(cpu_env, arg); - ctx->bstate =3D BS_STOP; + ctx->is_jmp =3D DISAS_STOP; rn =3D "HWREna"; break; default: @@ -7337,7 +7333,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } /* Stop translation as we may have switched the execution mode */ - ctx->bstate =3D BS_STOP; + ctx->is_jmp =3D DISAS_STOP; break; case 10: switch (sel) { @@ -7360,37 +7356,37 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) goto cp0_unimplemented; } /* Stop translation as we may have switched the execution mode */ - ctx->bstate =3D BS_STOP; + ctx->is_jmp =3D DISAS_STOP; break; case 12: switch (sel) { case 0: save_cpu_state(ctx, 1); gen_helper_mtc0_status(cpu_env, arg); - /* BS_STOP isn't good enough here, hflags may have changed. */ + /* DISAS_STOP isn't good enough here, hflags may have changed.= */ gen_save_pc(ctx->pc + 4); - ctx->bstate =3D BS_EXCP; + ctx->is_jmp =3D DISAS_EXCP; rn =3D "Status"; break; case 1: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_intctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode= */ - ctx->bstate =3D BS_STOP; + ctx->is_jmp =3D DISAS_STOP; rn =3D "IntCtl"; break; case 2: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode= */ - ctx->bstate =3D BS_STOP; + ctx->is_jmp =3D DISAS_STOP; rn =3D "SRSCtl"; break; case 3: check_insn(ctx, ISA_MIPS32R2); gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); /* Stop translation as we may have switched the execution mode= */ - ctx->bstate =3D BS_STOP; + ctx->is_jmp =3D DISAS_STOP; rn =3D "SRSMap"; break; default: @@ -7402,11 +7398,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) case 0: save_cpu_state(ctx, 1); gen_helper_mtc0_cause(cpu_env, arg); - /* Stop translation as we may have triggered an intetrupt. BS_= STOP - * isn't sufficient, we need to ensure we break out of transla= ted - * code to check for pending interrupts. */ + /* Stop translation as we may have triggered an intetrupt. + * DISAS_STOP isn't sufficient, we need to ensure we break out= of + * translated code to check for pending interrupts. */ gen_save_pc(ctx->pc + 4); - ctx->bstate =3D BS_EXCP; + ctx->is_jmp =3D DISAS_EXCP; rn =3D "Cause"; break; default: @@ -7444,7 +7440,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) gen_helper_mtc0_config0(cpu_env, arg); rn =3D "Config"; /* Stop translation as we may have switched the execution mode= */ - ctx->bstate =3D BS_STOP; + ctx->is_jmp =3D DISAS_STOP; break; case 1: /* ignored, read only */ @@ -7454,13 +7450,13 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) gen_helper_mtc0_config2(cpu_env, arg); rn =3D "Config2"; /* Stop translation as we may have switched the execution mode= */ - ctx->bstate =3D BS_STOP; + ctx->is_jmp =3D DISAS_STOP; break; case 3: gen_helper_mtc0_config3(cpu_env, arg); rn =3D "Config3"; /* Stop translation as we may have switched the execution mode= */ - ctx->bstate =3D BS_STOP; + ctx->is_jmp =3D DISAS_STOP; break; case 4: /* currently ignored */ @@ -7470,7 +7466,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) gen_helper_mtc0_config5(cpu_env, arg); rn =3D "Config5"; /* Stop translation as we may have switched the execution mode= */ - ctx->bstate =3D BS_STOP; + ctx->is_jmp =3D DISAS_STOP; break; /* 6,7 are implementation dependent */ default: @@ -7549,33 +7545,33 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) switch (sel) { case 0: gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */ - /* BS_STOP isn't good enough here, hflags may have changed. */ + /* DISAS_STOP isn't good enough here, hflags may have changed.= */ gen_save_pc(ctx->pc + 4); - ctx->bstate =3D BS_EXCP; + ctx->is_jmp =3D DISAS_EXCP; rn =3D "Debug"; break; case 1: // gen_helper_mtc0_tracecontrol(cpu_env, arg); /* PDtrace suppo= rt */ /* Stop translation as we may have switched the execution mode= */ - ctx->bstate =3D BS_STOP; + ctx->is_jmp =3D DISAS_STOP; rn =3D "TraceControl"; goto cp0_unimplemented; case 2: // gen_helper_mtc0_tracecontrol2(cpu_env, arg); /* PDtrace supp= ort */ /* Stop translation as we may have switched the execution mode= */ - ctx->bstate =3D BS_STOP; + ctx->is_jmp =3D DISAS_STOP; rn =3D "TraceControl2"; goto cp0_unimplemented; case 3: // gen_helper_mtc0_usertracedata(cpu_env, arg); /* PDtrace supp= ort */ /* Stop translation as we may have switched the execution mode= */ - ctx->bstate =3D BS_STOP; + ctx->is_jmp =3D DISAS_STOP; rn =3D "UserTraceData"; goto cp0_unimplemented; case 4: // gen_helper_mtc0_tracebpc(cpu_env, arg); /* PDtrace support */ /* Stop translation as we may have switched the execution mode= */ - ctx->bstate =3D BS_STOP; + ctx->is_jmp =3D DISAS_STOP; rn =3D "TraceBPC"; goto cp0_unimplemented; default: @@ -7635,7 +7631,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) switch (sel) { case 0: gen_helper_mtc0_errctl(cpu_env, arg); - ctx->bstate =3D BS_STOP; + ctx->is_jmp =3D DISAS_STOP; rn =3D "ErrCtl"; break; default: @@ -7728,10 +7724,10 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) /* For simplicity assume that all writes can cause interrupts. */ if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_end(); - /* BS_STOP isn't sufficient, we need to ensure we break out of + /* DISAS_STOP isn't sufficient, we need to ensure we break out of * translated code to check for pending interrupts. */ gen_save_pc(ctx->pc + 4); - ctx->bstate =3D BS_EXCP; + ctx->is_jmp =3D DISAS_EXCP; } return; =20 @@ -8142,7 +8138,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext = *ctx, int rd, int rt, tcg_temp_free_i32(fs_tmp); } /* Stop translation as we may have changed hflags */ - ctx->bstate =3D BS_STOP; + ctx->is_jmp =3D DISAS_STOP; break; /* COP2: Not implemented. */ case 4: @@ -8301,7 +8297,7 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext = *ctx, uint32_t opc, int rt, check_insn(ctx, ISA_MIPS2); gen_helper_eret(cpu_env); } - ctx->bstate =3D BS_EXCP; + ctx->is_jmp =3D DISAS_EXCP; } break; case OPC_DERET: @@ -8316,7 +8312,7 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext = *ctx, uint32_t opc, int rt, generate_exception_end(ctx, EXCP_RI); } else { gen_helper_deret(cpu_env); - ctx->bstate =3D BS_EXCP; + ctx->is_jmp =3D DISAS_EXCP; } break; case OPC_WAIT: @@ -8331,7 +8327,7 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext = *ctx, uint32_t opc, int rt, save_cpu_state(ctx, 1); ctx->pc -=3D 4; gen_helper_wait(cpu_env); - ctx->bstate =3D BS_EXCP; + ctx->is_jmp =3D DISAS_EXCP; break; default: die: @@ -8756,7 +8752,7 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc,= int rt, int fs) tcg_temp_free_i32(fs_tmp); } /* Stop translation as we may have changed hflags */ - ctx->bstate =3D BS_STOP; + ctx->is_jmp =3D DISAS_STOP; break; #if defined(TARGET_MIPS64) case OPC_DMFC1: @@ -10764,10 +10760,10 @@ static void gen_rdhwr(DisasContext *ctx, int rt, = int rd, int sel) } gen_store_gpr(t0, rt); /* Break the TB to be able to take timer interrupts immediately - after reading count. BS_STOP isn't sufficient, we need to ensure + after reading count. DISAS_STOP isn't sufficient, we need to en= sure we break completely out of translated code. */ gen_save_pc(ctx->pc + 4); - ctx->bstate =3D BS_EXCP; + ctx->is_jmp =3D DISAS_EXCP; break; case 3: gen_helper_rdhwr_ccres(t0, cpu_env); @@ -10817,7 +10813,7 @@ static void gen_rdhwr(DisasContext *ctx, int rt, in= t rd, int sel) static inline void clear_branch_hflags(DisasContext *ctx) { ctx->hflags &=3D ~MIPS_HFLAG_BMASK; - if (ctx->bstate =3D=3D BS_NONE) { + if (ctx->is_jmp =3D=3D DISAS_NEXT) { save_cpu_state(ctx, 0); } else { /* it is not safe to save ctx->hflags as hflags may be changed @@ -10832,7 +10828,7 @@ static void gen_branch(DisasContext *ctx, int insn_= bytes) int proc_hflags =3D ctx->hflags & MIPS_HFLAG_BMASK; /* Branches completion */ clear_branch_hflags(ctx); - ctx->bstate =3D BS_BRANCH; + ctx->is_jmp =3D DISAS_NORETURN; /* FIXME: Need to clear can_do_io. */ switch (proc_hflags & MIPS_HFLAG_BMASK_BASE) { case MIPS_HFLAG_FBNSLOT: @@ -13574,7 +13570,7 @@ static void gen_pool32axf (CPUMIPSState *env, Disas= Context *ctx, int rt, int rs) gen_helper_di(t0, cpu_env); gen_store_gpr(t0, rs); /* Stop translation as we may have switched the execution = mode */ - ctx->bstate =3D BS_STOP; + ctx->is_jmp =3D DISAS_STOP; tcg_temp_free(t0); } break; @@ -13586,10 +13582,10 @@ static void gen_pool32axf (CPUMIPSState *env, Dis= asContext *ctx, int rt, int rs) save_cpu_state(ctx, 1); gen_helper_ei(t0, cpu_env); gen_store_gpr(t0, rs); - /* BS_STOP isn't sufficient, we need to ensure we break out + /* DISAS_STOP isn't sufficient, we need to ensure we break= out of translated code to check for pending interrupts. */ gen_save_pc(ctx->pc + 4); - ctx->bstate =3D BS_EXCP; + ctx->is_jmp =3D DISAS_EXCP; tcg_temp_free(t0); } break; @@ -14745,7 +14741,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) /* SYNCI */ /* Break the TB to be able to sync copied instructions immediately */ - ctx->bstate =3D BS_STOP; + ctx->is_jmp =3D DISAS_STOP; } else { /* TNEI */ mips32_op =3D OPC_TNEI; @@ -14776,7 +14772,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) check_insn_opc_removed(ctx, ISA_MIPS32R6); /* Break the TB to be able to sync copied instructions immediately */ - ctx->bstate =3D BS_STOP; + ctx->is_jmp =3D DISAS_STOP; break; case BC2F: case BC2T: @@ -19601,7 +19597,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) check_insn(ctx, ISA_MIPS32R2); /* Break the TB to be able to sync copied instructions immediately */ - ctx->bstate =3D BS_STOP; + ctx->is_jmp =3D DISAS_STOP; break; case OPC_BPOSGE32: /* MIPS DSP branch */ #if defined(TARGET_MIPS64) @@ -19704,17 +19700,17 @@ static void decode_opc(CPUMIPSState *env, DisasCo= ntext *ctx) gen_store_gpr(t0, rt); /* Stop translation as we may have switched the execution mode. */ - ctx->bstate =3D BS_STOP; + ctx->is_jmp =3D DISAS_STOP; break; case OPC_EI: check_insn(ctx, ISA_MIPS32R2); save_cpu_state(ctx, 1); gen_helper_ei(t0, cpu_env); gen_store_gpr(t0, rt); - /* BS_STOP isn't sufficient, we need to ensure we brea= k out - of translated code to check for pending interrupts.= */ + /* DISAS_STOP isn't sufficient, we need to ensure we b= reak + out of translated code to check for pending interru= pts */ gen_save_pc(ctx->pc + 4); - ctx->bstate =3D BS_EXCP; + ctx->is_jmp =3D DISAS_EXCP; break; default: /* Invalid */ MIPS_INVAL("mfmc0"); @@ -20216,7 +20212,7 @@ void gen_intermediate_code(CPUState *cs, struct Tra= nslationBlock *tb) ctx.insn_flags =3D env->insn_flags; ctx.CP0_Config1 =3D env->CP0_Config1; ctx.tb =3D tb; - ctx.bstate =3D BS_NONE; + ctx.is_jmp =3D DISAS_NEXT; ctx.btarget =3D 0; ctx.kscrexist =3D (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff; ctx.rxi =3D (env->CP0_Config3 >> CP0C3_RXI) & 1; @@ -20257,13 +20253,13 @@ void gen_intermediate_code(CPUState *cs, struct T= ranslationBlock *tb) =20 LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx.mem_idx, ctx.hflags); gen_tb_start(tb); - while (ctx.bstate =3D=3D BS_NONE) { + while (ctx.is_jmp =3D=3D DISAS_NEXT) { tcg_gen_insn_start(ctx.pc, ctx.hflags & MIPS_HFLAG_BMASK, ctx.btar= get); num_insns++; =20 if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) { save_cpu_state(&ctx, 1); - ctx.bstate =3D BS_BRANCH; + ctx.is_jmp =3D DISAS_NORETURN; gen_helper_raise_exception_debug(cpu_env); /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be @@ -20337,22 +20333,22 @@ void gen_intermediate_code(CPUState *cs, struct T= ranslationBlock *tb) if (tb_cflags(tb) & CF_LAST_IO) { gen_io_end(); } - if (cs->singlestep_enabled && ctx.bstate !=3D BS_BRANCH) { - save_cpu_state(&ctx, ctx.bstate !=3D BS_EXCP); + if (cs->singlestep_enabled && ctx.is_jmp !=3D DISAS_NORETURN) { + save_cpu_state(&ctx, ctx.is_jmp !=3D DISAS_EXCP); gen_helper_raise_exception_debug(cpu_env); } else { - switch (ctx.bstate) { - case BS_STOP: + switch (ctx.is_jmp) { + case DISAS_STOP: gen_goto_tb(&ctx, 0, ctx.pc); break; - case BS_NONE: + case DISAS_NEXT: save_cpu_state(&ctx, 0); gen_goto_tb(&ctx, 0, ctx.pc); break; - case BS_EXCP: + case DISAS_EXCP: tcg_gen_exit_tb(0); break; - case BS_BRANCH: + case DISAS_NORETURN: default: break; } --=20 2.7.4 From nobody Fri Oct 24 09:56:51 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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Cota" To: qemu-devel@nongnu.org Date: Thu, 15 Feb 2018 21:02:50 -0500 Message-Id: <1518746572-14747-3-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1518746572-14747-1-git-send-email-cota@braap.org> References: <1518746572-14747-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.29 Subject: [Qemu-devel] [PATCH 2/4] target/mips: convert to DisasContextBase X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yongbok Kim , Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Emilio G. Cota --- target/mips/translate.c | 346 ++++++++++++++++++++++++--------------------= ---- 1 file changed, 175 insertions(+), 171 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index a133205..aefd729 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1430,17 +1430,15 @@ static TCGv_i64 msa_wr_d[64]; } while(0) =20 typedef struct DisasContext { - struct TranslationBlock *tb; - target_ulong pc, saved_pc; + DisasContextBase base; + target_ulong saved_pc; uint32_t opcode; - int singlestep_enabled; int insn_flags; int32_t CP0_Config1; /* Routine used to access memory */ int mem_idx; TCGMemOp default_tcg_memop_mask; uint32_t hflags, saved_hflags; - DisasJumpType is_jmp; target_ulong btarget; bool ulri; int kscrexist; @@ -1517,8 +1515,9 @@ static const char * const msaregnames[] =3D { if (MIPS_DEBUG_DISAS) { = \ qemu_log_mask(CPU_LOG_TB_IN_ASM, = \ TARGET_FMT_lx ": %08x Invalid %s %03x %03x %03x\= n", \ - ctx->pc, ctx->opcode, op, ctx->opcode >> 26, = \ - ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)= ); \ + ctx->base.pc_next, ctx->opcode, op, = \ + ctx->opcode >> 26, ctx->opcode & 0x3F, = \ + ((ctx->opcode >> 16) & 0x1F)); = \ } = \ } while (0) =20 @@ -1594,9 +1593,9 @@ static inline void gen_save_pc(target_ulong pc) static inline void save_cpu_state(DisasContext *ctx, int do_save_pc) { LOG_DISAS("hflags %08x saved %08x\n", ctx->hflags, ctx->saved_hflags); - if (do_save_pc && ctx->pc !=3D ctx->saved_pc) { - gen_save_pc(ctx->pc); - ctx->saved_pc =3D ctx->pc; + if (do_save_pc && ctx->base.pc_next !=3D ctx->saved_pc) { + gen_save_pc(ctx->base.pc_next); + ctx->saved_pc =3D ctx->base.pc_next; } if (ctx->hflags !=3D ctx->saved_hflags) { tcg_gen_movi_i32(hflags, ctx->hflags); @@ -1635,7 +1634,7 @@ static inline void generate_exception_err(DisasContex= t *ctx, int excp, int err) gen_helper_raise_exception_err(cpu_env, texcp, terr); tcg_temp_free_i32(terr); tcg_temp_free_i32(texcp); - ctx->is_jmp =3D DISAS_EXCP; + ctx->base.is_jmp =3D DISAS_EXCP; } =20 static inline void generate_exception(DisasContext *ctx, int excp) @@ -2126,7 +2125,7 @@ static void gen_base_offset_addr (DisasContext *ctx, = TCGv addr, =20 static target_ulong pc_relative_pc (DisasContext *ctx) { - target_ulong pc =3D ctx->pc; + target_ulong pc =3D ctx->base.pc_next; =20 if (ctx->hflags & MIPS_HFLAG_BMASK) { int branch_bytes =3D ctx->hflags & MIPS_HFLAG_BDS16 ? 2 : 4; @@ -4275,12 +4274,12 @@ static void gen_trap (DisasContext *ctx, uint32_t o= pc, =20 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) { - if (unlikely(ctx->singlestep_enabled)) { + if (unlikely(ctx->base.singlestep_enabled)) { return false; } =20 #ifndef CONFIG_USER_ONLY - return (ctx->tb->pc & TARGET_PAGE_MASK) =3D=3D (dest & TARGET_PAGE_MAS= K); + return (ctx->base.tb->pc & TARGET_PAGE_MASK) =3D=3D (dest & TARGET_PAG= E_MASK); #else return true; #endif @@ -4291,10 +4290,10 @@ static inline void gen_goto_tb(DisasContext *ctx, i= nt n, target_ulong dest) if (use_goto_tb(ctx, dest)) { tcg_gen_goto_tb(n); gen_save_pc(dest); - tcg_gen_exit_tb((uintptr_t)ctx->tb + n); + tcg_gen_exit_tb((uintptr_t)ctx->base.tb + n); } else { gen_save_pc(dest); - if (ctx->singlestep_enabled) { + if (ctx->base.singlestep_enabled) { save_cpu_state(ctx, 0); gen_helper_raise_exception_debug(cpu_env); } @@ -4317,7 +4316,7 @@ static void gen_compute_branch (DisasContext *ctx, ui= nt32_t opc, if (ctx->hflags & MIPS_HFLAG_BMASK) { #ifdef MIPS_DEBUG_DISAS LOG_DISAS("Branch in delay / forbidden slot at PC 0x" - TARGET_FMT_lx "\n", ctx->pc); + TARGET_FMT_lx "\n", ctx->base.pc_next); #endif generate_exception_end(ctx, EXCP_RI); goto out; @@ -4335,7 +4334,7 @@ static void gen_compute_branch (DisasContext *ctx, ui= nt32_t opc, gen_load_gpr(t1, rt); bcond_compute =3D 1; } - btgt =3D ctx->pc + insn_bytes + offset; + btgt =3D ctx->base.pc_next + insn_bytes + offset; break; case OPC_BGEZ: case OPC_BGEZAL: @@ -4354,7 +4353,7 @@ static void gen_compute_branch (DisasContext *ctx, ui= nt32_t opc, gen_load_gpr(t0, rs); bcond_compute =3D 1; } - btgt =3D ctx->pc + insn_bytes + offset; + btgt =3D ctx->base.pc_next + insn_bytes + offset; break; case OPC_BPOSGE32: #if defined(TARGET_MIPS64) @@ -4364,13 +4363,14 @@ static void gen_compute_branch (DisasContext *ctx, = uint32_t opc, tcg_gen_andi_tl(t0, cpu_dspctrl, 0x3F); #endif bcond_compute =3D 1; - btgt =3D ctx->pc + insn_bytes + offset; + btgt =3D ctx->base.pc_next + insn_bytes + offset; break; case OPC_J: case OPC_JAL: case OPC_JALX: /* Jump to immediate */ - btgt =3D ((ctx->pc + insn_bytes) & (int32_t)0xF0000000) | (uint32_= t)offset; + btgt =3D ((ctx->base.pc_next + insn_bytes) & (int32_t)0xF0000000) | + (uint32_t)offset; break; case OPC_JR: case OPC_JALR: @@ -4416,19 +4416,19 @@ static void gen_compute_branch (DisasContext *ctx, = uint32_t opc, /* Handle as an unconditional branch to get correct delay slot checking. */ blink =3D 31; - btgt =3D ctx->pc + insn_bytes + delayslot_size; + btgt =3D ctx->base.pc_next + insn_bytes + delayslot_size; ctx->hflags |=3D MIPS_HFLAG_B; break; case OPC_BLTZALL: /* 0 < 0 likely */ - tcg_gen_movi_tl(cpu_gpr[31], ctx->pc + 8); + tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 8); /* Skip the instruction in the delay slot */ - ctx->pc +=3D 4; + ctx->base.pc_next +=3D 4; goto out; case OPC_BNEL: /* rx !=3D rx likely */ case OPC_BGTZL: /* 0 > 0 likely */ case OPC_BLTZL: /* 0 < 0 likely */ /* Skip the instruction in the delay slot */ - ctx->pc +=3D 4; + ctx->base.pc_next +=3D 4; goto out; case OPC_J: ctx->hflags |=3D MIPS_HFLAG_B; @@ -4540,7 +4540,8 @@ static void gen_compute_branch (DisasContext *ctx, ui= nt32_t opc, int post_delay =3D insn_bytes + delayslot_size; int lowbit =3D !!(ctx->hflags & MIPS_HFLAG_M16); =20 - tcg_gen_movi_tl(cpu_gpr[blink], ctx->pc + post_delay + lowbit); + tcg_gen_movi_tl(cpu_gpr[blink], + ctx->base.pc_next + post_delay + lowbit); } =20 out: @@ -5322,18 +5323,18 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) switch (sel) { case 0: /* Mark as an IO operation because we read the time. */ - if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_mfc0_count(arg, cpu_env); - if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { gen_io_end(); } /* Break the TB to be able to take timer interrupts immediately after reading count. DISAS_STOP isn't sufficient, we need to ensure we break completely out of translated code. */ - gen_save_pc(ctx->pc + 4); - ctx->is_jmp =3D DISAS_EXCP; + gen_save_pc(ctx->base.pc_next + 4); + ctx->base.is_jmp =3D DISAS_EXCP; rn =3D "Count"; break; /* 6,7 are implementation dependent */ @@ -5729,7 +5730,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) if (sel !=3D 0) check_insn(ctx, ISA_MIPS32); =20 - if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } =20 @@ -5901,7 +5902,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_pagegrain(cpu_env, arg); rn =3D "PageGrain"; - ctx->is_jmp =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; break; case 2: CP0_CHECK(ctx->sc); @@ -5962,7 +5963,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case 0: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_hwrena(cpu_env, arg); - ctx->is_jmp =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; rn =3D "HWREna"; break; default: @@ -6025,29 +6026,29 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) save_cpu_state(ctx, 1); gen_helper_mtc0_status(cpu_env, arg); /* DISAS_STOP isn't good enough here, hflags may have changed.= */ - gen_save_pc(ctx->pc + 4); - ctx->is_jmp =3D DISAS_EXCP; + gen_save_pc(ctx->base.pc_next + 4); + ctx->base.is_jmp =3D DISAS_EXCP; rn =3D "Status"; break; case 1: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_intctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode= */ - ctx->is_jmp =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; rn =3D "IntCtl"; break; case 2: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode= */ - ctx->is_jmp =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; rn =3D "SRSCtl"; break; case 3: check_insn(ctx, ISA_MIPS32R2); gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); /* Stop translation as we may have switched the execution mode= */ - ctx->is_jmp =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; rn =3D "SRSMap"; break; default: @@ -6062,8 +6063,8 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) /* Stop translation as we may have triggered an interrupt. * DISAS_STOP isn't sufficient, we need to ensure we break out= of * translated code to check for pending interrupts. */ - gen_save_pc(ctx->pc + 4); - ctx->is_jmp =3D DISAS_EXCP; + gen_save_pc(ctx->base.pc_next + 4); + ctx->base.is_jmp =3D DISAS_EXCP; rn =3D "Cause"; break; default: @@ -6101,7 +6102,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) gen_helper_mtc0_config0(cpu_env, arg); rn =3D "Config"; /* Stop translation as we may have switched the execution mode= */ - ctx->is_jmp =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; break; case 1: /* ignored, read only */ @@ -6111,24 +6112,24 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) gen_helper_mtc0_config2(cpu_env, arg); rn =3D "Config2"; /* Stop translation as we may have switched the execution mode= */ - ctx->is_jmp =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; break; case 3: gen_helper_mtc0_config3(cpu_env, arg); rn =3D "Config3"; /* Stop translation as we may have switched the execution mode= */ - ctx->is_jmp =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; break; case 4: gen_helper_mtc0_config4(cpu_env, arg); rn =3D "Config4"; - ctx->is_jmp =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; break; case 5: gen_helper_mtc0_config5(cpu_env, arg); rn =3D "Config5"; /* Stop translation as we may have switched the execution mode= */ - ctx->is_jmp =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; break; /* 6,7 are implementation dependent */ case 6: @@ -6218,34 +6219,34 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) case 0: gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */ /* DISAS_STOP isn't good enough here, hflags may have changed.= */ - gen_save_pc(ctx->pc + 4); - ctx->is_jmp =3D DISAS_EXCP; + gen_save_pc(ctx->base.pc_next + 4); + ctx->base.is_jmp =3D DISAS_EXCP; rn =3D "Debug"; break; case 1: // gen_helper_mtc0_tracecontrol(cpu_env, arg); /* PDtrace suppo= rt */ rn =3D "TraceControl"; /* Stop translation as we may have switched the execution mode= */ - ctx->is_jmp =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; goto cp0_unimplemented; case 2: // gen_helper_mtc0_tracecontrol2(cpu_env, arg); /* PDtrace supp= ort */ rn =3D "TraceControl2"; /* Stop translation as we may have switched the execution mode= */ - ctx->is_jmp =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; goto cp0_unimplemented; case 3: /* Stop translation as we may have switched the execution mode= */ - ctx->is_jmp =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; // gen_helper_mtc0_usertracedata(cpu_env, arg); /* PDtrace supp= ort */ rn =3D "UserTraceData"; /* Stop translation as we may have switched the execution mode= */ - ctx->is_jmp =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; goto cp0_unimplemented; case 4: // gen_helper_mtc0_tracebpc(cpu_env, arg); /* PDtrace support */ /* Stop translation as we may have switched the execution mode= */ - ctx->is_jmp =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; rn =3D "TraceBPC"; goto cp0_unimplemented; default: @@ -6305,7 +6306,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) switch (sel) { case 0: gen_helper_mtc0_errctl(cpu_env, arg); - ctx->is_jmp =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; rn =3D "ErrCtl"; break; default: @@ -6396,12 +6397,12 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) trace_mips_translate_c0("mtc0", rn, reg, sel); =20 /* For simplicity assume that all writes can cause interrupts. */ - if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { gen_io_end(); /* DISAS_STOP isn't sufficient, we need to ensure we break out of * translated code to check for pending interrupts. */ - gen_save_pc(ctx->pc + 4); - ctx->is_jmp =3D DISAS_EXCP; + gen_save_pc(ctx->base.pc_next + 4); + ctx->base.is_jmp =3D DISAS_EXCP; } return; =20 @@ -6674,18 +6675,18 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) switch (sel) { case 0: /* Mark as an IO operation because we read the time. */ - if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_mfc0_count(arg, cpu_env); - if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { gen_io_end(); } /* Break the TB to be able to take timer interrupts immediately after reading count. DISAS_STOP isn't sufficient, we need to ensure we break completely out of translated code. */ - gen_save_pc(ctx->pc + 4); - ctx->is_jmp =3D DISAS_EXCP; + gen_save_pc(ctx->base.pc_next + 4); + ctx->base.is_jmp =3D DISAS_EXCP; rn =3D "Count"; break; /* 6,7 are implementation dependent */ @@ -7067,7 +7068,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) if (sel !=3D 0) check_insn(ctx, ISA_MIPS64); =20 - if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } =20 @@ -7297,7 +7298,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) case 0: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_hwrena(cpu_env, arg); - ctx->is_jmp =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; rn =3D "HWREna"; break; default: @@ -7333,7 +7334,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } /* Stop translation as we may have switched the execution mode */ - ctx->is_jmp =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; break; case 10: switch (sel) { @@ -7356,7 +7357,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } /* Stop translation as we may have switched the execution mode */ - ctx->is_jmp =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; break; case 12: switch (sel) { @@ -7364,29 +7365,29 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) save_cpu_state(ctx, 1); gen_helper_mtc0_status(cpu_env, arg); /* DISAS_STOP isn't good enough here, hflags may have changed.= */ - gen_save_pc(ctx->pc + 4); - ctx->is_jmp =3D DISAS_EXCP; + gen_save_pc(ctx->base.pc_next + 4); + ctx->base.is_jmp =3D DISAS_EXCP; rn =3D "Status"; break; case 1: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_intctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode= */ - ctx->is_jmp =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; rn =3D "IntCtl"; break; case 2: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode= */ - ctx->is_jmp =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; rn =3D "SRSCtl"; break; case 3: check_insn(ctx, ISA_MIPS32R2); gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); /* Stop translation as we may have switched the execution mode= */ - ctx->is_jmp =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; rn =3D "SRSMap"; break; default: @@ -7401,8 +7402,8 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) /* Stop translation as we may have triggered an intetrupt. * DISAS_STOP isn't sufficient, we need to ensure we break out= of * translated code to check for pending interrupts. */ - gen_save_pc(ctx->pc + 4); - ctx->is_jmp =3D DISAS_EXCP; + gen_save_pc(ctx->base.pc_next + 4); + ctx->base.is_jmp =3D DISAS_EXCP; rn =3D "Cause"; break; default: @@ -7440,7 +7441,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) gen_helper_mtc0_config0(cpu_env, arg); rn =3D "Config"; /* Stop translation as we may have switched the execution mode= */ - ctx->is_jmp =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; break; case 1: /* ignored, read only */ @@ -7450,13 +7451,13 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) gen_helper_mtc0_config2(cpu_env, arg); rn =3D "Config2"; /* Stop translation as we may have switched the execution mode= */ - ctx->is_jmp =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; break; case 3: gen_helper_mtc0_config3(cpu_env, arg); rn =3D "Config3"; /* Stop translation as we may have switched the execution mode= */ - ctx->is_jmp =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; break; case 4: /* currently ignored */ @@ -7466,7 +7467,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) gen_helper_mtc0_config5(cpu_env, arg); rn =3D "Config5"; /* Stop translation as we may have switched the execution mode= */ - ctx->is_jmp =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; break; /* 6,7 are implementation dependent */ default: @@ -7546,32 +7547,32 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) case 0: gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */ /* DISAS_STOP isn't good enough here, hflags may have changed.= */ - gen_save_pc(ctx->pc + 4); - ctx->is_jmp =3D DISAS_EXCP; + gen_save_pc(ctx->base.pc_next + 4); + ctx->base.is_jmp =3D DISAS_EXCP; rn =3D "Debug"; break; case 1: // gen_helper_mtc0_tracecontrol(cpu_env, arg); /* PDtrace suppo= rt */ /* Stop translation as we may have switched the execution mode= */ - ctx->is_jmp =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; rn =3D "TraceControl"; goto cp0_unimplemented; case 2: // gen_helper_mtc0_tracecontrol2(cpu_env, arg); /* PDtrace supp= ort */ /* Stop translation as we may have switched the execution mode= */ - ctx->is_jmp =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; rn =3D "TraceControl2"; goto cp0_unimplemented; case 3: // gen_helper_mtc0_usertracedata(cpu_env, arg); /* PDtrace supp= ort */ /* Stop translation as we may have switched the execution mode= */ - ctx->is_jmp =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; rn =3D "UserTraceData"; goto cp0_unimplemented; case 4: // gen_helper_mtc0_tracebpc(cpu_env, arg); /* PDtrace support */ /* Stop translation as we may have switched the execution mode= */ - ctx->is_jmp =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; rn =3D "TraceBPC"; goto cp0_unimplemented; default: @@ -7631,7 +7632,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) switch (sel) { case 0: gen_helper_mtc0_errctl(cpu_env, arg); - ctx->is_jmp =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; rn =3D "ErrCtl"; break; default: @@ -7722,12 +7723,12 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) trace_mips_translate_c0("dmtc0", rn, reg, sel); =20 /* For simplicity assume that all writes can cause interrupts. */ - if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { gen_io_end(); /* DISAS_STOP isn't sufficient, we need to ensure we break out of * translated code to check for pending interrupts. */ - gen_save_pc(ctx->pc + 4); - ctx->is_jmp =3D DISAS_EXCP; + gen_save_pc(ctx->base.pc_next + 4); + ctx->base.is_jmp =3D DISAS_EXCP; } return; =20 @@ -8138,7 +8139,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext = *ctx, int rd, int rt, tcg_temp_free_i32(fs_tmp); } /* Stop translation as we may have changed hflags */ - ctx->is_jmp =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; break; /* COP2: Not implemented. */ case 4: @@ -8297,7 +8298,7 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext = *ctx, uint32_t opc, int rt, check_insn(ctx, ISA_MIPS2); gen_helper_eret(cpu_env); } - ctx->is_jmp =3D DISAS_EXCP; + ctx->base.is_jmp =3D DISAS_EXCP; } break; case OPC_DERET: @@ -8312,7 +8313,7 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext = *ctx, uint32_t opc, int rt, generate_exception_end(ctx, EXCP_RI); } else { gen_helper_deret(cpu_env); - ctx->is_jmp =3D DISAS_EXCP; + ctx->base.is_jmp =3D DISAS_EXCP; } break; case OPC_WAIT: @@ -8323,11 +8324,11 @@ static void gen_cp0 (CPUMIPSState *env, DisasContex= t *ctx, uint32_t opc, int rt, goto die; } /* If we get an exception, we want to restart at next instruction = */ - ctx->pc +=3D 4; + ctx->base.pc_next +=3D 4; save_cpu_state(ctx, 1); - ctx->pc -=3D 4; + ctx->base.pc_next -=3D 4; gen_helper_wait(cpu_env); - ctx->is_jmp =3D DISAS_EXCP; + ctx->base.is_jmp =3D DISAS_EXCP; break; default: die: @@ -8354,7 +8355,7 @@ static void gen_compute_branch1(DisasContext *ctx, ui= nt32_t op, if (cc !=3D 0) check_insn(ctx, ISA_MIPS4 | ISA_MIPS32); =20 - btarget =3D ctx->pc + 4 + offset; + btarget =3D ctx->base.pc_next + 4 + offset; =20 switch (op) { case OPC_BC1F: @@ -8457,7 +8458,7 @@ static void gen_compute_branch1_r6(DisasContext *ctx,= uint32_t op, if (ctx->hflags & MIPS_HFLAG_BMASK) { #ifdef MIPS_DEBUG_DISAS LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx - "\n", ctx->pc); + "\n", ctx->base.pc_next); #endif generate_exception_end(ctx, EXCP_RI); goto out; @@ -8466,7 +8467,7 @@ static void gen_compute_branch1_r6(DisasContext *ctx,= uint32_t op, gen_load_fpr64(ctx, t0, ft); tcg_gen_andi_i64(t0, t0, 1); =20 - btarget =3D addr_add(ctx, ctx->pc + 4, offset); + btarget =3D addr_add(ctx, ctx->base.pc_next + 4, offset); =20 switch (op) { case OPC_BC1EQZ: @@ -8752,7 +8753,7 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc,= int rt, int fs) tcg_temp_free_i32(fs_tmp); } /* Stop translation as we may have changed hflags */ - ctx->is_jmp =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; break; #if defined(TARGET_MIPS64) case OPC_DMFC1: @@ -10751,19 +10752,19 @@ static void gen_rdhwr(DisasContext *ctx, int rt, = int rd, int sel) gen_store_gpr(t0, rt); break; case 2: - if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_rdhwr_cc(t0, cpu_env); - if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { gen_io_end(); } gen_store_gpr(t0, rt); /* Break the TB to be able to take timer interrupts immediately after reading count. DISAS_STOP isn't sufficient, we need to en= sure we break completely out of translated code. */ - gen_save_pc(ctx->pc + 4); - ctx->is_jmp =3D DISAS_EXCP; + gen_save_pc(ctx->base.pc_next + 4); + ctx->base.is_jmp =3D DISAS_EXCP; break; case 3: gen_helper_rdhwr_ccres(t0, cpu_env); @@ -10813,7 +10814,7 @@ static void gen_rdhwr(DisasContext *ctx, int rt, in= t rd, int sel) static inline void clear_branch_hflags(DisasContext *ctx) { ctx->hflags &=3D ~MIPS_HFLAG_BMASK; - if (ctx->is_jmp =3D=3D DISAS_NEXT) { + if (ctx->base.is_jmp =3D=3D DISAS_NEXT) { save_cpu_state(ctx, 0); } else { /* it is not safe to save ctx->hflags as hflags may be changed @@ -10828,11 +10829,11 @@ static void gen_branch(DisasContext *ctx, int ins= n_bytes) int proc_hflags =3D ctx->hflags & MIPS_HFLAG_BMASK; /* Branches completion */ clear_branch_hflags(ctx); - ctx->is_jmp =3D DISAS_NORETURN; + ctx->base.is_jmp =3D DISAS_NORETURN; /* FIXME: Need to clear can_do_io. */ switch (proc_hflags & MIPS_HFLAG_BMASK_BASE) { case MIPS_HFLAG_FBNSLOT: - gen_goto_tb(ctx, 0, ctx->pc + insn_bytes); + gen_goto_tb(ctx, 0, ctx->base.pc_next + insn_bytes); break; case MIPS_HFLAG_B: /* unconditional branch */ @@ -10851,7 +10852,7 @@ static void gen_branch(DisasContext *ctx, int insn_= bytes) TCGLabel *l1 =3D gen_new_label(); =20 tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1); - gen_goto_tb(ctx, 1, ctx->pc + insn_bytes); + gen_goto_tb(ctx, 1, ctx->base.pc_next + insn_bytes); gen_set_label(l1); gen_goto_tb(ctx, 0, ctx->btarget); } @@ -10874,7 +10875,7 @@ static void gen_branch(DisasContext *ctx, int insn_= bytes) } else { tcg_gen_mov_tl(cpu_PC, btarget); } - if (ctx->singlestep_enabled) { + if (ctx->base.singlestep_enabled) { save_cpu_state(ctx, 0); gen_helper_raise_exception_debug(cpu_env); } @@ -10899,7 +10900,7 @@ static void gen_compute_compact_branch(DisasContext= *ctx, uint32_t opc, if (ctx->hflags & MIPS_HFLAG_BMASK) { #ifdef MIPS_DEBUG_DISAS LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx - "\n", ctx->pc); + "\n", ctx->base.pc_next); #endif generate_exception_end(ctx, EXCP_RI); goto out; @@ -10913,10 +10914,10 @@ static void gen_compute_compact_branch(DisasConte= xt *ctx, uint32_t opc, gen_load_gpr(t0, rs); gen_load_gpr(t1, rt); bcond_compute =3D 1; - ctx->btarget =3D addr_add(ctx, ctx->pc + 4, offset); + ctx->btarget =3D addr_add(ctx, ctx->base.pc_next + 4, offset); if (rs <=3D rt && rs =3D=3D 0) { /* OPC_BEQZALC, OPC_BNEZALC */ - tcg_gen_movi_tl(cpu_gpr[31], ctx->pc + 4 + m16_lowbit); + tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbi= t); } break; case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC */ @@ -10924,23 +10925,23 @@ static void gen_compute_compact_branch(DisasConte= xt *ctx, uint32_t opc, gen_load_gpr(t0, rs); gen_load_gpr(t1, rt); bcond_compute =3D 1; - ctx->btarget =3D addr_add(ctx, ctx->pc + 4, offset); + ctx->btarget =3D addr_add(ctx, ctx->base.pc_next + 4, offset); break; case OPC_BLEZALC: /* OPC_BGEZALC, OPC_BGEUC */ case OPC_BGTZALC: /* OPC_BLTZALC, OPC_BLTUC */ if (rs =3D=3D 0 || rs =3D=3D rt) { /* OPC_BLEZALC, OPC_BGEZALC */ /* OPC_BGTZALC, OPC_BLTZALC */ - tcg_gen_movi_tl(cpu_gpr[31], ctx->pc + 4 + m16_lowbit); + tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbi= t); } gen_load_gpr(t0, rs); gen_load_gpr(t1, rt); bcond_compute =3D 1; - ctx->btarget =3D addr_add(ctx, ctx->pc + 4, offset); + ctx->btarget =3D addr_add(ctx, ctx->base.pc_next + 4, offset); break; case OPC_BC: case OPC_BALC: - ctx->btarget =3D addr_add(ctx, ctx->pc + 4, offset); + ctx->btarget =3D addr_add(ctx, ctx->base.pc_next + 4, offset); break; case OPC_BEQZC: case OPC_BNEZC: @@ -10948,7 +10949,7 @@ static void gen_compute_compact_branch(DisasContext= *ctx, uint32_t opc, /* OPC_BEQZC, OPC_BNEZC */ gen_load_gpr(t0, rs); bcond_compute =3D 1; - ctx->btarget =3D addr_add(ctx, ctx->pc + 4, offset); + ctx->btarget =3D addr_add(ctx, ctx->base.pc_next + 4, offset); } else { /* OPC_JIC, OPC_JIALC */ TCGv tbase =3D tcg_temp_new(); @@ -10971,13 +10972,13 @@ static void gen_compute_compact_branch(DisasConte= xt *ctx, uint32_t opc, /* Uncoditional compact branch */ switch (opc) { case OPC_JIALC: - tcg_gen_movi_tl(cpu_gpr[31], ctx->pc + 4 + m16_lowbit); + tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbi= t); /* Fallthrough */ case OPC_JIC: ctx->hflags |=3D MIPS_HFLAG_BR; break; case OPC_BALC: - tcg_gen_movi_tl(cpu_gpr[31], ctx->pc + 4 + m16_lowbit); + tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbi= t); /* Fallthrough */ case OPC_BC: ctx->hflags |=3D MIPS_HFLAG_B; @@ -11602,7 +11603,7 @@ static void decode_i64_mips16 (DisasContext *ctx, =20 static int decode_extended_mips16_opc (CPUMIPSState *env, DisasContext *ct= x) { - int extend =3D cpu_lduw_code(env, ctx->pc + 2); + int extend =3D cpu_lduw_code(env, ctx->base.pc_next + 2); int op, rx, ry, funct, sa; int16_t imm, offset; =20 @@ -11842,7 +11843,7 @@ static int decode_mips16_opc (CPUMIPSState *env, Di= sasContext *ctx) /* No delay slot, so just process as a normal instruction */ break; case M16_OPC_JAL: - offset =3D cpu_lduw_code(env, ctx->pc + 2); + offset =3D cpu_lduw_code(env, ctx->base.pc_next + 2); offset =3D (((ctx->opcode & 0x1f) << 21) | ((ctx->opcode >> 5) & 0x1f) << 16 | offset) << 2; @@ -13570,7 +13571,7 @@ static void gen_pool32axf (CPUMIPSState *env, Disas= Context *ctx, int rt, int rs) gen_helper_di(t0, cpu_env); gen_store_gpr(t0, rs); /* Stop translation as we may have switched the execution = mode */ - ctx->is_jmp =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; tcg_temp_free(t0); } break; @@ -13584,8 +13585,8 @@ static void gen_pool32axf (CPUMIPSState *env, Disas= Context *ctx, int rt, int rs) gen_store_gpr(t0, rs); /* DISAS_STOP isn't sufficient, we need to ensure we break= out of translated code to check for pending interrupts. */ - gen_save_pc(ctx->pc + 4); - ctx->is_jmp =3D DISAS_EXCP; + gen_save_pc(ctx->base.pc_next + 4); + ctx->base.is_jmp =3D DISAS_EXCP; tcg_temp_free(t0); } break; @@ -13940,7 +13941,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) uint32_t op, minor, minor2, mips32_op; uint32_t cond, fmt, cc; =20 - insn =3D cpu_lduw_code(env, ctx->pc + 2); + insn =3D cpu_lduw_code(env, ctx->base.pc_next + 2); ctx->opcode =3D (ctx->opcode << 16) | insn; =20 rt =3D (ctx->opcode >> 21) & 0x1f; @@ -14741,7 +14742,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) /* SYNCI */ /* Break the TB to be able to sync copied instructions immediately */ - ctx->is_jmp =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; } else { /* TNEI */ mips32_op =3D OPC_TNEI; @@ -14772,7 +14773,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) check_insn_opc_removed(ctx, ISA_MIPS32R6); /* Break the TB to be able to sync copied instructions immediately */ - ctx->is_jmp =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; break; case BC2F: case BC2T: @@ -15135,16 +15136,16 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) /* PCREL: ADDIUPC, AUIPC, ALUIPC, LWPC */ switch ((ctx->opcode >> 16) & 0x1f) { case ADDIUPC_00 ... ADDIUPC_07: - gen_pcrel(ctx, OPC_ADDIUPC, ctx->pc & ~0x3, rt); + gen_pcrel(ctx, OPC_ADDIUPC, ctx->base.pc_next & ~0x3, rt); break; case AUIPC: - gen_pcrel(ctx, OPC_AUIPC, ctx->pc, rt); + gen_pcrel(ctx, OPC_AUIPC, ctx->base.pc_next, rt); break; case ALUIPC: - gen_pcrel(ctx, OPC_ALUIPC, ctx->pc, rt); + gen_pcrel(ctx, OPC_ALUIPC, ctx->base.pc_next, rt); break; case LWPC_08 ... LWPC_0F: - gen_pcrel(ctx, R6_OPC_LWPC, ctx->pc & ~0x3, rt); + gen_pcrel(ctx, R6_OPC_LWPC, ctx->base.pc_next & ~0x3, rt); break; default: generate_exception(ctx, EXCP_RI); @@ -15276,8 +15277,8 @@ static int decode_micromips_opc (CPUMIPSState *env,= DisasContext *ctx) uint32_t op; =20 /* make sure instructions are on a halfword boundary */ - if (ctx->pc & 0x1) { - env->CP0_BadVAddr =3D ctx->pc; + if (ctx->base.pc_next & 0x1) { + env->CP0_BadVAddr =3D ctx->base.pc_next; generate_exception_end(ctx, EXCP_AdEL); return 2; } @@ -18503,7 +18504,7 @@ static void gen_msa_branch(CPUMIPSState *env, Disas= Context *ctx, uint32_t op1) break; } =20 - ctx->btarget =3D ctx->pc + (s16 << 2) + 4; + ctx->btarget =3D ctx->base.pc_next + (s16 << 2) + 4; =20 ctx->hflags |=3D MIPS_HFLAG_BC; ctx->hflags |=3D MIPS_HFLAG_BDS32; @@ -19524,8 +19525,8 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) int16_t imm; =20 /* make sure instructions are on a word boundary */ - if (ctx->pc & 0x3) { - env->CP0_BadVAddr =3D ctx->pc; + if (ctx->base.pc_next & 0x3) { + env->CP0_BadVAddr =3D ctx->base.pc_next; generate_exception_err(ctx, EXCP_AdEL, EXCP_INST_NOTAVAIL); return; } @@ -19536,7 +19537,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) =20 tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1); tcg_gen_movi_i32(hflags, ctx->hflags & ~MIPS_HFLAG_BMASK); - gen_goto_tb(ctx, 1, ctx->pc + 4); + gen_goto_tb(ctx, 1, ctx->base.pc_next + 4); gen_set_label(l1); } =20 @@ -19597,7 +19598,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) check_insn(ctx, ISA_MIPS32R2); /* Break the TB to be able to sync copied instructions immediately */ - ctx->is_jmp =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; break; case OPC_BPOSGE32: /* MIPS DSP branch */ #if defined(TARGET_MIPS64) @@ -19700,7 +19701,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) gen_store_gpr(t0, rt); /* Stop translation as we may have switched the execution mode. */ - ctx->is_jmp =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; break; case OPC_EI: check_insn(ctx, ISA_MIPS32R2); @@ -19709,8 +19710,8 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) gen_store_gpr(t0, rt); /* DISAS_STOP isn't sufficient, we need to ensure we b= reak out of translated code to check for pending interru= pts */ - gen_save_pc(ctx->pc + 4); - ctx->is_jmp =3D DISAS_EXCP; + gen_save_pc(ctx->base.pc_next + 4); + ctx->base.is_jmp =3D DISAS_EXCP; break; default: /* Invalid */ MIPS_INVAL("mfmc0"); @@ -20184,7 +20185,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) break; case OPC_PCREL: check_insn(ctx, ISA_MIPS32R6); - gen_pcrel(ctx, ctx->opcode, ctx->pc, rs); + gen_pcrel(ctx, ctx->opcode, ctx->base.pc_next, rs); break; default: /* Invalid */ MIPS_INVAL("major opcode"); @@ -20197,22 +20198,22 @@ void gen_intermediate_code(CPUState *cs, struct T= ranslationBlock *tb) { CPUMIPSState *env =3D cs->env_ptr; DisasContext ctx; - target_ulong pc_start; target_ulong next_page_start; - int num_insns; int max_insns; int insn_bytes; int is_slot; =20 - pc_start =3D tb->pc; - next_page_start =3D (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; - ctx.pc =3D pc_start; + ctx.base.tb =3D tb; + ctx.base.pc_first =3D tb->pc; + ctx.base.pc_next =3D tb->pc; + ctx.base.is_jmp =3D DISAS_NEXT; + ctx.base.singlestep_enabled =3D cs->singlestep_enabled; + ctx.base.num_insns =3D 0; + + next_page_start =3D (ctx.base.pc_first & TARGET_PAGE_MASK) + TARGET_PA= GE_SIZE; ctx.saved_pc =3D -1; - ctx.singlestep_enabled =3D cs->singlestep_enabled; ctx.insn_flags =3D env->insn_flags; ctx.CP0_Config1 =3D env->CP0_Config1; - ctx.tb =3D tb; - ctx.is_jmp =3D DISAS_NEXT; ctx.btarget =3D 0; ctx.kscrexist =3D (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff; ctx.rxi =3D (env->CP0_Config3 >> CP0C3_RXI) & 1; @@ -20226,7 +20227,7 @@ void gen_intermediate_code(CPUState *cs, struct Tra= nslationBlock *tb) ctx.CP0_LLAddr_shift =3D env->CP0_LLAddr_shift; ctx.cmgcr =3D (env->CP0_Config3 >> CP0C3_CMGCR) & 1; /* Restore delay slot state from the tb context. */ - ctx.hflags =3D (uint32_t)tb->flags; /* FIXME: maybe use 64 bits here? = */ + ctx.hflags =3D (uint32_t)ctx.base.tb->flags; /* FIXME: maybe use 64 bi= ts? */ ctx.ulri =3D (env->CP0_Config3 >> CP0C3_ULRI) & 1; ctx.ps =3D ((env->active_fpu.fcr0 >> FCR0_PS) & 1) || (env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)); @@ -20242,7 +20243,6 @@ void gen_intermediate_code(CPUState *cs, struct Tra= nslationBlock *tb) #endif ctx.default_tcg_memop_mask =3D (ctx.insn_flags & ISA_MIPS32R6) ? MO_UNALN : MO_ALIGN; - num_insns =3D 0; max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; @@ -20253,36 +20253,37 @@ void gen_intermediate_code(CPUState *cs, struct T= ranslationBlock *tb) =20 LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx.mem_idx, ctx.hflags); gen_tb_start(tb); - while (ctx.is_jmp =3D=3D DISAS_NEXT) { - tcg_gen_insn_start(ctx.pc, ctx.hflags & MIPS_HFLAG_BMASK, ctx.btar= get); - num_insns++; + while (ctx.base.is_jmp =3D=3D DISAS_NEXT) { + tcg_gen_insn_start(ctx.base.pc_next, ctx.hflags & MIPS_HFLAG_BMASK, + ctx.btarget); + ctx.base.num_insns++; =20 - if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) { + if (unlikely(cpu_breakpoint_test(cs, ctx.base.pc_next, BP_ANY))) { save_cpu_state(&ctx, 1); - ctx.is_jmp =3D DISAS_NORETURN; + ctx.base.is_jmp =3D DISAS_NORETURN; gen_helper_raise_exception_debug(cpu_env); /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that the logic setting tb->size below does the right thing. */ - ctx.pc +=3D 4; + ctx.base.pc_next +=3D 4; goto done_generating; } =20 - if (num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAST_IO)) { + if (ctx.base.num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAS= T_IO)) { gen_io_start(); } =20 is_slot =3D ctx.hflags & MIPS_HFLAG_BMASK; if (!(ctx.hflags & MIPS_HFLAG_M16)) { - ctx.opcode =3D cpu_ldl_code(env, ctx.pc); + ctx.opcode =3D cpu_ldl_code(env, ctx.base.pc_next); insn_bytes =3D 4; decode_opc(env, &ctx); } else if (ctx.insn_flags & ASE_MICROMIPS) { - ctx.opcode =3D cpu_lduw_code(env, ctx.pc); + ctx.opcode =3D cpu_lduw_code(env, ctx.base.pc_next); insn_bytes =3D decode_micromips_opc(env, &ctx); } else if (ctx.insn_flags & ASE_MIPS16) { - ctx.opcode =3D cpu_lduw_code(env, ctx.pc); + ctx.opcode =3D cpu_lduw_code(env, ctx.base.pc_next); insn_bytes =3D decode_mips16_opc(env, &ctx); } else { generate_exception_end(&ctx, EXCP_RI); @@ -20306,17 +20307,18 @@ void gen_intermediate_code(CPUState *cs, struct T= ranslationBlock *tb) if (is_slot) { gen_branch(&ctx, insn_bytes); } - ctx.pc +=3D insn_bytes; + ctx.base.pc_next +=3D insn_bytes; =20 /* Execute a branch and its delay slot as a single instruction. This is what GDB expects and is consistent with what the hardware does (e.g. if a delay slot instruction faults, the reported PC is the PC of the branch). */ - if (cs->singlestep_enabled && (ctx.hflags & MIPS_HFLAG_BMASK) =3D= =3D 0) { + if (ctx.base.singlestep_enabled && + (ctx.hflags & MIPS_HFLAG_BMASK) =3D=3D 0) { break; } =20 - if (ctx.pc >=3D next_page_start) { + if (ctx.base.pc_next >=3D next_page_start) { break; } =20 @@ -20324,8 +20326,9 @@ void gen_intermediate_code(CPUState *cs, struct Tra= nslationBlock *tb) break; } =20 - if (num_insns >=3D max_insns) + if (ctx.base.num_insns >=3D max_insns) { break; + } =20 if (singlestep) break; @@ -20333,17 +20336,17 @@ void gen_intermediate_code(CPUState *cs, struct T= ranslationBlock *tb) if (tb_cflags(tb) & CF_LAST_IO) { gen_io_end(); } - if (cs->singlestep_enabled && ctx.is_jmp !=3D DISAS_NORETURN) { - save_cpu_state(&ctx, ctx.is_jmp !=3D DISAS_EXCP); + if (ctx.base.singlestep_enabled && ctx.base.is_jmp !=3D DISAS_NORETURN= ) { + save_cpu_state(&ctx, ctx.base.is_jmp !=3D DISAS_EXCP); gen_helper_raise_exception_debug(cpu_env); } else { - switch (ctx.is_jmp) { + switch (ctx.base.is_jmp) { case DISAS_STOP: - gen_goto_tb(&ctx, 0, ctx.pc); + gen_goto_tb(&ctx, 0, ctx.base.pc_next); break; case DISAS_NEXT: save_cpu_state(&ctx, 0); - gen_goto_tb(&ctx, 0, ctx.pc); + gen_goto_tb(&ctx, 0, ctx.base.pc_next); break; case DISAS_EXCP: tcg_gen_exit_tb(0); @@ -20354,18 +20357,19 @@ void gen_intermediate_code(CPUState *cs, struct T= ranslationBlock *tb) } } done_generating: - gen_tb_end(tb, num_insns); + gen_tb_end(tb, ctx.base.num_insns); =20 - tb->size =3D ctx.pc - pc_start; - tb->icount =3D num_insns; + tb->size =3D ctx.base.pc_next - ctx.base.pc_first; + tb->icount =3D ctx.base.num_insns; =20 #ifdef DEBUG_DISAS LOG_DISAS("\n"); if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(pc_start)) { + && qemu_log_in_addr_range(ctx.base.pc_first)) { qemu_log_lock(); - qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, ctx.pc - pc_start); + qemu_log("IN: %s\n", lookup_symbol(ctx.base.pc_first)); + log_target_disas(cs, ctx.base.pc_first, + ctx.base.pc_next - ctx.base.pc_first); qemu_log("\n"); qemu_log_unlock(); } --=20 2.7.4 From nobody Fri Oct 24 09:56:51 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1518746869676538.3057153654551; Thu, 15 Feb 2018 18:07:49 -0800 (PST) Received: from localhost ([::1]:55234 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1emVR9-0000mv-HM for importer@patchew.org; Thu, 15 Feb 2018 21:07:43 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56225) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1emVMi-0004nK-Vx for qemu-devel@nongnu.org; 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Cota" To: qemu-devel@nongnu.org Date: Thu, 15 Feb 2018 21:02:51 -0500 Message-Id: <1518746572-14747-4-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1518746572-14747-1-git-send-email-cota@braap.org> References: <1518746572-14747-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.29 Subject: [Qemu-devel] [PATCH 3/4] target/mips: use *ctx for DisasContext X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yongbok Kim , Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" No changes to the logic here; this is just to make the diff that follows easier to read. While at it, remove the unnecessary 'struct' in 'struct TranslationBlock'. Note that checkpatch complains with a false positive: ERROR: space prohibited after that '&' (ctx:WxW) #75: FILE: target/mips/translate.c:20220: + ctx->kscrexist =3D (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff; ^ Signed-off-by: Emilio G. Cota --- target/mips/translate.c | 166 ++++++++++++++++++++++++--------------------= ---- 1 file changed, 84 insertions(+), 82 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index aefd729..08bd140 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -20194,55 +20194,57 @@ static void decode_opc(CPUMIPSState *env, DisasCo= ntext *ctx) } } =20 -void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { CPUMIPSState *env =3D cs->env_ptr; - DisasContext ctx; + DisasContext ctx1; + DisasContext *ctx =3D &ctx1; target_ulong next_page_start; int max_insns; int insn_bytes; int is_slot; =20 - ctx.base.tb =3D tb; - ctx.base.pc_first =3D tb->pc; - ctx.base.pc_next =3D tb->pc; - ctx.base.is_jmp =3D DISAS_NEXT; - ctx.base.singlestep_enabled =3D cs->singlestep_enabled; - ctx.base.num_insns =3D 0; - - next_page_start =3D (ctx.base.pc_first & TARGET_PAGE_MASK) + TARGET_PA= GE_SIZE; - ctx.saved_pc =3D -1; - ctx.insn_flags =3D env->insn_flags; - ctx.CP0_Config1 =3D env->CP0_Config1; - ctx.btarget =3D 0; - ctx.kscrexist =3D (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff; - ctx.rxi =3D (env->CP0_Config3 >> CP0C3_RXI) & 1; - ctx.ie =3D (env->CP0_Config4 >> CP0C4_IE) & 3; - ctx.bi =3D (env->CP0_Config3 >> CP0C3_BI) & 1; - ctx.bp =3D (env->CP0_Config3 >> CP0C3_BP) & 1; - ctx.PAMask =3D env->PAMask; - ctx.mvh =3D (env->CP0_Config5 >> CP0C5_MVH) & 1; - ctx.eva =3D (env->CP0_Config5 >> CP0C5_EVA) & 1; - ctx.sc =3D (env->CP0_Config3 >> CP0C3_SC) & 1; - ctx.CP0_LLAddr_shift =3D env->CP0_LLAddr_shift; - ctx.cmgcr =3D (env->CP0_Config3 >> CP0C3_CMGCR) & 1; + ctx->base.tb =3D tb; + ctx->base.pc_first =3D tb->pc; + ctx->base.pc_next =3D tb->pc; + ctx->base.is_jmp =3D DISAS_NEXT; + ctx->base.singlestep_enabled =3D cs->singlestep_enabled; + ctx->base.num_insns =3D 0; + + next_page_start =3D (ctx->base.pc_first & TARGET_PAGE_MASK) + + TARGET_PAGE_SIZE; + ctx->saved_pc =3D -1; + ctx->insn_flags =3D env->insn_flags; + ctx->CP0_Config1 =3D env->CP0_Config1; + ctx->btarget =3D 0; + ctx->kscrexist =3D (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff; + ctx->rxi =3D (env->CP0_Config3 >> CP0C3_RXI) & 1; + ctx->ie =3D (env->CP0_Config4 >> CP0C4_IE) & 3; + ctx->bi =3D (env->CP0_Config3 >> CP0C3_BI) & 1; + ctx->bp =3D (env->CP0_Config3 >> CP0C3_BP) & 1; + ctx->PAMask =3D env->PAMask; + ctx->mvh =3D (env->CP0_Config5 >> CP0C5_MVH) & 1; + ctx->eva =3D (env->CP0_Config5 >> CP0C5_EVA) & 1; + ctx->sc =3D (env->CP0_Config3 >> CP0C3_SC) & 1; + ctx->CP0_LLAddr_shift =3D env->CP0_LLAddr_shift; + ctx->cmgcr =3D (env->CP0_Config3 >> CP0C3_CMGCR) & 1; /* Restore delay slot state from the tb context. */ - ctx.hflags =3D (uint32_t)ctx.base.tb->flags; /* FIXME: maybe use 64 bi= ts? */ - ctx.ulri =3D (env->CP0_Config3 >> CP0C3_ULRI) & 1; - ctx.ps =3D ((env->active_fpu.fcr0 >> FCR0_PS) & 1) || + ctx->hflags =3D (uint32_t)ctx->base.tb->flags; /* FIXME: maybe use 64 = bits? */ + ctx->ulri =3D (env->CP0_Config3 >> CP0C3_ULRI) & 1; + ctx->ps =3D ((env->active_fpu.fcr0 >> FCR0_PS) & 1) || (env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)); - ctx.vp =3D (env->CP0_Config5 >> CP0C5_VP) & 1; - ctx.mrp =3D (env->CP0_Config5 >> CP0C5_MRP) & 1; - ctx.nan2008 =3D (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1; - ctx.abs2008 =3D (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1; - restore_cpu_state(env, &ctx); + ctx->vp =3D (env->CP0_Config5 >> CP0C5_VP) & 1; + ctx->mrp =3D (env->CP0_Config5 >> CP0C5_MRP) & 1; + ctx->nan2008 =3D (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1; + ctx->abs2008 =3D (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1; + restore_cpu_state(env, ctx); #ifdef CONFIG_USER_ONLY - ctx.mem_idx =3D MIPS_HFLAG_UM; + ctx->mem_idx =3D MIPS_HFLAG_UM; #else - ctx.mem_idx =3D hflags_mmu_index(ctx.hflags); + ctx->mem_idx =3D hflags_mmu_index(ctx->hflags); #endif - ctx.default_tcg_memop_mask =3D (ctx.insn_flags & ISA_MIPS32R6) ? - MO_UNALN : MO_ALIGN; + ctx->default_tcg_memop_mask =3D (ctx->insn_flags & ISA_MIPS32R6) ? + MO_UNALN : MO_ALIGN; max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; @@ -20251,74 +20253,74 @@ void gen_intermediate_code(CPUState *cs, struct T= ranslationBlock *tb) max_insns =3D TCG_MAX_INSNS; } =20 - LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx.mem_idx, ctx.hflags); + LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx->mem_idx, ctx->hflag= s); gen_tb_start(tb); - while (ctx.base.is_jmp =3D=3D DISAS_NEXT) { - tcg_gen_insn_start(ctx.base.pc_next, ctx.hflags & MIPS_HFLAG_BMASK, - ctx.btarget); - ctx.base.num_insns++; - - if (unlikely(cpu_breakpoint_test(cs, ctx.base.pc_next, BP_ANY))) { - save_cpu_state(&ctx, 1); - ctx.base.is_jmp =3D DISAS_NORETURN; + while (ctx->base.is_jmp =3D=3D DISAS_NEXT) { + tcg_gen_insn_start(ctx->base.pc_next, ctx->hflags & MIPS_HFLAG_BMA= SK, + ctx->btarget); + ctx->base.num_insns++; + + if (unlikely(cpu_breakpoint_test(cs, ctx->base.pc_next, BP_ANY))) { + save_cpu_state(ctx, 1); + ctx->base.is_jmp =3D DISAS_NORETURN; gen_helper_raise_exception_debug(cpu_env); /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that the logic setting tb->size below does the right thing. */ - ctx.base.pc_next +=3D 4; + ctx->base.pc_next +=3D 4; goto done_generating; } =20 - if (ctx.base.num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAS= T_IO)) { + if (ctx->base.num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LA= ST_IO)) { gen_io_start(); } =20 - is_slot =3D ctx.hflags & MIPS_HFLAG_BMASK; - if (!(ctx.hflags & MIPS_HFLAG_M16)) { - ctx.opcode =3D cpu_ldl_code(env, ctx.base.pc_next); + is_slot =3D ctx->hflags & MIPS_HFLAG_BMASK; + if (!(ctx->hflags & MIPS_HFLAG_M16)) { + ctx->opcode =3D cpu_ldl_code(env, ctx->base.pc_next); insn_bytes =3D 4; - decode_opc(env, &ctx); - } else if (ctx.insn_flags & ASE_MICROMIPS) { - ctx.opcode =3D cpu_lduw_code(env, ctx.base.pc_next); - insn_bytes =3D decode_micromips_opc(env, &ctx); - } else if (ctx.insn_flags & ASE_MIPS16) { - ctx.opcode =3D cpu_lduw_code(env, ctx.base.pc_next); - insn_bytes =3D decode_mips16_opc(env, &ctx); + decode_opc(env, ctx); + } else if (ctx->insn_flags & ASE_MICROMIPS) { + ctx->opcode =3D cpu_lduw_code(env, ctx->base.pc_next); + insn_bytes =3D decode_micromips_opc(env, ctx); + } else if (ctx->insn_flags & ASE_MIPS16) { + ctx->opcode =3D cpu_lduw_code(env, ctx->base.pc_next); + insn_bytes =3D decode_mips16_opc(env, ctx); } else { - generate_exception_end(&ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } =20 - if (ctx.hflags & MIPS_HFLAG_BMASK) { - if (!(ctx.hflags & (MIPS_HFLAG_BDS16 | MIPS_HFLAG_BDS32 | + if (ctx->hflags & MIPS_HFLAG_BMASK) { + if (!(ctx->hflags & (MIPS_HFLAG_BDS16 | MIPS_HFLAG_BDS32 | MIPS_HFLAG_FBNSLOT))) { /* force to generate branch as there is neither delay nor forbidden slot */ is_slot =3D 1; } - if ((ctx.hflags & MIPS_HFLAG_M16) && - (ctx.hflags & MIPS_HFLAG_FBNSLOT)) { + if ((ctx->hflags & MIPS_HFLAG_M16) && + (ctx->hflags & MIPS_HFLAG_FBNSLOT)) { /* Force to generate branch as microMIPS R6 doesn't restri= ct branches in the forbidden slot. */ is_slot =3D 1; } } if (is_slot) { - gen_branch(&ctx, insn_bytes); + gen_branch(ctx, insn_bytes); } - ctx.base.pc_next +=3D insn_bytes; + ctx->base.pc_next +=3D insn_bytes; =20 /* Execute a branch and its delay slot as a single instruction. This is what GDB expects and is consistent with what the hardware does (e.g. if a delay slot instruction faults, the reported PC is the PC of the branch). */ - if (ctx.base.singlestep_enabled && - (ctx.hflags & MIPS_HFLAG_BMASK) =3D=3D 0) { + if (ctx->base.singlestep_enabled && + (ctx->hflags & MIPS_HFLAG_BMASK) =3D=3D 0) { break; } =20 - if (ctx.base.pc_next >=3D next_page_start) { + if (ctx->base.pc_next >=3D next_page_start) { break; } =20 @@ -20326,7 +20328,7 @@ void gen_intermediate_code(CPUState *cs, struct Tra= nslationBlock *tb) break; } =20 - if (ctx.base.num_insns >=3D max_insns) { + if (ctx->base.num_insns >=3D max_insns) { break; } =20 @@ -20336,17 +20338,17 @@ void gen_intermediate_code(CPUState *cs, struct T= ranslationBlock *tb) if (tb_cflags(tb) & CF_LAST_IO) { gen_io_end(); } - if (ctx.base.singlestep_enabled && ctx.base.is_jmp !=3D DISAS_NORETURN= ) { - save_cpu_state(&ctx, ctx.base.is_jmp !=3D DISAS_EXCP); + if (ctx->base.singlestep_enabled && ctx->base.is_jmp !=3D DISAS_NORETU= RN) { + save_cpu_state(ctx, ctx->base.is_jmp !=3D DISAS_EXCP); gen_helper_raise_exception_debug(cpu_env); } else { - switch (ctx.base.is_jmp) { + switch (ctx->base.is_jmp) { case DISAS_STOP: - gen_goto_tb(&ctx, 0, ctx.base.pc_next); + gen_goto_tb(ctx, 0, ctx->base.pc_next); break; case DISAS_NEXT: - save_cpu_state(&ctx, 0); - gen_goto_tb(&ctx, 0, ctx.base.pc_next); + save_cpu_state(ctx, 0); + gen_goto_tb(ctx, 0, ctx->base.pc_next); break; case DISAS_EXCP: tcg_gen_exit_tb(0); @@ -20357,19 +20359,19 @@ void gen_intermediate_code(CPUState *cs, struct T= ranslationBlock *tb) } } done_generating: - gen_tb_end(tb, ctx.base.num_insns); + gen_tb_end(tb, ctx->base.num_insns); =20 - tb->size =3D ctx.base.pc_next - ctx.base.pc_first; - tb->icount =3D ctx.base.num_insns; + tb->size =3D ctx->base.pc_next - ctx->base.pc_first; + tb->icount =3D ctx->base.num_insns; =20 #ifdef DEBUG_DISAS LOG_DISAS("\n"); if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(ctx.base.pc_first)) { + && qemu_log_in_addr_range(ctx->base.pc_first)) { qemu_log_lock(); - qemu_log("IN: %s\n", lookup_symbol(ctx.base.pc_first)); - log_target_disas(cs, ctx.base.pc_first, - ctx.base.pc_next - ctx.base.pc_first); + qemu_log("IN: %s\n", lookup_symbol(ctx->base.pc_first)); + log_target_disas(cs, ctx->base.pc_first, + ctx->base.pc_next - ctx->base.pc_first); qemu_log("\n"); qemu_log_unlock(); } --=20 2.7.4 From nobody Fri Oct 24 09:56:51 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15187467264831004.7502065537582; Thu, 15 Feb 2018 18:05:26 -0800 (PST) Received: from localhost ([::1]:55047 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1emVOv-0006Ob-GA for importer@patchew.org; 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Cota" To: qemu-devel@nongnu.org Date: Thu, 15 Feb 2018 21:02:52 -0500 Message-Id: <1518746572-14747-5-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1518746572-14747-1-git-send-email-cota@braap.org> References: <1518746572-14747-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.29 Subject: [Qemu-devel] [PATCH 4/4] target/mips: convert to TranslatorOps X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yongbok Kim , Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Notes: - DISAS_TOO_MANY replaces the former "break" in the translation loop. However, care must be taken not to overwrite a previous condition in is_jmp; that's why in translate_insn we first check is_jmp and return if it's !=3D DISAS_NEXT. - Added an assert in translate_insn, before exiting due to an exception, to make sure that is_jmp is set to DISAS_EXCP (the exception generation function always sets it.) - Added an assert for the default case in is_jmp's switch. Signed-off-by: Emilio G. Cota --- target/mips/translate.c | 229 ++++++++++++++++++++++++--------------------= ---- 1 file changed, 115 insertions(+), 114 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 08bd140..22eee49 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1432,6 +1432,7 @@ static TCGv_i64 msa_wr_d[64]; typedef struct DisasContext { DisasContextBase base; target_ulong saved_pc; + target_ulong next_page_start; uint32_t opcode; int insn_flags; int32_t CP0_Config1; @@ -20194,24 +20195,13 @@ static void decode_opc(CPUMIPSState *env, DisasCo= ntext *ctx) } } =20 -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +static int mips_tr_init_disas_context(DisasContextBase *dcbase, + CPUState *cs, int max_insns) { + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); CPUMIPSState *env =3D cs->env_ptr; - DisasContext ctx1; - DisasContext *ctx =3D &ctx1; - target_ulong next_page_start; - int max_insns; - int insn_bytes; - int is_slot; - - ctx->base.tb =3D tb; - ctx->base.pc_first =3D tb->pc; - ctx->base.pc_next =3D tb->pc; - ctx->base.is_jmp =3D DISAS_NEXT; - ctx->base.singlestep_enabled =3D cs->singlestep_enabled; - ctx->base.num_insns =3D 0; =20 - next_page_start =3D (ctx->base.pc_first & TARGET_PAGE_MASK) + + ctx->next_page_start =3D (ctx->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; ctx->saved_pc =3D -1; ctx->insn_flags =3D env->insn_flags; @@ -20245,99 +20235,103 @@ void gen_intermediate_code(CPUState *cs, Transla= tionBlock *tb) #endif ctx->default_tcg_memop_mask =3D (ctx->insn_flags & ISA_MIPS32R6) ? MO_UNALN : MO_ALIGN; - max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } =20 - LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx->mem_idx, ctx->hflag= s); - gen_tb_start(tb); - while (ctx->base.is_jmp =3D=3D DISAS_NEXT) { - tcg_gen_insn_start(ctx->base.pc_next, ctx->hflags & MIPS_HFLAG_BMA= SK, - ctx->btarget); - ctx->base.num_insns++; + LOG_DISAS("\ntb %p idx %d hflags %04x\n", ctx->base.tb, ctx->mem_idx, + ctx->hflags); + return max_insns; +} =20 - if (unlikely(cpu_breakpoint_test(cs, ctx->base.pc_next, BP_ANY))) { - save_cpu_state(ctx, 1); - ctx->base.is_jmp =3D DISAS_NORETURN; - gen_helper_raise_exception_debug(cpu_env); - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - ctx->base.pc_next +=3D 4; - goto done_generating; - } +static void mips_tr_tb_start(DisasContextBase *dcbase, CPUState *cs) +{ +} =20 - if (ctx->base.num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LA= ST_IO)) { - gen_io_start(); - } +static void mips_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - is_slot =3D ctx->hflags & MIPS_HFLAG_BMASK; - if (!(ctx->hflags & MIPS_HFLAG_M16)) { - ctx->opcode =3D cpu_ldl_code(env, ctx->base.pc_next); - insn_bytes =3D 4; - decode_opc(env, ctx); - } else if (ctx->insn_flags & ASE_MICROMIPS) { - ctx->opcode =3D cpu_lduw_code(env, ctx->base.pc_next); - insn_bytes =3D decode_micromips_opc(env, ctx); - } else if (ctx->insn_flags & ASE_MIPS16) { - ctx->opcode =3D cpu_lduw_code(env, ctx->base.pc_next); - insn_bytes =3D decode_mips16_opc(env, ctx); - } else { - generate_exception_end(ctx, EXCP_RI); - break; - } + tcg_gen_insn_start(ctx->base.pc_next, ctx->hflags & MIPS_HFLAG_BMASK, + ctx->btarget); +} =20 - if (ctx->hflags & MIPS_HFLAG_BMASK) { - if (!(ctx->hflags & (MIPS_HFLAG_BDS16 | MIPS_HFLAG_BDS32 | - MIPS_HFLAG_FBNSLOT))) { - /* force to generate branch as there is neither delay nor - forbidden slot */ - is_slot =3D 1; - } - if ((ctx->hflags & MIPS_HFLAG_M16) && - (ctx->hflags & MIPS_HFLAG_FBNSLOT)) { - /* Force to generate branch as microMIPS R6 doesn't restri= ct - branches in the forbidden slot. */ - is_slot =3D 1; - } - } - if (is_slot) { - gen_branch(ctx, insn_bytes); - } - ctx->base.pc_next +=3D insn_bytes; +static bool mips_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *c= s, + const CPUBreakpoint *bp) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - /* Execute a branch and its delay slot as a single instruction. - This is what GDB expects and is consistent with what the - hardware does (e.g. if a delay slot instruction faults, the - reported PC is the PC of the branch). */ - if (ctx->base.singlestep_enabled && - (ctx->hflags & MIPS_HFLAG_BMASK) =3D=3D 0) { - break; - } + save_cpu_state(ctx, 1); + ctx->base.is_jmp =3D DISAS_NORETURN; + gen_helper_raise_exception_debug(cpu_env); + /* The address covered by the breakpoint must be included in + [tb->pc, tb->pc + tb->size) in order to for it to be + properly cleared -- thus we increment the PC here so that + the logic setting tb->size below does the right thing. */ + ctx->base.pc_next +=3D 4; + return true; +} =20 - if (ctx->base.pc_next >=3D next_page_start) { - break; - } +static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) +{ + CPUMIPSState *env =3D cs->env_ptr; + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); + int insn_bytes; + int is_slot; =20 - if (tcg_op_buf_full()) { - break; - } + is_slot =3D ctx->hflags & MIPS_HFLAG_BMASK; + if (!(ctx->hflags & MIPS_HFLAG_M16)) { + ctx->opcode =3D cpu_ldl_code(env, ctx->base.pc_next); + insn_bytes =3D 4; + decode_opc(env, ctx); + } else if (ctx->insn_flags & ASE_MICROMIPS) { + ctx->opcode =3D cpu_lduw_code(env, ctx->base.pc_next); + insn_bytes =3D decode_micromips_opc(env, ctx); + } else if (ctx->insn_flags & ASE_MIPS16) { + ctx->opcode =3D cpu_lduw_code(env, ctx->base.pc_next); + insn_bytes =3D decode_mips16_opc(env, ctx); + } else { + generate_exception_end(ctx, EXCP_RI); + g_assert(ctx->base.is_jmp =3D=3D DISAS_EXCP); + return; + } =20 - if (ctx->base.num_insns >=3D max_insns) { - break; + if (ctx->hflags & MIPS_HFLAG_BMASK) { + if (!(ctx->hflags & (MIPS_HFLAG_BDS16 | MIPS_HFLAG_BDS32 | + MIPS_HFLAG_FBNSLOT))) { + /* force to generate branch as there is neither delay nor + forbidden slot */ + is_slot =3D 1; + } + if ((ctx->hflags & MIPS_HFLAG_M16) && + (ctx->hflags & MIPS_HFLAG_FBNSLOT)) { + /* Force to generate branch as microMIPS R6 doesn't restrict + branches in the forbidden slot. */ + is_slot =3D 1; } + } + if (is_slot) { + gen_branch(ctx, insn_bytes); + } + ctx->base.pc_next +=3D insn_bytes; =20 - if (singlestep) - break; + if (ctx->base.is_jmp !=3D DISAS_NEXT) { + return; } - if (tb_cflags(tb) & CF_LAST_IO) { - gen_io_end(); + /* Execute a branch and its delay slot as a single instruction. + This is what GDB expects and is consistent with what the + hardware does (e.g. if a delay slot instruction faults, the + reported PC is the PC of the branch). */ + if (ctx->base.singlestep_enabled && + (ctx->hflags & MIPS_HFLAG_BMASK) =3D=3D 0) { + ctx->base.is_jmp =3D DISAS_TOO_MANY; + } + if (ctx->base.pc_next >=3D ctx->next_page_start) { + ctx->base.is_jmp =3D DISAS_TOO_MANY; } +} + +static void mips_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); + if (ctx->base.singlestep_enabled && ctx->base.is_jmp !=3D DISAS_NORETU= RN) { save_cpu_state(ctx, ctx->base.is_jmp !=3D DISAS_EXCP); gen_helper_raise_exception_debug(cpu_env); @@ -20347,6 +20341,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) gen_goto_tb(ctx, 0, ctx->base.pc_next); break; case DISAS_NEXT: + case DISAS_TOO_MANY: save_cpu_state(ctx, 0); gen_goto_tb(ctx, 0, ctx->base.pc_next); break; @@ -20354,28 +20349,34 @@ void gen_intermediate_code(CPUState *cs, Translat= ionBlock *tb) tcg_gen_exit_tb(0); break; case DISAS_NORETURN: - default: break; + default: + g_assert_not_reached(); } } -done_generating: - gen_tb_end(tb, ctx->base.num_insns); - - tb->size =3D ctx->base.pc_next - ctx->base.pc_first; - tb->icount =3D ctx->base.num_insns; - -#ifdef DEBUG_DISAS - LOG_DISAS("\n"); - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(ctx->base.pc_first)) { - qemu_log_lock(); - qemu_log("IN: %s\n", lookup_symbol(ctx->base.pc_first)); - log_target_disas(cs, ctx->base.pc_first, - ctx->base.pc_next - ctx->base.pc_first); - qemu_log("\n"); - qemu_log_unlock(); - } -#endif +} + +static void mips_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) +{ + qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); + log_target_disas(cs, dcbase->pc_first, dcbase->tb->size); +} + +static const TranslatorOps mips_tr_ops =3D { + .init_disas_context =3D mips_tr_init_disas_context, + .tb_start =3D mips_tr_tb_start, + .insn_start =3D mips_tr_insn_start, + .breakpoint_check =3D mips_tr_breakpoint_check, + .translate_insn =3D mips_tr_translate_insn, + .tb_stop =3D mips_tr_tb_stop, + .disas_log =3D mips_tr_disas_log, +}; + +void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) +{ + DisasContext ctx; + + translator_loop(&mips_tr_ops, &ctx.base, cs, tb); } =20 static void fpu_dump_state(CPUMIPSState *env, FILE *f, fprintf_function fp= u_fprintf, --=20 2.7.4