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Cota" To: qemu-devel@nongnu.org Date: Thu, 15 Feb 2018 18:17:56 -0500 Message-Id: <1518736676-5994-4-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1518736676-5994-1-git-send-email-cota@braap.org> References: <1518736676-5994-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.29 Subject: [Qemu-devel] [PATCH 3/3] target/sparc: convert to TranslatorOps X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland , Artyom Tarasenko , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Notes: - Moved the cross-page check from the end of translate_insn to init_disas_context. Signed-off-by: Emilio G. Cota --- target/sparc/translate.c | 181 +++++++++++++++++++++++--------------------= ---- 1 file changed, 88 insertions(+), 93 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index da77a27..5a25a51 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5732,105 +5732,94 @@ static void disas_sparc_insn(DisasContext * dc, un= signed int insn) } } =20 -void gen_intermediate_code(CPUState *cs, TranslationBlock * tb) +static int sparc_tr_init_disas_context(DisasContextBase *dcbase, + CPUState *cs, int max_insns) { + DisasContext *dc =3D container_of(dcbase, DisasContext, base); CPUSPARCState *env =3D cs->env_ptr; - DisasContext dc1, *dc =3D &dc1; - int max_insns; - unsigned int insn; - - memset(dc, 0, sizeof(DisasContext)); - dc->base.tb =3D tb; - dc->base.pc_first =3D tb->pc; - dc->base.pc_next =3D tb->pc; - dc->base.is_jmp =3D DISAS_NEXT; - dc->base.num_insns =3D 0; - dc->base.singlestep_enabled =3D cs->singlestep_enabled; + int bound; =20 dc->pc =3D dc->base.pc_first; - dc->npc =3D (target_ulong) tb->cs_base; + dc->npc =3D (target_ulong)dc->base.tb->cs_base; dc->cc_op =3D CC_OP_DYNAMIC; - dc->mem_idx =3D tb->flags & TB_FLAG_MMU_MASK; + dc->mem_idx =3D dc->base.tb->flags & TB_FLAG_MMU_MASK; dc->def =3D &env->def; - dc->fpu_enabled =3D tb_fpu_enabled(tb->flags); - dc->address_mask_32bit =3D tb_am_enabled(tb->flags); + dc->fpu_enabled =3D tb_fpu_enabled(dc->base.tb->flags); + dc->address_mask_32bit =3D tb_am_enabled(dc->base.tb->flags); =20 #ifndef CONFIG_USER_ONLY - dc->supervisor =3D (tb->flags & TB_FLAG_SUPER) !=3D 0; + dc->supervisor =3D (dc->base.tb->flags & TB_FLAG_SUPER) !=3D 0; #endif #ifdef TARGET_SPARC64 dc->fprs_dirty =3D 0; - dc->asi =3D (tb->flags >> TB_FLAG_ASI_SHIFT) & 0xff; + dc->asi =3D (dc->base.tb->flags >> TB_FLAG_ASI_SHIFT) & 0xff; #ifndef CONFIG_USER_ONLY - dc->hypervisor =3D (tb->flags & TB_FLAG_HYPER) !=3D 0; + dc->hypervisor =3D (dc->base.tb->flags & TB_FLAG_HYPER) !=3D 0; #endif #endif + /* + * if we reach a page boundary, we stop generation so that the + * PC of a TT_TFAULT exception is always in the right page + */ + bound =3D -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; + return MIN(max_insns, bound); +} =20 - max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } - if (singlestep) { - max_insns =3D 1; - } +static void sparc_tr_tb_start(DisasContextBase *db, CPUState *cs) +{ +} =20 - gen_tb_start(tb); - do { - if (dc->npc & JUMP_PC) { - assert(dc->jump_pc[1] =3D=3D dc->pc + 4); - tcg_gen_insn_start(dc->pc, dc->jump_pc[0] | JUMP_PC); - } else { - tcg_gen_insn_start(dc->pc, dc->npc); - } - dc->base.num_insns++; +static void sparc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); =20 - if (unlikely(cpu_breakpoint_test(cs, dc->base.pc_next, BP_ANY))) { - if (dc->pc !=3D dc->base.pc_first) { - save_state(dc); - } - gen_helper_debug(cpu_env); - tcg_gen_exit_tb(0); - dc->base.is_jmp =3D DISAS_NORETURN; - dc->base.pc_next +=3D 4; - goto exit_gen_loop; - } + if (dc->npc & JUMP_PC) { + assert(dc->jump_pc[1] =3D=3D dc->pc + 4); + tcg_gen_insn_start(dc->pc, dc->jump_pc[0] | JUMP_PC); + } else { + tcg_gen_insn_start(dc->pc, dc->npc); + } +} =20 - if (dc->base.num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAS= T_IO)) { - gen_io_start(); - } +static bool sparc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *= cs, + const CPUBreakpoint *bp) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); =20 - insn =3D cpu_ldl_code(env, dc->pc); - dc->base.pc_next +=3D 4; + if (dc->pc !=3D dc->base.pc_first) { + save_state(dc); + } + gen_helper_debug(cpu_env); + tcg_gen_exit_tb(0); + dc->base.is_jmp =3D DISAS_NORETURN; + /* update pc_next so that the current instruction is included in tb->s= ize */ + dc->base.pc_next +=3D 4; + return true; +} =20 - disas_sparc_insn(dc, insn); +static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + CPUSPARCState *env =3D cs->env_ptr; + unsigned int insn; =20 - if (dc->base.is_jmp =3D=3D DISAS_NORETURN) { - break; - } - /* if the next PC is different, we abort now */ - if (dc->pc !=3D dc->base.pc_next) { - break; - } - /* if we reach a page boundary, we stop generation so that the - PC of a TT_TFAULT exception is always in the right page */ - if ((dc->pc & (TARGET_PAGE_SIZE - 1)) =3D=3D 0) - break; - /* if single step mode, we generate only one instruction and - generate an exception */ - if (dc->base.singlestep_enabled) { - break; - } - } while (!tcg_op_buf_full() && - (dc->pc - dc->base.pc_first) < (TARGET_PAGE_SIZE - 32) && - dc->base.num_insns < max_insns); + insn =3D cpu_ldl_code(env, dc->pc); + dc->base.pc_next +=3D 4; + disas_sparc_insn(dc, insn); =20 - exit_gen_loop: - if (tb_cflags(tb) & CF_LAST_IO) { - gen_io_end(); + if (dc->base.is_jmp =3D=3D DISAS_NORETURN) { + return; + } + if (dc->pc !=3D dc->base.pc_next || + (dc->pc - dc->base.pc_first) >=3D (TARGET_PAGE_SIZE - 32)) { + dc->base.is_jmp =3D DISAS_TOO_MANY; } +} + +static void sparc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + if (dc->base.is_jmp !=3D DISAS_NORETURN) { if (dc->pc !=3D DYNAMIC_PC && (dc->npc !=3D DYNAMIC_PC && dc->npc !=3D JUMP_PC)) { @@ -5844,23 +5833,29 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock * tb) tcg_gen_exit_tb(0); } } - gen_tb_end(tb, dc->base.num_insns); - - tb->size =3D dc->base.pc_next - dc->base.pc_first; - tb->icount =3D dc->base.num_insns; - -#ifdef DEBUG_DISAS - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(dc->base.pc_first)) { - qemu_log_lock(); - qemu_log("--------------\n"); - qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); - log_target_disas(cs, dc->base.pc_first, - dc->base.pc_next - dc->base.pc_first); - qemu_log("\n"); - qemu_log_unlock(); - } -#endif +} + +static void sparc_tr_disas_log(const DisasContextBase *dcbase, CPUState *c= pu) +{ + qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); + log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); +} + +static const TranslatorOps sparc_tr_ops =3D { + .init_disas_context =3D sparc_tr_init_disas_context, + .tb_start =3D sparc_tr_tb_start, + .insn_start =3D sparc_tr_insn_start, + .breakpoint_check =3D sparc_tr_breakpoint_check, + .translate_insn =3D sparc_tr_translate_insn, + .tb_stop =3D sparc_tr_tb_stop, + .disas_log =3D sparc_tr_disas_log, +}; + +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +{ + DisasContext dc =3D {}; + + translator_loop(&sparc_tr_ops, &dc.base, cs, tb); } =20 void sparc_tcg_init(void) --=20 2.7.4