From nobody Fri Oct 24 09:56:46 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 151873746178351.11821454789492; Thu, 15 Feb 2018 15:31:01 -0800 (PST) Received: from localhost ([::1]:43324 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1emSzV-0000nR-0x for importer@patchew.org; Thu, 15 Feb 2018 18:31:01 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46771) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1emSn3-0003bT-5N for qemu-devel@nongnu.org; Thu, 15 Feb 2018 18:18:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1emSmz-0000kj-Gz for qemu-devel@nongnu.org; Thu, 15 Feb 2018 18:18:09 -0500 Received: from out5-smtp.messagingengine.com ([66.111.4.29]:58953) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1emSmz-0000kW-CX for qemu-devel@nongnu.org; Thu, 15 Feb 2018 18:18:05 -0500 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 12FFF20DE3; Thu, 15 Feb 2018 18:18:05 -0500 (EST) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Thu, 15 Feb 2018 18:18:05 -0500 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id B1AFE7E34D; Thu, 15 Feb 2018 18:18:04 -0500 (EST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc; s=mesmtp; bh=eypZB0NtPgV4Ov XLpoSPOpcUED/mjKX08TRawmsXkdk=; b=KGPrCeymy3dCeh0nxgMZnrIer8WVA8 xJeQJH42764n63LSDaTIH3VkHfpAqrPCOjGSR4BUSSOs0RC+5qPErF0iatCC9+az S84ZBKItKw7SX/w3gWGWGex6AIt38BsxtupJ4No27w2FBJq19M8x9Mg1rE7khIdw uFSOP+0pNIxZg= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc; s= fm2; bh=eypZB0NtPgV4OvXLpoSPOpcUED/mjKX08TRawmsXkdk=; b=EnONq7UH iEWHoFfiXLV4sJEbrLhxVAzdg6BFlMT/b4yuQmGI0BluKFqm0yuFBTFMH11CH7Kf wbg3HS1ql2n5Dm9e9gIFxfNhLI8MRXUfTMzg6807uhPFxhksNfWy/2UJPcUtjtsS xdUP6Bp1cKWvBGII6aBlMVgffCPg+/7ThwHQCUWaxgPwo12Ku6bFsw8DU1YeUNJH qAAt9rO4xWki6NG/0JcvLPdJRe5PSyVPeqhClxumwujVwsyevauw+YSqv/GngRo/ uguWDleofer2b6Q145i3fS0wpgNPr83HxTytN8PZzjQcCpJXdpE0Sl9t3nySGLLe cGn/DvOiUHvm9A== X-ME-Sender: From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Thu, 15 Feb 2018 18:17:54 -0500 Message-Id: <1518736676-5994-2-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1518736676-5994-1-git-send-email-cota@braap.org> References: <1518736676-5994-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.29 Subject: [Qemu-devel] [PATCH 1/3] target/sparc: convert to DisasJumpType X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland , Artyom Tarasenko , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Emilio G. Cota Reviewed-by: Richard Henderson --- target/sparc/translate.c | 27 +++++++++++++++------------ 1 file changed, 15 insertions(+), 12 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 71e0853..730e25d 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -30,6 +30,7 @@ #include "exec/helper-gen.h" =20 #include "trace-tcg.h" +#include "exec/translator.h" #include "exec/log.h" #include "asi.h" =20 @@ -69,7 +70,7 @@ typedef struct DisasContext { target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC = */ target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */ target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */ - int is_br; + DisasJumpType is_jmp; int mem_idx; bool fpu_enabled; bool address_mask_32bit; @@ -995,7 +996,7 @@ static void gen_branch_a(DisasContext *dc, target_ulong= pc1) gen_set_label(l1); gen_goto_tb(dc, 1, npc + 4, npc + 8); =20 - dc->is_br =3D 1; + dc->is_jmp =3D DISAS_NORETURN; } =20 static void gen_branch_n(DisasContext *dc, target_ulong pc1) @@ -1078,7 +1079,7 @@ static void gen_exception(DisasContext *dc, int which) t =3D tcg_const_i32(which); gen_helper_raise_exception(cpu_env, t); tcg_temp_free_i32(t); - dc->is_br =3D 1; + dc->is_jmp =3D DISAS_NORETURN; } =20 static void gen_check_align(TCGv addr, int mask) @@ -3346,7 +3347,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) =20 if (cond =3D=3D 8) { /* An unconditional trap ends the TB. */ - dc->is_br =3D 1; + dc->is_jmp =3D DISAS_NORETURN; goto jmp_insn; } else { /* A conditional trap falls through to the next insn. = */ @@ -4326,7 +4327,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) save_state(dc); gen_op_next_insn(); tcg_gen_exit_tb(0); - dc->is_br =3D 1; + dc->is_jmp =3D DISAS_NORETURN; break; case 0x6: /* V9 wrfprs */ tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src= 2); @@ -4335,7 +4336,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) save_state(dc); gen_op_next_insn(); tcg_gen_exit_tb(0); - dc->is_br =3D 1; + dc->is_jmp =3D DISAS_NORETURN; break; case 0xf: /* V9 sir, nop if user */ #if !defined(CONFIG_USER_ONLY) @@ -4463,7 +4464,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) save_state(dc); gen_op_next_insn(); tcg_gen_exit_tb(0); - dc->is_br =3D 1; + dc->is_jmp =3D DISAS_NORETURN; #endif } break; @@ -4619,7 +4620,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) save_state(dc); gen_op_next_insn(); tcg_gen_exit_tb(0); - dc->is_br =3D 1; + dc->is_jmp =3D DISAS_NORETURN; break; case 1: // htstate // XXX gen_op_wrhtstate(); @@ -5685,7 +5686,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) } else if (dc->npc =3D=3D JUMP_PC) { /* we can do a static jump */ gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond); - dc->is_br =3D 1; + dc->is_jmp =3D DISAS_NORETURN; } else { dc->pc =3D dc->npc; dc->npc =3D dc->npc + 4; @@ -5747,6 +5748,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock * tb) pc_start =3D tb->pc; dc->pc =3D pc_start; last_pc =3D dc->pc; + dc->is_jmp =3D DISAS_NEXT; dc->npc =3D (target_ulong) tb->cs_base; dc->cc_op =3D CC_OP_DYNAMIC; dc->mem_idx =3D tb->flags & TB_FLAG_MMU_MASK; @@ -5791,7 +5793,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock * tb) } gen_helper_debug(cpu_env); tcg_gen_exit_tb(0); - dc->is_br =3D 1; + dc->is_jmp =3D DISAS_NORETURN; goto exit_gen_loop; } =20 @@ -5803,8 +5805,9 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock * tb) =20 disas_sparc_insn(dc, insn); =20 - if (dc->is_br) + if (dc->is_jmp =3D=3D DISAS_NORETURN) { break; + } /* if the next PC is different, we abort now */ if (dc->pc !=3D (last_pc + 4)) break; @@ -5825,7 +5828,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock * tb) if (tb_cflags(tb) & CF_LAST_IO) { gen_io_end(); } - if (!dc->is_br) { + if (dc->is_jmp !=3D DISAS_NORETURN) { if (dc->pc !=3D DYNAMIC_PC && (dc->npc !=3D DYNAMIC_PC && dc->npc !=3D JUMP_PC)) { /* static PC and NPC: we can use direct chaining */ --=20 2.7.4 From nobody Fri Oct 24 09:56:46 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1518737008450474.685926541017; Thu, 15 Feb 2018 15:23:28 -0800 (PST) Received: from localhost ([::1]:42289 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1emSrw-0007Wl-OS for importer@patchew.org; Thu, 15 Feb 2018 18:23:12 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46772) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1emSn3-0003bU-5f for qemu-devel@nongnu.org; Thu, 15 Feb 2018 18:18:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1emSmz-0000kw-MW for qemu-devel@nongnu.org; Thu, 15 Feb 2018 18:18:09 -0500 Received: from out5-smtp.messagingengine.com ([66.111.4.29]:56475) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1emSmz-0000ka-Gy for qemu-devel@nongnu.org; Thu, 15 Feb 2018 18:18:05 -0500 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 40DA220C91; Thu, 15 Feb 2018 18:18:05 -0500 (EST) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Thu, 15 Feb 2018 18:18:05 -0500 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id E3FCB241E0; Thu, 15 Feb 2018 18:18:04 -0500 (EST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc; s=mesmtp; bh=xKGR9vAfOiFdK1 TaBV/i+kgHTkoOc5Od3PcS2T5YT2c=; b=1SK9jh2IOSuQDpZ/m6MAioUWSb4J1q oWPFR0hyxdxoL1634EL8joNS+qx7tVsRDAN9hjkzF3GkjzbqISqeiTPxKhc+Zb64 +4zdj6zVyVyexu5M0tqJutd+LEoRKdWV5aEePR4ZJkgwXDQWSXS9WnXTAhs1UCGN McG08AD+a5vOc= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc; s= fm2; bh=xKGR9vAfOiFdK1TaBV/i+kgHTkoOc5Od3PcS2T5YT2c=; b=Vmxm8WlR CyChydz6OMNMGH6B+MO8HPNTi4s4j3C5l+Z4F6hh5jgwKzJWCv3N7oR6MJsgiCH/ b9EIZ5ibI4epE2+J9s+tNPaB6lXZStHHbRwUm5zgqYlrIaI6NzofsrFTSbQcP7fO 8hitofzgQXvbEg4xRfOVvKilxHIMTsDUz/yOLpcO03ALij1ltLYv6NSW7GqaLcm0 si+7FVRkTNdGR6uzjw9wp/v1M6adALBdXSCzRkBqXa1K5Crc63J5zx4Y4IOCMH6y fYLtdAq6mx54B+AgcV7DdFX2sOwft8536kP4742l54amelTfHLucVI1o8RnLEAfy JYFqpHnv2g5FQA== X-ME-Sender: From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Thu, 15 Feb 2018 18:17:55 -0500 Message-Id: <1518736676-5994-3-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1518736676-5994-1-git-send-email-cota@braap.org> References: <1518736676-5994-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.29 Subject: [Qemu-devel] [PATCH 2/3] target/sparc: convert to DisasContextBase X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland , Artyom Tarasenko , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Notes: - pc and npc are left unmodified, since they can point to out-of-TB jump targets. - Got rid of last_pc in gen_intermediate_code(), using base.pc_next instead. Only update pc_next (1) on a breakpoint (so that tb->size includes the insn), and (2) after reading the current instruction from memory. This allows us to use base.pc_next in the BP check, which is what the translator loop does. - The original meaning of ctx.singlestep is cs->singlestep_enabled || singlestep , which required a little extra work since base.singlestep_enabled only gets its value from cs->singlestep_enabled. Signed-off-by: Emilio G. Cota --- target/sparc/translate.c | 90 +++++++++++++++++++++++++-------------------= ---- 1 file changed, 47 insertions(+), 43 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 730e25d..da77a27 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -67,14 +67,13 @@ static TCGv_i64 cpu_fpr[TARGET_DPREGS]; #include "exec/gen-icount.h" =20 typedef struct DisasContext { + DisasContextBase base; target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC = */ target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */ target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */ - DisasJumpType is_jmp; int mem_idx; bool fpu_enabled; bool address_mask_32bit; - bool singlestep; #ifndef CONFIG_USER_ONLY bool supervisor; #ifdef TARGET_SPARC64 @@ -83,7 +82,6 @@ typedef struct DisasContext { #endif =20 uint32_t cc_op; /* current CC operation */ - struct TranslationBlock *tb; sparc_def_t *def; TCGv_i32 t32[3]; TCGv ttl[5]; @@ -342,13 +340,13 @@ static inline TCGv gen_dest_gpr(DisasContext *dc, int= reg) static inline bool use_goto_tb(DisasContext *s, target_ulong pc, target_ulong npc) { - if (unlikely(s->singlestep)) { + if (unlikely(s->base.singlestep_enabled || singlestep)) { return false; } =20 #ifndef CONFIG_USER_ONLY - return (pc & TARGET_PAGE_MASK) =3D=3D (s->tb->pc & TARGET_PAGE_MASK) && - (npc & TARGET_PAGE_MASK) =3D=3D (s->tb->pc & TARGET_PAGE_MASK); + return (pc & TARGET_PAGE_MASK) =3D=3D (s->base.tb->pc & TARGET_PAGE_MA= SK) && + (npc & TARGET_PAGE_MASK) =3D=3D (s->base.tb->pc & TARGET_PAGE_M= ASK); #else return true; #endif @@ -362,7 +360,7 @@ static inline void gen_goto_tb(DisasContext *s, int tb_= num, tcg_gen_goto_tb(tb_num); tcg_gen_movi_tl(cpu_pc, pc); tcg_gen_movi_tl(cpu_npc, npc); - tcg_gen_exit_tb((uintptr_t)s->tb + tb_num); + tcg_gen_exit_tb((uintptr_t)s->base.tb + tb_num); } else { /* jump to another page: currently not optimized */ tcg_gen_movi_tl(cpu_pc, pc); @@ -996,7 +994,7 @@ static void gen_branch_a(DisasContext *dc, target_ulong= pc1) gen_set_label(l1); gen_goto_tb(dc, 1, npc + 4, npc + 8); =20 - dc->is_jmp =3D DISAS_NORETURN; + dc->base.is_jmp =3D DISAS_NORETURN; } =20 static void gen_branch_n(DisasContext *dc, target_ulong pc1) @@ -1079,7 +1077,7 @@ static void gen_exception(DisasContext *dc, int which) t =3D tcg_const_i32(which); gen_helper_raise_exception(cpu_env, t); tcg_temp_free_i32(t); - dc->is_jmp =3D DISAS_NORETURN; + dc->base.is_jmp =3D DISAS_NORETURN; } =20 static void gen_check_align(TCGv addr, int mask) @@ -2437,7 +2435,7 @@ static void gen_ldstub_asi(DisasContext *dc, TCGv dst= , TCGv addr, int insn) default: /* ??? In theory, this should be raise DAE_invalid_asi. But the SS-20 roms do ldstuba [%l0] #ASI_M_CTL, %o1. */ - if (tb_cflags(dc->tb) & CF_PARALLEL) { + if (tb_cflags(dc->base.tb) & CF_PARALLEL) { gen_helper_exit_atomic(cpu_env); } else { TCGv_i32 r_asi =3D tcg_const_i32(da.asi); @@ -3347,7 +3345,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) =20 if (cond =3D=3D 8) { /* An unconditional trap ends the TB. */ - dc->is_jmp =3D DISAS_NORETURN; + dc->base.is_jmp =3D DISAS_NORETURN; goto jmp_insn; } else { /* A conditional trap falls through to the next insn. = */ @@ -4327,7 +4325,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) save_state(dc); gen_op_next_insn(); tcg_gen_exit_tb(0); - dc->is_jmp =3D DISAS_NORETURN; + dc->base.is_jmp =3D DISAS_NORETURN; break; case 0x6: /* V9 wrfprs */ tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src= 2); @@ -4336,7 +4334,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) save_state(dc); gen_op_next_insn(); tcg_gen_exit_tb(0); - dc->is_jmp =3D DISAS_NORETURN; + dc->base.is_jmp =3D DISAS_NORETURN; break; case 0xf: /* V9 sir, nop if user */ #if !defined(CONFIG_USER_ONLY) @@ -4464,7 +4462,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) save_state(dc); gen_op_next_insn(); tcg_gen_exit_tb(0); - dc->is_jmp =3D DISAS_NORETURN; + dc->base.is_jmp =3D DISAS_NORETURN; #endif } break; @@ -4620,7 +4618,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) save_state(dc); gen_op_next_insn(); tcg_gen_exit_tb(0); - dc->is_jmp =3D DISAS_NORETURN; + dc->base.is_jmp =3D DISAS_NORETURN; break; case 1: // htstate // XXX gen_op_wrhtstate(); @@ -5686,7 +5684,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) } else if (dc->npc =3D=3D JUMP_PC) { /* we can do a static jump */ gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond); - dc->is_jmp =3D DISAS_NORETURN; + dc->base.is_jmp =3D DISAS_NORETURN; } else { dc->pc =3D dc->npc; dc->npc =3D dc->npc + 4; @@ -5737,25 +5735,26 @@ static void disas_sparc_insn(DisasContext * dc, uns= igned int insn) void gen_intermediate_code(CPUState *cs, TranslationBlock * tb) { CPUSPARCState *env =3D cs->env_ptr; - target_ulong pc_start, last_pc; DisasContext dc1, *dc =3D &dc1; - int num_insns; int max_insns; unsigned int insn; =20 memset(dc, 0, sizeof(DisasContext)); - dc->tb =3D tb; - pc_start =3D tb->pc; - dc->pc =3D pc_start; - last_pc =3D dc->pc; - dc->is_jmp =3D DISAS_NEXT; + dc->base.tb =3D tb; + dc->base.pc_first =3D tb->pc; + dc->base.pc_next =3D tb->pc; + dc->base.is_jmp =3D DISAS_NEXT; + dc->base.num_insns =3D 0; + dc->base.singlestep_enabled =3D cs->singlestep_enabled; + + dc->pc =3D dc->base.pc_first; dc->npc =3D (target_ulong) tb->cs_base; dc->cc_op =3D CC_OP_DYNAMIC; dc->mem_idx =3D tb->flags & TB_FLAG_MMU_MASK; dc->def =3D &env->def; dc->fpu_enabled =3D tb_fpu_enabled(tb->flags); dc->address_mask_32bit =3D tb_am_enabled(tb->flags); - dc->singlestep =3D (cs->singlestep_enabled || singlestep); + #ifndef CONFIG_USER_ONLY dc->supervisor =3D (tb->flags & TB_FLAG_SUPER) !=3D 0; #endif @@ -5767,7 +5766,6 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock * tb) #endif #endif =20 - num_insns =3D 0; max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; @@ -5775,6 +5773,9 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock * tb) if (max_insns > TCG_MAX_INSNS) { max_insns =3D TCG_MAX_INSNS; } + if (singlestep) { + max_insns =3D 1; + } =20 gen_tb_start(tb); do { @@ -5784,51 +5785,53 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock * tb) } else { tcg_gen_insn_start(dc->pc, dc->npc); } - num_insns++; - last_pc =3D dc->pc; + dc->base.num_insns++; =20 - if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { - if (dc->pc !=3D pc_start) { + if (unlikely(cpu_breakpoint_test(cs, dc->base.pc_next, BP_ANY))) { + if (dc->pc !=3D dc->base.pc_first) { save_state(dc); } gen_helper_debug(cpu_env); tcg_gen_exit_tb(0); - dc->is_jmp =3D DISAS_NORETURN; + dc->base.is_jmp =3D DISAS_NORETURN; + dc->base.pc_next +=3D 4; goto exit_gen_loop; } =20 - if (num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAST_IO)) { + if (dc->base.num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAS= T_IO)) { gen_io_start(); } =20 insn =3D cpu_ldl_code(env, dc->pc); + dc->base.pc_next +=3D 4; =20 disas_sparc_insn(dc, insn); =20 - if (dc->is_jmp =3D=3D DISAS_NORETURN) { + if (dc->base.is_jmp =3D=3D DISAS_NORETURN) { break; } /* if the next PC is different, we abort now */ - if (dc->pc !=3D (last_pc + 4)) + if (dc->pc !=3D dc->base.pc_next) { break; + } /* if we reach a page boundary, we stop generation so that the PC of a TT_TFAULT exception is always in the right page */ if ((dc->pc & (TARGET_PAGE_SIZE - 1)) =3D=3D 0) break; /* if single step mode, we generate only one instruction and generate an exception */ - if (dc->singlestep) { + if (dc->base.singlestep_enabled) { break; } } while (!tcg_op_buf_full() && - (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32) && - num_insns < max_insns); + (dc->pc - dc->base.pc_first) < (TARGET_PAGE_SIZE - 32) && + dc->base.num_insns < max_insns); =20 exit_gen_loop: if (tb_cflags(tb) & CF_LAST_IO) { gen_io_end(); } - if (dc->is_jmp !=3D DISAS_NORETURN) { + if (dc->base.is_jmp !=3D DISAS_NORETURN) { if (dc->pc !=3D DYNAMIC_PC && (dc->npc !=3D DYNAMIC_PC && dc->npc !=3D JUMP_PC)) { /* static PC and NPC: we can use direct chaining */ @@ -5841,18 +5844,19 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock * tb) tcg_gen_exit_tb(0); } } - gen_tb_end(tb, num_insns); + gen_tb_end(tb, dc->base.num_insns); =20 - tb->size =3D last_pc + 4 - pc_start; - tb->icount =3D num_insns; + tb->size =3D dc->base.pc_next - dc->base.pc_first; + tb->icount =3D dc->base.num_insns; =20 #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(pc_start)) { + && qemu_log_in_addr_range(dc->base.pc_first)) { qemu_log_lock(); qemu_log("--------------\n"); - qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, last_pc + 4 - pc_start); + qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); + log_target_disas(cs, dc->base.pc_first, + dc->base.pc_next - dc->base.pc_first); qemu_log("\n"); qemu_log_unlock(); } --=20 2.7.4 From nobody Fri Oct 24 09:56:46 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1518737349670870.5637735097264; Thu, 15 Feb 2018 15:29:09 -0800 (PST) Received: from localhost ([::1]:42911 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1emSxg-0007A2-Ri for importer@patchew.org; Thu, 15 Feb 2018 18:29:08 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46769) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1emSn3-0003bR-56 for qemu-devel@nongnu.org; Thu, 15 Feb 2018 18:18:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1emSmz-0000l8-Ts for qemu-devel@nongnu.org; Thu, 15 Feb 2018 18:18:09 -0500 Received: from out5-smtp.messagingengine.com ([66.111.4.29]:58143) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1emSmz-0000ko-Ok for qemu-devel@nongnu.org; Thu, 15 Feb 2018 18:18:05 -0500 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 76DB820DE5; Thu, 15 Feb 2018 18:18:05 -0500 (EST) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Thu, 15 Feb 2018 18:18:05 -0500 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 2B18B7E1DE; Thu, 15 Feb 2018 18:18:05 -0500 (EST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc; s=mesmtp; bh=Tjrc1NYUNs67/T xSQUQIunHM89LN4v0KwZfvEg7NpGI=; b=iaERSLuFQZPIsKgv8/YTRxsLHXxBv5 F24ymarzW18QvwbKx7So8hIgyjuQdJvVODuHI6+GLQFrrj35I/XV/n+Dr9YwY7YK E3wvCaQh7G/5mfTjqnf/UpQI/LQ9DbuKBsbkQ6TmapKG3VQ2WKwqAHDQP4zkIKGM waq5HMQI44P4Y= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc; s= fm2; bh=Tjrc1NYUNs67/TxSQUQIunHM89LN4v0KwZfvEg7NpGI=; b=gMlG6IJ3 YOgs5FMx6yoPkzj7zjxVKPCd8Bwz3cDJCWSlwEY4OMOol3DLz9kQJQQzScVhSImd 55td648EvfP+r6coWQGtCoydlUIzBeBdx8fdX8j2LzJvkCHKfENB+KMlJyiarwEi DAczvPL4z2ejt8XOZoCQvFywWCOeX+vKd2t2dIwtHIKOcLw08Ph7vtLcVwBWk3M+ tgafH4L9P/CXiCn3653vp0ggn6ZsVK8Km3Z2oJjEtAywxmT/zbMC3uVIo0ljyQsl EjQw2M/OLSQ9wXlQPFmboYGNoWb7yhTh14Sp2VPR9saBZuKTesdzp5UMhg9iiZ0Q SSnHWZZGlwXP5A== X-ME-Sender: From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Thu, 15 Feb 2018 18:17:56 -0500 Message-Id: <1518736676-5994-4-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1518736676-5994-1-git-send-email-cota@braap.org> References: <1518736676-5994-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.29 Subject: [Qemu-devel] [PATCH 3/3] target/sparc: convert to TranslatorOps X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland , Artyom Tarasenko , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Notes: - Moved the cross-page check from the end of translate_insn to init_disas_context. Signed-off-by: Emilio G. Cota --- target/sparc/translate.c | 181 +++++++++++++++++++++++--------------------= ---- 1 file changed, 88 insertions(+), 93 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index da77a27..5a25a51 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5732,105 +5732,94 @@ static void disas_sparc_insn(DisasContext * dc, un= signed int insn) } } =20 -void gen_intermediate_code(CPUState *cs, TranslationBlock * tb) +static int sparc_tr_init_disas_context(DisasContextBase *dcbase, + CPUState *cs, int max_insns) { + DisasContext *dc =3D container_of(dcbase, DisasContext, base); CPUSPARCState *env =3D cs->env_ptr; - DisasContext dc1, *dc =3D &dc1; - int max_insns; - unsigned int insn; - - memset(dc, 0, sizeof(DisasContext)); - dc->base.tb =3D tb; - dc->base.pc_first =3D tb->pc; - dc->base.pc_next =3D tb->pc; - dc->base.is_jmp =3D DISAS_NEXT; - dc->base.num_insns =3D 0; - dc->base.singlestep_enabled =3D cs->singlestep_enabled; + int bound; =20 dc->pc =3D dc->base.pc_first; - dc->npc =3D (target_ulong) tb->cs_base; + dc->npc =3D (target_ulong)dc->base.tb->cs_base; dc->cc_op =3D CC_OP_DYNAMIC; - dc->mem_idx =3D tb->flags & TB_FLAG_MMU_MASK; + dc->mem_idx =3D dc->base.tb->flags & TB_FLAG_MMU_MASK; dc->def =3D &env->def; - dc->fpu_enabled =3D tb_fpu_enabled(tb->flags); - dc->address_mask_32bit =3D tb_am_enabled(tb->flags); + dc->fpu_enabled =3D tb_fpu_enabled(dc->base.tb->flags); + dc->address_mask_32bit =3D tb_am_enabled(dc->base.tb->flags); =20 #ifndef CONFIG_USER_ONLY - dc->supervisor =3D (tb->flags & TB_FLAG_SUPER) !=3D 0; + dc->supervisor =3D (dc->base.tb->flags & TB_FLAG_SUPER) !=3D 0; #endif #ifdef TARGET_SPARC64 dc->fprs_dirty =3D 0; - dc->asi =3D (tb->flags >> TB_FLAG_ASI_SHIFT) & 0xff; + dc->asi =3D (dc->base.tb->flags >> TB_FLAG_ASI_SHIFT) & 0xff; #ifndef CONFIG_USER_ONLY - dc->hypervisor =3D (tb->flags & TB_FLAG_HYPER) !=3D 0; + dc->hypervisor =3D (dc->base.tb->flags & TB_FLAG_HYPER) !=3D 0; #endif #endif + /* + * if we reach a page boundary, we stop generation so that the + * PC of a TT_TFAULT exception is always in the right page + */ + bound =3D -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; + return MIN(max_insns, bound); +} =20 - max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } - if (singlestep) { - max_insns =3D 1; - } +static void sparc_tr_tb_start(DisasContextBase *db, CPUState *cs) +{ +} =20 - gen_tb_start(tb); - do { - if (dc->npc & JUMP_PC) { - assert(dc->jump_pc[1] =3D=3D dc->pc + 4); - tcg_gen_insn_start(dc->pc, dc->jump_pc[0] | JUMP_PC); - } else { - tcg_gen_insn_start(dc->pc, dc->npc); - } - dc->base.num_insns++; +static void sparc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); =20 - if (unlikely(cpu_breakpoint_test(cs, dc->base.pc_next, BP_ANY))) { - if (dc->pc !=3D dc->base.pc_first) { - save_state(dc); - } - gen_helper_debug(cpu_env); - tcg_gen_exit_tb(0); - dc->base.is_jmp =3D DISAS_NORETURN; - dc->base.pc_next +=3D 4; - goto exit_gen_loop; - } + if (dc->npc & JUMP_PC) { + assert(dc->jump_pc[1] =3D=3D dc->pc + 4); + tcg_gen_insn_start(dc->pc, dc->jump_pc[0] | JUMP_PC); + } else { + tcg_gen_insn_start(dc->pc, dc->npc); + } +} =20 - if (dc->base.num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAS= T_IO)) { - gen_io_start(); - } +static bool sparc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *= cs, + const CPUBreakpoint *bp) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); =20 - insn =3D cpu_ldl_code(env, dc->pc); - dc->base.pc_next +=3D 4; + if (dc->pc !=3D dc->base.pc_first) { + save_state(dc); + } + gen_helper_debug(cpu_env); + tcg_gen_exit_tb(0); + dc->base.is_jmp =3D DISAS_NORETURN; + /* update pc_next so that the current instruction is included in tb->s= ize */ + dc->base.pc_next +=3D 4; + return true; +} =20 - disas_sparc_insn(dc, insn); +static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + CPUSPARCState *env =3D cs->env_ptr; + unsigned int insn; =20 - if (dc->base.is_jmp =3D=3D DISAS_NORETURN) { - break; - } - /* if the next PC is different, we abort now */ - if (dc->pc !=3D dc->base.pc_next) { - break; - } - /* if we reach a page boundary, we stop generation so that the - PC of a TT_TFAULT exception is always in the right page */ - if ((dc->pc & (TARGET_PAGE_SIZE - 1)) =3D=3D 0) - break; - /* if single step mode, we generate only one instruction and - generate an exception */ - if (dc->base.singlestep_enabled) { - break; - } - } while (!tcg_op_buf_full() && - (dc->pc - dc->base.pc_first) < (TARGET_PAGE_SIZE - 32) && - dc->base.num_insns < max_insns); + insn =3D cpu_ldl_code(env, dc->pc); + dc->base.pc_next +=3D 4; + disas_sparc_insn(dc, insn); =20 - exit_gen_loop: - if (tb_cflags(tb) & CF_LAST_IO) { - gen_io_end(); + if (dc->base.is_jmp =3D=3D DISAS_NORETURN) { + return; + } + if (dc->pc !=3D dc->base.pc_next || + (dc->pc - dc->base.pc_first) >=3D (TARGET_PAGE_SIZE - 32)) { + dc->base.is_jmp =3D DISAS_TOO_MANY; } +} + +static void sparc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + if (dc->base.is_jmp !=3D DISAS_NORETURN) { if (dc->pc !=3D DYNAMIC_PC && (dc->npc !=3D DYNAMIC_PC && dc->npc !=3D JUMP_PC)) { @@ -5844,23 +5833,29 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock * tb) tcg_gen_exit_tb(0); } } - gen_tb_end(tb, dc->base.num_insns); - - tb->size =3D dc->base.pc_next - dc->base.pc_first; - tb->icount =3D dc->base.num_insns; - -#ifdef DEBUG_DISAS - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(dc->base.pc_first)) { - qemu_log_lock(); - qemu_log("--------------\n"); - qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); - log_target_disas(cs, dc->base.pc_first, - dc->base.pc_next - dc->base.pc_first); - qemu_log("\n"); - qemu_log_unlock(); - } -#endif +} + +static void sparc_tr_disas_log(const DisasContextBase *dcbase, CPUState *c= pu) +{ + qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); + log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); +} + +static const TranslatorOps sparc_tr_ops =3D { + .init_disas_context =3D sparc_tr_init_disas_context, + .tb_start =3D sparc_tr_tb_start, + .insn_start =3D sparc_tr_insn_start, + .breakpoint_check =3D sparc_tr_breakpoint_check, + .translate_insn =3D sparc_tr_translate_insn, + .tb_stop =3D sparc_tr_tb_stop, + .disas_log =3D sparc_tr_disas_log, +}; + +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +{ + DisasContext dc =3D {}; + + translator_loop(&sparc_tr_ops, &dc.base, cs, tb); } =20 void sparc_tcg_init(void) --=20 2.7.4