From nobody Fri Oct 24 09:56:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1518724442488556.7417933111145; Thu, 15 Feb 2018 11:54:02 -0800 (PST) Received: from localhost ([::1]:54087 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1emPbV-000189-Dk for importer@patchew.org; Thu, 15 Feb 2018 14:54:01 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57119) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1emPZg-0008OL-4e for qemu-devel@nongnu.org; Thu, 15 Feb 2018 14:52:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1emPZb-00037N-Ef for qemu-devel@nongnu.org; Thu, 15 Feb 2018 14:52:08 -0500 Received: from out5-smtp.messagingengine.com ([66.111.4.29]:40121) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1emPZb-00036H-7I; Thu, 15 Feb 2018 14:52:03 -0500 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id C3C6020D25; Thu, 15 Feb 2018 14:52:02 -0500 (EST) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Thu, 15 Feb 2018 14:52:02 -0500 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 725D824550; Thu, 15 Feb 2018 14:52:02 -0500 (EST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc; s=mesmtp; bh=Q8g7hEv47tZF7F V5KD9jaWcwtaXxa1M9nlX2hGycPys=; b=nYoVdz3zoBjJtuGF1FfAb45MXhOiie d1sZsK6ABI3joGlSMDG4+KmPXGXAWv206y9ISQpjwDfb0R4VEnUh4rDw9Yd1Mj67 990aYzBGDhgdPPV+WoACBnYHjn7F/ZJPTC6My6rNE0yNp/PtyXr3l4LsRr3g2OdD zJCGJdDJngTaQ= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc; s= fm2; bh=Q8g7hEv47tZF7FV5KD9jaWcwtaXxa1M9nlX2hGycPys=; b=gfx3gJBN ADekj5zGtq4pgzttYsVkAVx+faonz3pErxoTpVacmhncTLBTM/An/ykwv/Cuctqz ITQ+TqqF0XlDIMi5JIuhtvzGsGThoGeCwzJIFJdnF45tm46oZHoDYB2DNhhpeN5U sqxF5NR9RXbgtr3uClExZynzdyIZk4gkqVxdSpjfPOM9zXtotOF0Yecs6wEqnQLa c+S+fu9IHx3DQ7JFsh4hvf+IwdoyNrNYOYd6DlZvn+fan0O3CnxIn1Q04eD/eLPh MPyWguZP8zNChaaKvEuPgeaYYkEsf3l9zIzQALj62Q4tLU8LYpuFhPvrhYpCkRKD nWmJL6/FYFCU3w== X-ME-Sender: From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Thu, 15 Feb 2018 14:51:48 -0500 Message-Id: <1518724309-5025-2-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1518724309-5025-1-git-send-email-cota@braap.org> References: <1518724309-5025-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.29 Subject: [Qemu-devel] [PATCH 1/2] target/ppc: convert to DisasContextBase X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Gibson , qemu-ppc@nongnu.org, Alexander Graf , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" A couple of notes: - removed ctx->nip in favour of base->pc_next. Yes, it is annoying, but didn't want to waste its 4 bytes. - ctx->singlestep_enabled does a lot more than base.singlestep_enabled; this confused me at first. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- target/ppc/translate.c | 129 +++++++++++++++++++-------------= ---- target/ppc/translate/dfp-impl.inc.c | 16 ++--- target/ppc/translate_init.c | 32 ++++----- 3 files changed, 91 insertions(+), 86 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 4132f67..6e35daa 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -31,6 +31,7 @@ #include "exec/helper-gen.h" =20 #include "trace-tcg.h" +#include "exec/translator.h" #include "exec/log.h" =20 =20 @@ -187,8 +188,7 @@ void ppc_translate_init(void) =20 /* internal defines */ struct DisasContext { - struct TranslationBlock *tb; - target_ulong nip; + DisasContextBase base; uint32_t opcode; uint32_t exception; /* Routine used to access memory */ @@ -275,7 +275,7 @@ static void gen_exception_err(DisasContext *ctx, uint32= _t excp, uint32_t error) * the faulting instruction */ if (ctx->exception =3D=3D POWERPC_EXCP_NONE) { - gen_update_nip(ctx, ctx->nip - 4); + gen_update_nip(ctx, ctx->base.pc_next - 4); } t0 =3D tcg_const_i32(excp); t1 =3D tcg_const_i32(error); @@ -293,7 +293,7 @@ static void gen_exception(DisasContext *ctx, uint32_t e= xcp) * the faulting instruction */ if (ctx->exception =3D=3D POWERPC_EXCP_NONE) { - gen_update_nip(ctx, ctx->nip - 4); + gen_update_nip(ctx, ctx->base.pc_next - 4); } t0 =3D tcg_const_i32(excp); gen_helper_raise_exception(cpu_env, t0); @@ -322,7 +322,7 @@ static void gen_debug_exception(DisasContext *ctx) */ if ((ctx->exception !=3D POWERPC_EXCP_BRANCH) && (ctx->exception !=3D POWERPC_EXCP_SYNC)) { - gen_update_nip(ctx, ctx->nip); + gen_update_nip(ctx, ctx->base.pc_next); } t0 =3D tcg_const_i32(EXCP_DEBUG); gen_helper_raise_exception(cpu_env, t0); @@ -349,7 +349,7 @@ static inline void gen_hvpriv_exception(DisasContext *c= tx, uint32_t error) /* Stop translation */ static inline void gen_stop_exception(DisasContext *ctx) { - gen_update_nip(ctx, ctx->nip); + gen_update_nip(ctx, ctx->base.pc_next); ctx->exception =3D POWERPC_EXCP_STOP; } =20 @@ -978,7 +978,7 @@ static void gen_addpcis(DisasContext *ctx) { target_long d =3D DX(ctx->opcode); =20 - tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->nip + (d << 16)); + tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->base.pc_next + (d << 16= )); } =20 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg= 1, @@ -1580,7 +1580,7 @@ static void gen_pause(DisasContext *ctx) tcg_temp_free_i32(t0); =20 /* Stop translation, this gives other CPUs a chance to run */ - gen_exception_nip(ctx, EXCP_HLT, ctx->nip); + gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); } #endif /* defined(TARGET_PPC64) */ =20 @@ -2397,7 +2397,7 @@ static inline void gen_check_align(DisasContext *ctx,= TCGv EA, int mask) tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); t1 =3D tcg_const_i32(POWERPC_EXCP_ALIGN); t2 =3D tcg_const_i32(ctx->opcode & 0x03FF0000); - gen_update_nip(ctx, ctx->nip - 4); + gen_update_nip(ctx, ctx->base.pc_next - 4); gen_helper_raise_exception_err(cpu_env, t1, t2); tcg_temp_free_i32(t1); tcg_temp_free_i32(t2); @@ -3322,7 +3322,7 @@ static void gen_wait(DisasContext *ctx) -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)= ); tcg_temp_free_i32(t0); /* Stop translation, as the CPU is supposed to sleep from now */ - gen_exception_nip(ctx, EXCP_HLT, ctx->nip); + gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); } =20 #if defined(TARGET_PPC64) @@ -3407,7 +3407,7 @@ static inline bool use_goto_tb(DisasContext *ctx, tar= get_ulong dest) } =20 #ifndef CONFIG_USER_ONLY - return (ctx->tb->pc & TARGET_PAGE_MASK) =3D=3D (dest & TARGET_PAGE_MAS= K); + return (ctx->base.tb->pc & TARGET_PAGE_MASK) =3D=3D (dest & TARGET_PAG= E_MASK); #else return true; #endif @@ -3422,7 +3422,7 @@ static void gen_goto_tb(DisasContext *ctx, int n, tar= get_ulong dest) if (use_goto_tb(ctx, dest)) { tcg_gen_goto_tb(n); tcg_gen_movi_tl(cpu_nip, dest & ~3); - tcg_gen_exit_tb((uintptr_t)ctx->tb + n); + tcg_gen_exit_tb((uintptr_t)ctx->base.tb + n); } else { tcg_gen_movi_tl(cpu_nip, dest & ~3); if (unlikely(ctx->singlestep_enabled)) { @@ -3458,14 +3458,14 @@ static void gen_b(DisasContext *ctx) li =3D LI(ctx->opcode); li =3D (li ^ 0x02000000) - 0x02000000; if (likely(AA(ctx->opcode) =3D=3D 0)) { - target =3D ctx->nip + li - 4; + target =3D ctx->base.pc_next + li - 4; } else { target =3D li; } if (LK(ctx->opcode)) { - gen_setlr(ctx, ctx->nip); + gen_setlr(ctx, ctx->base.pc_next); } - gen_update_cfar(ctx, ctx->nip - 4); + gen_update_cfar(ctx, ctx->base.pc_next - 4); gen_goto_tb(ctx, 0, target); } =20 @@ -3493,7 +3493,7 @@ static void gen_bcond(DisasContext *ctx, int type) target =3D NULL; } if (LK(ctx->opcode)) - gen_setlr(ctx, ctx->nip); + gen_setlr(ctx, ctx->base.pc_next); l1 =3D gen_new_label(); if ((bo & 0x4) =3D=3D 0) { /* Decrement and test CTR */ @@ -3530,11 +3530,11 @@ static void gen_bcond(DisasContext *ctx, int type) } tcg_temp_free_i32(temp); } - gen_update_cfar(ctx, ctx->nip - 4); + gen_update_cfar(ctx, ctx->base.pc_next - 4); if (type =3D=3D BCOND_IM) { target_ulong li =3D (target_long)((int16_t)(BD(ctx->opcode))); if (likely(AA(ctx->opcode) =3D=3D 0)) { - gen_goto_tb(ctx, 0, ctx->nip + li - 4); + gen_goto_tb(ctx, 0, ctx->base.pc_next + li - 4); } else { gen_goto_tb(ctx, 0, li); } @@ -3549,7 +3549,7 @@ static void gen_bcond(DisasContext *ctx, int type) } if ((bo & 0x14) !=3D 0x14) { gen_set_label(l1); - gen_goto_tb(ctx, 1, ctx->nip); + gen_goto_tb(ctx, 1, ctx->base.pc_next); } } =20 @@ -3645,7 +3645,7 @@ static void gen_rfi(DisasContext *ctx) } /* Restore CPU state */ CHK_SV; - gen_update_cfar(ctx, ctx->nip - 4); + gen_update_cfar(ctx, ctx->base.pc_next - 4); gen_helper_rfi(cpu_env); gen_sync_exception(ctx); #endif @@ -3659,7 +3659,7 @@ static void gen_rfid(DisasContext *ctx) #else /* Restore CPU state */ CHK_SV; - gen_update_cfar(ctx, ctx->nip - 4); + gen_update_cfar(ctx, ctx->base.pc_next - 4); gen_helper_rfid(cpu_env); gen_sync_exception(ctx); #endif @@ -3934,10 +3934,11 @@ static inline void gen_op_mfspr(DisasContext *ctx) */ if (sprn !=3D SPR_PVR) { fprintf(stderr, "Trying to read privileged spr %d (0x%03x)= at " - TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); + TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next = - 4); if (qemu_log_separate()) { qemu_log("Trying to read privileged spr %d (0x%03x) at= " - TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); + TARGET_FMT_lx "\n", sprn, sprn, + ctx->base.pc_next - 4); } } gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); @@ -3951,10 +3952,10 @@ static inline void gen_op_mfspr(DisasContext *ctx) } /* Not defined */ fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at " - TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); + TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4); if (qemu_log_separate()) { qemu_log("Trying to read invalid spr %d (0x%03x) at " - TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); + TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4= ); } =20 /* The behaviour depends on MSR:PR and SPR# bit 0x10, @@ -4030,7 +4031,7 @@ static void gen_mtmsrd(DisasContext *ctx) * if we enter power saving mode, we will exit the loop * directly from ppc_store_msr */ - gen_update_nip(ctx, ctx->nip); + gen_update_nip(ctx, ctx->base.pc_next); gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); /* Must stop the translation as machine state (may have) changed */ /* Note that mtmsr is not always defined as context-synchronizing = */ @@ -4059,7 +4060,7 @@ static void gen_mtmsr(DisasContext *ctx) * if we enter power saving mode, we will exit the loop * directly from ppc_store_msr */ - gen_update_nip(ctx, ctx->nip); + gen_update_nip(ctx, ctx->base.pc_next); #if defined(TARGET_PPC64) tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); #else @@ -4097,10 +4098,10 @@ static void gen_mtspr(DisasContext *ctx) } else { /* Privilege exception */ fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at= " - TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); + TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4); if (qemu_log_separate()) { qemu_log("Trying to write privileged spr %d (0x%03x) at " - TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); + TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next= - 4); } gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); } @@ -4115,10 +4116,10 @@ static void gen_mtspr(DisasContext *ctx) /* Not defined */ if (qemu_log_separate()) { qemu_log("Trying to write invalid spr %d (0x%03x) at " - TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); + TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4= ); } fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at " - TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); + TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4); =20 =20 /* The behaviour depends on MSR:PR and SPR# bit 0x10, @@ -7212,13 +7213,14 @@ void gen_intermediate_code(CPUState *cs, struct Tra= nslationBlock *tb) CPUPPCState *env =3D cs->env_ptr; DisasContext ctx, *ctxp =3D &ctx; opc_handler_t **table, *handler; - target_ulong pc_start; - int num_insns; int max_insns; =20 - pc_start =3D tb->pc; - ctx.nip =3D pc_start; - ctx.tb =3D tb; + ctx.base.singlestep_enabled =3D cs->singlestep_enabled; + ctx.base.tb =3D tb; + ctx.base.pc_first =3D tb->pc; + ctx.base.pc_next =3D tb->pc; /* nip */ + ctx.base.num_insns =3D 0; + ctx.exception =3D POWERPC_EXCP_NONE; ctx.spr_cb =3D env->spr_cb; ctx.pr =3D msr_pr; @@ -7270,14 +7272,14 @@ void gen_intermediate_code(CPUState *cs, struct Tra= nslationBlock *tb) ctx.singlestep_enabled =3D 0; if ((env->flags & POWERPC_FLAG_BE) && msr_be) ctx.singlestep_enabled |=3D CPU_BRANCH_STEP; - if (unlikely(cs->singlestep_enabled)) { + if (unlikely(ctx.base.singlestep_enabled)) { ctx.singlestep_enabled |=3D GDBSTUB_SINGLE_STEP; } #if defined (DO_SINGLE_STEP) && 0 /* Single step trace mode */ msr_se =3D 1; #endif - num_insns =3D 0; + ctx.base.num_insns =3D 0; max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; @@ -7290,34 +7292,35 @@ void gen_intermediate_code(CPUState *cs, struct Tra= nslationBlock *tb) tcg_clear_temp_count(); /* Set env in case of segfault during code fetch */ while (ctx.exception =3D=3D POWERPC_EXCP_NONE && !tcg_op_buf_full()) { - tcg_gen_insn_start(ctx.nip); - num_insns++; + tcg_gen_insn_start(ctx.base.pc_next); + ctx.base.num_insns++; =20 - if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) { + if (unlikely(cpu_breakpoint_test(cs, ctx.base.pc_next, BP_ANY))) { gen_debug_exception(ctxp); /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that the logic setting tb->size below does the right thing. */ - ctx.nip +=3D 4; + ctx.base.pc_next +=3D 4; break; } =20 LOG_DISAS("----------------\n"); LOG_DISAS("nip=3D" TARGET_FMT_lx " super=3D%d ir=3D%d\n", - ctx.nip, ctx.mem_idx, (int)msr_ir); - if (num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAST_IO)) + ctx.base.pc_next, ctx.mem_idx, (int)msr_ir); + if (ctx.base.num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAS= T_IO)) { gen_io_start(); + } if (unlikely(need_byteswap(&ctx))) { - ctx.opcode =3D bswap32(cpu_ldl_code(env, ctx.nip)); + ctx.opcode =3D bswap32(cpu_ldl_code(env, ctx.base.pc_next)); } else { - ctx.opcode =3D cpu_ldl_code(env, ctx.nip); + ctx.opcode =3D cpu_ldl_code(env, ctx.base.pc_next); } LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode), opc3(ctx.opcode), opc4(ctx.opcode), ctx.le_mode ? "little" : "big"); - ctx.nip +=3D 4; + ctx.base.pc_next +=3D 4; table =3D env->opcodes; handler =3D table[opc1(ctx.opcode)]; if (is_indirect_opcode(handler)) { @@ -7339,7 +7342,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) TARGET_FMT_lx " %d\n", opc1(ctx.opcode), opc2(ctx.opcode), opc3(ctx.opcode), opc4(ctx.opcode), - ctx.opcode, ctx.nip - 4, (int)msr_ir); + ctx.opcode, ctx.base.pc_next - 4, (int)msr_ir); } else { uint32_t inval; =20 @@ -7355,7 +7358,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) TARGET_FMT_lx "\n", ctx.opcode & inval, opc1(ctx.opcode), opc2(ctx.opcode), opc3(ctx.opcode), opc4(ctx.opcode), - ctx.opcode, ctx.nip - 4); + ctx.opcode, ctx.base.pc_next - 4); gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL); break; } @@ -7366,15 +7369,16 @@ void gen_intermediate_code(CPUState *cs, struct Tra= nslationBlock *tb) #endif /* Check trace mode exceptions */ if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP && - (ctx.nip <=3D 0x100 || ctx.nip > 0xF00) && + (ctx.base.pc_next <=3D 0x100 || ctx.base.pc_next > 0x= F00) && ctx.exception !=3D POWERPC_SYSCALL && ctx.exception !=3D POWERPC_EXCP_TRAP && ctx.exception !=3D POWERPC_EXCP_BRANCH)) { - gen_exception_nip(ctxp, POWERPC_EXCP_TRACE, ctx.nip); - } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) =3D=3D 0) = || - (cs->singlestep_enabled) || + gen_exception_nip(ctxp, POWERPC_EXCP_TRACE, ctx.base.pc_next); + } else if (unlikely(((ctx.base.pc_next & (TARGET_PAGE_SIZE - 1)) + =3D=3D 0) || + (ctx.base.singlestep_enabled) || singlestep || - num_insns >=3D max_insns)) { + ctx.base.num_insns >=3D max_insns)) { /* if we reach a page boundary or are single stepping, stop * generation */ @@ -7390,25 +7394,26 @@ void gen_intermediate_code(CPUState *cs, struct Tra= nslationBlock *tb) if (tb_cflags(tb) & CF_LAST_IO) gen_io_end(); if (ctx.exception =3D=3D POWERPC_EXCP_NONE) { - gen_goto_tb(&ctx, 0, ctx.nip); + gen_goto_tb(&ctx, 0, ctx.base.pc_next); } else if (ctx.exception !=3D POWERPC_EXCP_BRANCH) { - if (unlikely(cs->singlestep_enabled)) { + if (unlikely(ctx.base.singlestep_enabled)) { gen_debug_exception(ctxp); } /* Generate the return instruction */ tcg_gen_exit_tb(0); } - gen_tb_end(tb, num_insns); + gen_tb_end(tb, ctx.base.num_insns); =20 - tb->size =3D ctx.nip - pc_start; - tb->icount =3D num_insns; + tb->size =3D ctx.base.pc_next - ctx.base.pc_first; + tb->icount =3D ctx.base.num_insns; =20 #if defined(DEBUG_DISAS) if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(pc_start)) { + && qemu_log_in_addr_range(ctx.base.pc_first)) { qemu_log_lock(); - qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, ctx.nip - pc_start); + qemu_log("IN: %s\n", lookup_symbol(ctx.base.pc_first)); + log_target_disas(cs, ctx.base.pc_first, + ctx.base.pc_next - ctx.base.pc_first); qemu_log("\n"); qemu_log_unlock(); } diff --git a/target/ppc/translate/dfp-impl.inc.c b/target/ppc/translate/dfp= -impl.inc.c index 178d304..634ef73 100644 --- a/target/ppc/translate/dfp-impl.inc.c +++ b/target/ppc/translate/dfp-impl.inc.c @@ -15,7 +15,7 @@ static void gen_##name(DisasContext *ctx) \ gen_exception(ctx, POWERPC_EXCP_FPU); \ return; \ } \ - gen_update_nip(ctx, ctx->nip - 4); \ + gen_update_nip(ctx, ctx->base.pc_next - 4); \ rd =3D gen_fprp_ptr(rD(ctx->opcode)); \ ra =3D gen_fprp_ptr(rA(ctx->opcode)); \ rb =3D gen_fprp_ptr(rB(ctx->opcode)); \ @@ -36,7 +36,7 @@ static void gen_##name(DisasContext *ctx) \ gen_exception(ctx, POWERPC_EXCP_FPU); \ return; \ } \ - gen_update_nip(ctx, ctx->nip - 4); \ + gen_update_nip(ctx, ctx->base.pc_next - 4); \ ra =3D gen_fprp_ptr(rA(ctx->opcode)); \ rb =3D gen_fprp_ptr(rB(ctx->opcode)); \ gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \ @@ -54,7 +54,7 @@ static void gen_##name(DisasContext *ctx) \ gen_exception(ctx, POWERPC_EXCP_FPU); \ return; \ } \ - gen_update_nip(ctx, ctx->nip - 4); \ + gen_update_nip(ctx, ctx->base.pc_next - 4); \ uim =3D tcg_const_i32(UIMM5(ctx->opcode)); \ rb =3D gen_fprp_ptr(rB(ctx->opcode)); \ gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \ @@ -72,7 +72,7 @@ static void gen_##name(DisasContext *ctx) \ gen_exception(ctx, POWERPC_EXCP_FPU); \ return; \ } \ - gen_update_nip(ctx, ctx->nip - 4); \ + gen_update_nip(ctx, ctx->base.pc_next - 4); \ ra =3D gen_fprp_ptr(rA(ctx->opcode)); \ dcm =3D tcg_const_i32(DCM(ctx->opcode)); \ gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \ @@ -90,7 +90,7 @@ static void gen_##name(DisasContext *ctx) \ gen_exception(ctx, POWERPC_EXCP_FPU); \ return; \ } \ - gen_update_nip(ctx, ctx->nip - 4); \ + gen_update_nip(ctx, ctx->base.pc_next - 4); \ rt =3D gen_fprp_ptr(rD(ctx->opcode)); \ rb =3D gen_fprp_ptr(rB(ctx->opcode)); \ u32_1 =3D tcg_const_i32(u32f1(ctx->opcode)); \ @@ -114,7 +114,7 @@ static void gen_##name(DisasContext *ctx) \ gen_exception(ctx, POWERPC_EXCP_FPU); \ return; \ } \ - gen_update_nip(ctx, ctx->nip - 4); \ + gen_update_nip(ctx, ctx->base.pc_next - 4); \ rt =3D gen_fprp_ptr(rD(ctx->opcode)); \ ra =3D gen_fprp_ptr(rA(ctx->opcode)); \ rb =3D gen_fprp_ptr(rB(ctx->opcode)); \ @@ -137,7 +137,7 @@ static void gen_##name(DisasContext *ctx) \ gen_exception(ctx, POWERPC_EXCP_FPU); \ return; \ } \ - gen_update_nip(ctx, ctx->nip - 4); \ + gen_update_nip(ctx, ctx->base.pc_next - 4); \ rt =3D gen_fprp_ptr(rD(ctx->opcode)); \ rb =3D gen_fprp_ptr(rB(ctx->opcode)); \ gen_helper_##name(cpu_env, rt, rb); \ @@ -157,7 +157,7 @@ static void gen_##name(DisasContext *ctx) \ gen_exception(ctx, POWERPC_EXCP_FPU); \ return; \ } \ - gen_update_nip(ctx, ctx->nip - 4); \ + gen_update_nip(ctx, ctx->base.pc_next - 4); \ rt =3D gen_fprp_ptr(rD(ctx->opcode)); \ rs =3D gen_fprp_ptr(fprfld(ctx->opcode)); \ i32 =3D tcg_const_i32(i32fld(ctx->opcode)); \ diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index 48f2c10..cbaa343 100644 --- a/target/ppc/translate_init.c +++ b/target/ppc/translate_init.c @@ -179,11 +179,11 @@ static void spr_write_ureg(DisasContext *ctx, int spr= n, int gprn) #if !defined(CONFIG_USER_ONLY) static void spr_read_decr(DisasContext *ctx, int gprn, int sprn) { - if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_load_decr(cpu_gpr[gprn], cpu_env); - if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { gen_io_end(); gen_stop_exception(ctx); } @@ -191,11 +191,11 @@ static void spr_read_decr(DisasContext *ctx, int gprn= , int sprn) =20 static void spr_write_decr(DisasContext *ctx, int sprn, int gprn) { - if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); - if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { gen_io_end(); gen_stop_exception(ctx); } @@ -206,11 +206,11 @@ static void spr_write_decr(DisasContext *ctx, int spr= n, int gprn) /* Time base */ static void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) { - if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); - if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { gen_io_end(); gen_stop_exception(ctx); } @@ -218,11 +218,11 @@ static void spr_read_tbl(DisasContext *ctx, int gprn,= int sprn) =20 static void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) { - if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); - if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { gen_io_end(); gen_stop_exception(ctx); } @@ -243,11 +243,11 @@ static void spr_read_atbu(DisasContext *ctx, int gprn= , int sprn) #if !defined(CONFIG_USER_ONLY) static void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) { - if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); - if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { gen_io_end(); gen_stop_exception(ctx); } @@ -255,11 +255,11 @@ static void spr_write_tbl(DisasContext *ctx, int sprn= , int gprn) =20 static void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) { - if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); - if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { gen_io_end(); gen_stop_exception(ctx); } @@ -287,11 +287,11 @@ static void spr_read_purr(DisasContext *ctx, int gprn= , int sprn) /* HDECR */ static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) { - if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); - if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { gen_io_end(); gen_stop_exception(ctx); } @@ -299,11 +299,11 @@ static void spr_read_hdecr(DisasContext *ctx, int gpr= n, int sprn) =20 static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) { - if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); - if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { gen_io_end(); gen_stop_exception(ctx); } --=20 2.7.4 From nobody Fri Oct 24 09:56:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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s= fm2; bh=cinsF3qXTpy/j1QdFqO1nNEeqasZhQoHJwbSpLJN6d0=; b=Iu9J8Ipi wHeDP+sLRT+nG+8YjeanY86UNGXR8tRD4LptaIGXnG2Cnv3G+ACaAUst9OTlw9e3 X++J7hs9uIpvs7EJxAIZyAkmFfKHSKURjC6n+QFuQ79L54Nt8klBfu19KOkA7B3i VMV9zD2pNineuMh8mnmeRkL6AMkEKrGl3H7+tKD6sgnAaFce/vDjatU0IA0ApfGR TAvyN5ptoui5gX67hFts0/BKcLEWDwUhfa9zy6tqe2MldMaUwZM9CBd6P4ldvIsX 515+MlBU9oryHd9m8W6TjMAyO4W3z9GfTCaof/K/ODD13WMGmv8zYZfQEDke5hWJ U/KVNb2xuX2MLg== X-ME-Sender: From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Thu, 15 Feb 2018 14:51:49 -0500 Message-Id: <1518724309-5025-3-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1518724309-5025-1-git-send-email-cota@braap.org> References: <1518724309-5025-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.29 Subject: [Qemu-devel] [PATCH 2/2] target/ppc: convert to TranslatorOps X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Gibson , qemu-ppc@nongnu.org, Alexander Graf , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" A few changes worth noting: - Didn't migrate ctx->exception to DISAS_* since the exception field is in many cases architecturally relevant. - Moved the cross-page check from the end of translate_insn to tb_start. - Removed the exit(1) after a TCG temp leak; changed the fprintf there to qemu_log. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- target/ppc/translate.c | 329 +++++++++++++++++++++++++--------------------= ---- 1 file changed, 167 insertions(+), 162 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 6e35daa..0a0c090 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7207,217 +7207,222 @@ void ppc_cpu_dump_statistics(CPUState *cs, FILE*f, #endif } =20 -/*************************************************************************= ****/ -void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) +static int ppc_tr_init_disas_context(DisasContextBase *dcbase, + CPUState *cs, int max_insns) { + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); CPUPPCState *env =3D cs->env_ptr; - DisasContext ctx, *ctxp =3D &ctx; - opc_handler_t **table, *handler; - int max_insns; - - ctx.base.singlestep_enabled =3D cs->singlestep_enabled; - ctx.base.tb =3D tb; - ctx.base.pc_first =3D tb->pc; - ctx.base.pc_next =3D tb->pc; /* nip */ - ctx.base.num_insns =3D 0; - - ctx.exception =3D POWERPC_EXCP_NONE; - ctx.spr_cb =3D env->spr_cb; - ctx.pr =3D msr_pr; - ctx.mem_idx =3D env->dmmu_idx; - ctx.dr =3D msr_dr; + int bound; + + ctx->exception =3D POWERPC_EXCP_NONE; + ctx->spr_cb =3D env->spr_cb; + ctx->pr =3D msr_pr; + ctx->mem_idx =3D env->dmmu_idx; + ctx->dr =3D msr_dr; #if !defined(CONFIG_USER_ONLY) - ctx.hv =3D msr_hv || !env->has_hv_mode; + ctx->hv =3D msr_hv || !env->has_hv_mode; #endif - ctx.insns_flags =3D env->insns_flags; - ctx.insns_flags2 =3D env->insns_flags2; - ctx.access_type =3D -1; - ctx.need_access_type =3D !(env->mmu_model & POWERPC_MMU_64B); - ctx.le_mode =3D !!(env->hflags & (1 << MSR_LE)); - ctx.default_tcg_memop_mask =3D ctx.le_mode ? MO_LE : MO_BE; + ctx->insns_flags =3D env->insns_flags; + ctx->insns_flags2 =3D env->insns_flags2; + ctx->access_type =3D -1; + ctx->need_access_type =3D !(env->mmu_model & POWERPC_MMU_64B); + ctx->le_mode =3D !!(env->hflags & (1 << MSR_LE)); + ctx->default_tcg_memop_mask =3D ctx->le_mode ? MO_LE : MO_BE; #if defined(TARGET_PPC64) - ctx.sf_mode =3D msr_is_64bit(env, env->msr); - ctx.has_cfar =3D !!(env->flags & POWERPC_FLAG_CFAR); + ctx->sf_mode =3D msr_is_64bit(env, env->msr); + ctx->has_cfar =3D !!(env->flags & POWERPC_FLAG_CFAR); #endif if (env->mmu_model =3D=3D POWERPC_MMU_32B || env->mmu_model =3D=3D POWERPC_MMU_601 || (env->mmu_model & POWERPC_MMU_64B)) - ctx.lazy_tlb_flush =3D true; + ctx->lazy_tlb_flush =3D true; =20 - ctx.fpu_enabled =3D !!msr_fp; + ctx->fpu_enabled =3D !!msr_fp; if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) - ctx.spe_enabled =3D !!msr_spe; + ctx->spe_enabled =3D !!msr_spe; else - ctx.spe_enabled =3D false; + ctx->spe_enabled =3D false; if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) - ctx.altivec_enabled =3D !!msr_vr; + ctx->altivec_enabled =3D !!msr_vr; else - ctx.altivec_enabled =3D false; + ctx->altivec_enabled =3D false; if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) { - ctx.vsx_enabled =3D !!msr_vsx; + ctx->vsx_enabled =3D !!msr_vsx; } else { - ctx.vsx_enabled =3D false; + ctx->vsx_enabled =3D false; } #if defined(TARGET_PPC64) if ((env->flags & POWERPC_FLAG_TM) && msr_tm) { - ctx.tm_enabled =3D !!msr_tm; + ctx->tm_enabled =3D !!msr_tm; } else { - ctx.tm_enabled =3D false; + ctx->tm_enabled =3D false; } #endif - ctx.gtse =3D !!(env->spr[SPR_LPCR] & LPCR_GTSE); + ctx->gtse =3D !!(env->spr[SPR_LPCR] & LPCR_GTSE); if ((env->flags & POWERPC_FLAG_SE) && msr_se) - ctx.singlestep_enabled =3D CPU_SINGLE_STEP; + ctx->singlestep_enabled =3D CPU_SINGLE_STEP; else - ctx.singlestep_enabled =3D 0; + ctx->singlestep_enabled =3D 0; if ((env->flags & POWERPC_FLAG_BE) && msr_be) - ctx.singlestep_enabled |=3D CPU_BRANCH_STEP; - if (unlikely(ctx.base.singlestep_enabled)) { - ctx.singlestep_enabled |=3D GDBSTUB_SINGLE_STEP; + ctx->singlestep_enabled |=3D CPU_BRANCH_STEP; + if (unlikely(ctx->base.singlestep_enabled)) { + ctx->singlestep_enabled |=3D GDBSTUB_SINGLE_STEP; } #if defined (DO_SINGLE_STEP) && 0 /* Single step trace mode */ msr_se =3D 1; #endif - ctx.base.num_insns =3D 0; - max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } - - gen_tb_start(tb); - tcg_clear_temp_count(); - /* Set env in case of segfault during code fetch */ - while (ctx.exception =3D=3D POWERPC_EXCP_NONE && !tcg_op_buf_full()) { - tcg_gen_insn_start(ctx.base.pc_next); - ctx.base.num_insns++; - - if (unlikely(cpu_breakpoint_test(cs, ctx.base.pc_next, BP_ANY))) { - gen_debug_exception(ctxp); - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - ctx.base.pc_next +=3D 4; - break; - } =20 - LOG_DISAS("----------------\n"); - LOG_DISAS("nip=3D" TARGET_FMT_lx " super=3D%d ir=3D%d\n", - ctx.base.pc_next, ctx.mem_idx, (int)msr_ir); - if (ctx.base.num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAS= T_IO)) { - gen_io_start(); - } - if (unlikely(need_byteswap(&ctx))) { - ctx.opcode =3D bswap32(cpu_ldl_code(env, ctx.base.pc_next)); - } else { - ctx.opcode =3D cpu_ldl_code(env, ctx.base.pc_next); - } - LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", - ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode), - opc3(ctx.opcode), opc4(ctx.opcode), - ctx.le_mode ? "little" : "big"); - ctx.base.pc_next +=3D 4; - table =3D env->opcodes; - handler =3D table[opc1(ctx.opcode)]; + bound =3D -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; + return MIN(max_insns, bound); +} + +static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) +{ +} + +static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) +{ + tcg_gen_insn_start(dcbase->pc_next); +} + +static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, + const CPUBreakpoint *bp) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); + + gen_debug_exception(ctx); + /* The address covered by the breakpoint must be included in + [tb->pc, tb->pc + tb->size) in order to for it to be + properly cleared -- thus we increment the PC here so that + the logic setting tb->size below does the right thing. */ + ctx->base.pc_next +=3D 4; + return true; +} + +static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); + CPUPPCState *env =3D cs->env_ptr; + opc_handler_t **table, *handler; + + LOG_DISAS("----------------\n"); + LOG_DISAS("nip=3D" TARGET_FMT_lx " super=3D%d ir=3D%d\n", + ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); + + if (unlikely(need_byteswap(ctx))) { + ctx->opcode =3D bswap32(cpu_ldl_code(env, ctx->base.pc_next)); + } else { + ctx->opcode =3D cpu_ldl_code(env, ctx->base.pc_next); + } + LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", + ctx->opcode, opc1(ctx->opcode), opc2(ctx->opcode), + opc3(ctx->opcode), opc4(ctx->opcode), + ctx->le_mode ? "little" : "big"); + ctx->base.pc_next +=3D 4; + table =3D env->opcodes; + handler =3D table[opc1(ctx->opcode)]; + if (is_indirect_opcode(handler)) { + table =3D ind_table(handler); + handler =3D table[opc2(ctx->opcode)]; if (is_indirect_opcode(handler)) { table =3D ind_table(handler); - handler =3D table[opc2(ctx.opcode)]; + handler =3D table[opc3(ctx->opcode)]; if (is_indirect_opcode(handler)) { table =3D ind_table(handler); - handler =3D table[opc3(ctx.opcode)]; - if (is_indirect_opcode(handler)) { - table =3D ind_table(handler); - handler =3D table[opc4(ctx.opcode)]; - } + handler =3D table[opc4(ctx->opcode)]; } } - /* Is opcode *REALLY* valid ? */ - if (unlikely(handler->handler =3D=3D &gen_invalid)) { - qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " - "%02x - %02x - %02x - %02x (%08x) " - TARGET_FMT_lx " %d\n", - opc1(ctx.opcode), opc2(ctx.opcode), - opc3(ctx.opcode), opc4(ctx.opcode), - ctx.opcode, ctx.base.pc_next - 4, (int)msr_ir); - } else { - uint32_t inval; + } + /* Is opcode *REALLY* valid ? */ + if (unlikely(handler->handler =3D=3D &gen_invalid)) { + qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " + "%02x - %02x - %02x - %02x (%08x) " + TARGET_FMT_lx " %d\n", + opc1(ctx->opcode), opc2(ctx->opcode), + opc3(ctx->opcode), opc4(ctx->opcode), + ctx->opcode, ctx->base.pc_next - 4, (int)msr_ir); + } else { + uint32_t inval; =20 - if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_S= PE_DOUBLE) && Rc(ctx.opcode))) { - inval =3D handler->inval2; - } else { - inval =3D handler->inval1; - } + if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_D= OUBLE) + && Rc(ctx->opcode))) { + inval =3D handler->inval2; + } else { + inval =3D handler->inval1; + } =20 - if (unlikely((ctx.opcode & inval) !=3D 0)) { - qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opc= ode: " - "%02x - %02x - %02x - %02x (%08x) " - TARGET_FMT_lx "\n", ctx.opcode & inval, - opc1(ctx.opcode), opc2(ctx.opcode), - opc3(ctx.opcode), opc4(ctx.opcode), - ctx.opcode, ctx.base.pc_next - 4); - gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL); - break; - } + if (unlikely((ctx->opcode & inval) !=3D 0)) { + qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode:= " + "%02x - %02x - %02x - %02x (%08x) " + TARGET_FMT_lx "\n", ctx->opcode & inval, + opc1(ctx->opcode), opc2(ctx->opcode), + opc3(ctx->opcode), opc4(ctx->opcode), + ctx->opcode, ctx->base.pc_next - 4); + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); + ctx->base.is_jmp =3D DISAS_NORETURN; + return; } - (*(handler->handler))(&ctx); + } + (*(handler->handler))(ctx); #if defined(DO_PPC_STATISTICS) - handler->count++; + handler->count++; #endif - /* Check trace mode exceptions */ - if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP && - (ctx.base.pc_next <=3D 0x100 || ctx.base.pc_next > 0x= F00) && - ctx.exception !=3D POWERPC_SYSCALL && - ctx.exception !=3D POWERPC_EXCP_TRAP && - ctx.exception !=3D POWERPC_EXCP_BRANCH)) { - gen_exception_nip(ctxp, POWERPC_EXCP_TRACE, ctx.base.pc_next); - } else if (unlikely(((ctx.base.pc_next & (TARGET_PAGE_SIZE - 1)) - =3D=3D 0) || - (ctx.base.singlestep_enabled) || - singlestep || - ctx.base.num_insns >=3D max_insns)) { - /* if we reach a page boundary or are single stepping, stop - * generation - */ - break; - } - if (tcg_check_temp_count()) { - fprintf(stderr, "Opcode %02x %02x %02x %02x (%08x) leaked " - "temporaries\n", opc1(ctx.opcode), opc2(ctx.opcode), - opc3(ctx.opcode), opc4(ctx.opcode), ctx.opcode); - exit(1); - } + /* Check trace mode exceptions */ + if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP && + (ctx->base.pc_next <=3D 0x100 || ctx->base.pc_next > 0xF0= 0) && + ctx->exception !=3D POWERPC_SYSCALL && + ctx->exception !=3D POWERPC_EXCP_TRAP && + ctx->exception !=3D POWERPC_EXCP_BRANCH)) { + gen_exception_nip(ctx, POWERPC_EXCP_TRACE, ctx->base.pc_next); + } + + if (tcg_check_temp_count()) { + qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked " + "temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode), + opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode); } - if (tb_cflags(tb) & CF_LAST_IO) - gen_io_end(); - if (ctx.exception =3D=3D POWERPC_EXCP_NONE) { - gen_goto_tb(&ctx, 0, ctx.base.pc_next); - } else if (ctx.exception !=3D POWERPC_EXCP_BRANCH) { - if (unlikely(ctx.base.singlestep_enabled)) { - gen_debug_exception(ctxp); + + ctx->base.is_jmp =3D ctx->exception =3D=3D POWERPC_EXCP_NONE ? + DISAS_NEXT : DISAS_NORETURN; +} + +static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); + + if (ctx->exception =3D=3D POWERPC_EXCP_NONE) { + gen_goto_tb(ctx, 0, ctx->base.pc_next); + } else if (ctx->exception !=3D POWERPC_EXCP_BRANCH) { + if (unlikely(ctx->base.singlestep_enabled)) { + gen_debug_exception(ctx); } /* Generate the return instruction */ tcg_gen_exit_tb(0); } - gen_tb_end(tb, ctx.base.num_insns); +} + +static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) +{ + qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); + log_target_disas(cs, dcbase->pc_first, dcbase->tb->size); +} =20 - tb->size =3D ctx.base.pc_next - ctx.base.pc_first; - tb->icount =3D ctx.base.num_insns; +static const TranslatorOps ppc_tr_ops =3D { + .init_disas_context =3D ppc_tr_init_disas_context, + .tb_start =3D ppc_tr_tb_start, + .insn_start =3D ppc_tr_insn_start, + .breakpoint_check =3D ppc_tr_breakpoint_check, + .translate_insn =3D ppc_tr_translate_insn, + .tb_stop =3D ppc_tr_tb_stop, + .disas_log =3D ppc_tr_disas_log, +}; =20 -#if defined(DEBUG_DISAS) - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(ctx.base.pc_first)) { - qemu_log_lock(); - qemu_log("IN: %s\n", lookup_symbol(ctx.base.pc_first)); - log_target_disas(cs, ctx.base.pc_first, - ctx.base.pc_next - ctx.base.pc_first); - qemu_log("\n"); - qemu_log_unlock(); - } -#endif +void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) +{ + DisasContext ctx; + + translator_loop(&ppc_tr_ops, &ctx.base, cs, tb); } =20 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, --=20 2.7.4