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X-Received-From: 2a00:1450:400c:c09::241 Subject: [Qemu-devel] [PULL 31/48] sdhci: rename the hostctl1 register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Philippe Mathieu-Daud=C3=A9 As per the Spec v3.00 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Message-Id: <20180208164818.7961-19-f4bug@amsat.org> --- hw/sd/sdhci.c | 42 +++++++++++++++++++++--------------------- include/hw/sd/sdhci.h | 2 +- 2 files changed, 22 insertions(+), 22 deletions(-) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 844c5d5..55b3f3a 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -691,7 +691,7 @@ static void get_adma_description(SDHCIState *s, ADMADes= cr *dscr) uint32_t adma1 =3D 0; uint64_t adma2 =3D 0; hwaddr entry_addr =3D (hwaddr)s->admasysaddr; - switch (SDHC_DMA_TYPE(s->hostctl)) { + switch (SDHC_DMA_TYPE(s->hostctl1)) { case SDHC_CTRL_ADMA2_32: dma_memory_read(s->dma_as, entry_addr, (uint8_t *)&adma2, sizeof(adma2)); @@ -880,7 +880,7 @@ static void sdhci_data_transfer(void *opaque) SDHCIState *s =3D (SDHCIState *)opaque; =20 if (s->trnmod & SDHC_TRNS_DMA) { - switch (SDHC_DMA_TYPE(s->hostctl)) { + switch (SDHC_DMA_TYPE(s->hostctl1)) { case SDHC_CTRL_SDMA: if ((s->blkcnt =3D=3D 1) || !(s->trnmod & SDHC_TRNS_MULTI)) { sdhci_sdma_transfer_single_block(s); @@ -989,7 +989,7 @@ static uint64_t sdhci_read(void *opaque, hwaddr offset,= unsigned size) ret =3D s->prnsts; break; case SDHC_HOSTCTL: - ret =3D s->hostctl | (s->pwrcon << 8) | (s->blkgap << 16) | + ret =3D s->hostctl1 | (s->pwrcon << 8) | (s->blkgap << 16) | (s->wakcon << 24); break; case SDHC_CLKCON: @@ -1107,7 +1107,7 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val= , unsigned size) MASKED_WRITE(s->sdmasysad, mask, value); /* Writing to last byte of sdmasysad might trigger transfer */ if (!(mask & 0xFF000000) && TRANSFERRING_DATA(s->prnsts) && s->blk= cnt && - s->blksize && SDHC_DMA_TYPE(s->hostctl) =3D=3D SDHC_CTRL_S= DMA) { + s->blksize && SDHC_DMA_TYPE(s->hostctl1) =3D=3D SDHC_CTRL_= SDMA) { if (s->trnmod & SDHC_TRNS_MULTI) { sdhci_sdma_transfer_multi_blocks(s); } else { @@ -1159,7 +1159,7 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val= , unsigned size) if (!(mask & 0xFF0000)) { sdhci_blkgap_write(s, value >> 16); } - MASKED_WRITE(s->hostctl, mask, value); + MASKED_WRITE(s->hostctl1, mask, value); MASKED_WRITE(s->pwrcon, mask >> 8, value >> 8); MASKED_WRITE(s->wakcon, mask >> 24, value >> 24); if (!(s->prnsts & SDHC_CARD_PRESENT) || ((s->pwrcon >> 1) & 0x7) <= 5 || @@ -1380,7 +1380,7 @@ const VMStateDescription sdhci_vmstate =3D { VMSTATE_UINT16(cmdreg, SDHCIState), VMSTATE_UINT32_ARRAY(rspreg, SDHCIState, 4), VMSTATE_UINT32(prnsts, SDHCIState), - VMSTATE_UINT8(hostctl, SDHCIState), + VMSTATE_UINT8(hostctl1, SDHCIState), VMSTATE_UINT8(pwrcon, SDHCIState), VMSTATE_UINT8(blkgap, SDHCIState), VMSTATE_UINT8(wakcon, SDHCIState), @@ -1586,7 +1586,7 @@ static uint64_t usdhc_read(void *opaque, hwaddr offse= t, unsigned size) { SDHCIState *s =3D SYSBUS_SDHCI(opaque); uint32_t ret; - uint16_t hostctl; + uint16_t hostctl1; =20 switch (offset) { default: @@ -1598,17 +1598,17 @@ static uint64_t usdhc_read(void *opaque, hwaddr off= set, unsigned size) * manipulation code see comments in a similar part of * usdhc_write() */ - hostctl =3D SDHC_DMA_TYPE(s->hostctl) << (8 - 3); + hostctl1 =3D SDHC_DMA_TYPE(s->hostctl1) << (8 - 3); =20 - if (s->hostctl & SDHC_CTRL_8BITBUS) { - hostctl |=3D ESDHC_CTRL_8BITBUS; + if (s->hostctl1 & SDHC_CTRL_8BITBUS) { + hostctl1 |=3D ESDHC_CTRL_8BITBUS; } =20 - if (s->hostctl & SDHC_CTRL_4BITBUS) { - hostctl |=3D ESDHC_CTRL_4BITBUS; + if (s->hostctl1 & SDHC_CTRL_4BITBUS) { + hostctl1 |=3D ESDHC_CTRL_4BITBUS; } =20 - ret =3D hostctl; + ret =3D hostctl1; ret |=3D (uint32_t)s->blkgap << 16; ret |=3D (uint32_t)s->wakcon << 24; =20 @@ -1632,7 +1632,7 @@ static void usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) { SDHCIState *s =3D SYSBUS_SDHCI(opaque); - uint8_t hostctl; + uint8_t hostctl1; uint32_t value =3D (uint32_t)val; =20 switch (offset) { @@ -1695,25 +1695,25 @@ usdhc_write(void *opaque, hwaddr offset, uint64_t v= al, unsigned size) /* * First, save bits 7 6 and 0 since they are identical */ - hostctl =3D value & (SDHC_CTRL_LED | - SDHC_CTRL_CDTEST_INS | - SDHC_CTRL_CDTEST_EN); + hostctl1 =3D value & (SDHC_CTRL_LED | + SDHC_CTRL_CDTEST_INS | + SDHC_CTRL_CDTEST_EN); /* * Second, split "Data Transfer Width" from bits 2 and 1 in to * bits 5 and 1 */ if (value & ESDHC_CTRL_8BITBUS) { - hostctl |=3D SDHC_CTRL_8BITBUS; + hostctl1 |=3D SDHC_CTRL_8BITBUS; } =20 if (value & ESDHC_CTRL_4BITBUS) { - hostctl |=3D ESDHC_CTRL_4BITBUS; + hostctl1 |=3D ESDHC_CTRL_4BITBUS; } =20 /* * Third, move DMA select from bits 9 and 8 to bits 4 and 3 */ - hostctl |=3D SDHC_DMA_TYPE(value >> (8 - 3)); + hostctl1 |=3D SDHC_DMA_TYPE(value >> (8 - 3)); =20 /* * Now place the corrected value into low 16-bit of the value @@ -1724,7 +1724,7 @@ usdhc_write(void *opaque, hwaddr offset, uint64_t val= , unsigned size) * kernel */ value &=3D ~UINT16_MAX; - value |=3D hostctl; + value |=3D hostctl1; value |=3D (uint16_t)s->pwrcon << 8; =20 sdhci_write(opaque, offset, value, size); diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index 2a26b46..5459484 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -59,7 +59,7 @@ typedef struct SDHCIState { uint16_t cmdreg; /* Command Register */ uint32_t rspreg[4]; /* Response Registers 0-3 */ uint32_t prnsts; /* Present State Register */ - uint8_t hostctl; /* Host Control Register */ + uint8_t hostctl1; /* Host Control Register */ uint8_t pwrcon; /* Power control Register */ uint8_t blkgap; /* Block Gap Control Register */ uint8_t wakcon; /* WakeUp Control Register */ --=20 1.8.3.1