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[125.237.39.90]) by smtp.gmail.com with ESMTPSA id k3sm5097653pff.41.2018.02.07.17.31.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 07 Feb 2018 17:31:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bUmoRH4TMHNKhKU9PUuJjuiGAS4pwabFq3FzTmc5PpM=; b=joyu6KiMkOioBQRtpU3G2h1cHIbwdWemY0ohX7priEs+ZnPwz+wXZpvcIOmlOS5RlZ 5mrI640WpYEE2F/PXatccNFW2M1gOfJpe+StSe89X1Y09fkHOartYKXs8B0rdqq8V9b3 +F2TI5vL4Q9LbyQCYcG7CeB6OVwz59C0h7H4TcHL4F8tgxLZvS1YXAeuokls/8phrsqQ vsrVSTgMyXh82rspO3kTAbntK77isjCwoAvAKELVizTgCj0MNkTvHefjVL+4ickOMdxt xB4rzIk9uVH0cpTdg/dOZmTqcFkRLi0xtR4myd941k71C9Lyn2Xctc33mtlSIMryoRk0 XaFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bUmoRH4TMHNKhKU9PUuJjuiGAS4pwabFq3FzTmc5PpM=; b=QvEWKLujWOnrbV+yD/D0xv97VgKXOLPmGMg1DEsEMRR5go7M6yfSLm8onm3uRDQZzI 0WrQ5WEAxLlW7U8Mm1VRCP078Kw7wEZWMZvDeLUa/JZsoGEBLMtO2fxXN4lQaQnoZK3u BIZkahVVfxYk79i0DnIkUc4MrBrgdNcMmXAhjfmN49JkY8XQgVYYflCiK2+P1PN86Esi 07etqtjSXNLXTDd3r7C6kYSXSLZC+3+O/kiCZmmG23Wtcy3mSAe5x/27nSusvN4pjGhh yAYdJTVeLmK71KhWQGwyYdLjbLvsQ6l4OdIsngdQhc/ig4b5wUgMYdVe9XH70tH9Pn4R XZ/A== X-Gm-Message-State: APf1xPATWtx/lmTLLG4vlXyZFZhBHzir5V+5oFofOCPEgc8e+Lxa5AzJ D3ws0Zvz7FSbIGbEjiqYV9OzANUSEDk= X-Google-Smtp-Source: AH8x225otKcENMWcBiaZYStKDOsfCqhkjKWf2qj41m5ZisaqCjODJSZNV1cl3P+3deC+KQSyyKYWkQ== X-Received: by 10.101.101.19 with SMTP id x19mr6650674pgv.347.1518053486901; Wed, 07 Feb 2018 17:31:26 -0800 (PST) From: Michael Clark To: qemu-devel@nongnu.org Date: Thu, 8 Feb 2018 14:28:45 +1300 Message-Id: <1518053328-34687-21-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1518053328-34687-1-git-send-email-mjc@sifive.com> References: <1518053328-34687-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v5 20/23] SiFive RISC-V Test Finisher X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Michael Clark , Palmer Dabbelt , Sagar Karandikar , RISC-V Patches Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Test finisher memory mapped device used to exit simulation. Signed-off-by: Michael Clark --- hw/riscv/sifive_test.c | 99 ++++++++++++++++++++++++++++++++++++++= ++++ include/hw/riscv/sifive_test.h | 48 ++++++++++++++++++++ 2 files changed, 147 insertions(+) create mode 100644 hw/riscv/sifive_test.c create mode 100644 include/hw/riscv/sifive_test.h diff --git a/hw/riscv/sifive_test.c b/hw/riscv/sifive_test.c new file mode 100644 index 0000000..9696f15 --- /dev/null +++ b/hw/riscv/sifive_test.c @@ -0,0 +1,99 @@ +/* + * QEMU SiFive Test Finisher + * + * Copyright (c) 2018 SiFive, Inc. + * + * Test finisher memory mapped device used to exit simulation + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "target/riscv/cpu.h" +#include "hw/riscv/sifive_test.h" + +static uint64_t sifive_test_read(void *opaque, hwaddr addr, unsigned int s= ize) +{ + return 0; +} + +static void sifive_test_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + if (addr =3D=3D 0) { + int status =3D val64 & 0xffff; + int code =3D (val64 >> 16) & 0xffff; + switch (status) { + case FINISHER_FAIL: + exit(code); + case FINISHER_PASS: + exit(0); + default: + break; + } + } + hw_error("%s: write: addr=3D0x%x val=3D0x%016" PRIx64 "\n", + __func__, (int)addr, val64); +} + +static const MemoryRegionOps sifive_test_ops =3D { + .read =3D sifive_test_read, + .write =3D sifive_test_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4 + } +}; + +static void sifive_test_init(Object *obj) +{ + SiFiveTestState *s =3D SIFIVE_TEST(obj); + + memory_region_init_io(&s->mmio, obj, &sifive_test_ops, s, + TYPE_SIFIVE_TEST, 0x1000); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); +} + +static const TypeInfo sifive_test_info =3D { + .name =3D TYPE_SIFIVE_TEST, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(SiFiveTestState), + .instance_init =3D sifive_test_init, +}; + +static void sifive_test_register_types(void) +{ + type_register_static(&sifive_test_info); +} + +type_init(sifive_test_register_types) + + +/* + * Create Test device. + */ +DeviceState *sifive_test_create(hwaddr addr) +{ + DeviceState *dev =3D qdev_create(NULL, TYPE_SIFIVE_TEST); + qdev_init_nofail(dev); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); + return dev; +} diff --git a/include/hw/riscv/sifive_test.h b/include/hw/riscv/sifive_test.h new file mode 100644 index 0000000..6a0f5bb --- /dev/null +++ b/include/hw/riscv/sifive_test.h @@ -0,0 +1,48 @@ +/* + * QEMU Test Finisher interface + * + * Copyright (c) 2018 SiFive, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef HW_SIFIVE_TEST_H +#define HW_SIFIVE_TEST_H + +#define TYPE_SIFIVE_TEST "riscv.sifive.test" + +#define SIFIVE_TEST(obj) \ + OBJECT_CHECK(SiFiveTestState, (obj), TYPE_SIFIVE_TEST) + +typedef struct SiFiveTestState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion mmio; +} SiFiveTestState; + +enum { + FINISHER_FAIL =3D 0x3333, + FINISHER_PASS =3D 0x5555 +}; + +DeviceState *sifive_test_create(hwaddr addr); + +#endif --=20 2.7.0