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[125.237.39.90]) by smtp.gmail.com with ESMTPSA id k3sm5097653pff.41.2018.02.07.17.31.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 07 Feb 2018 17:31:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=56A1LJg4VroFoLhnzCj7naKQYi7Vb05jdaG/l/TYjhU=; b=nputidmWS3YUbwZlxqalThJMZ9hvJiORqt4f3EEPj9X13HhmZZ21mw4I3eqapLQr4i c9L+D1kgd1QXJ3M/sKAARdA2wly/aPtjqrEUse774sTPmv02Y4/BoNCEU/u2koKubcxY SGxlyDyec+EsFl0qEJG3rpDxAiHMeO3sCHjIm93Lzt099w0bVp93b/FOqkL8iqWJRBOX urO7ZYD5F7oe3iuxNqC7vGp+bEyo2mdtuvGvO4cbVkRbP62M0T6FF0RVi2hVwRrA0J84 hvIpHJqB/A2ViBLGK30AkPEz8IQ0M+lrg3aREEIgsVfVMUYU3K7t0ViRFIidp0EBsG+1 uE1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=56A1LJg4VroFoLhnzCj7naKQYi7Vb05jdaG/l/TYjhU=; b=Sx9kE0ST5s76PviSmTj/DcuAf0aiNbiFzNAceSgxNoFyOfRmfePZXWl7ItR2laoPgs N0axfEJOxdwl129W0/d8XWHzxD6Cg6qBq4xvZoH45mgCZie+gXxbuMgwQpWeZuuzLi// F0PVsis66lWsFO/spTpb7i96bIzIX9fEshIww60swzvZ5jlGNydogsz7GUpCHNSu2peD PtfejbLb9JWutct6wC+XycjIKu05gXqAQ/fNrqz4Yvt6Tf6H0VLbk9EWW+V37PWgeN3i BOT/SthMQa/7wYo5vBfD+oH5GYS/dsrV34+tq4juFa39HPQaCI2EzBhv/OJH78b/vlmU oQBg== X-Gm-Message-State: APf1xPCQKPeMEnoeiHOqhAywsrEqqU6rZfOoE8a9HDMRy7RorvJKsagg 0F2v54ikAqE9ICE2rzoc98Pt/q0jsZc= X-Google-Smtp-Source: AH8x2253LL3SJ7tfg/ni7EdllAuXK/iZaUV6yYMIYajvTk7AFjZK/d3awKkJI5Mv4y8TLLgfTiXMuw== X-Received: by 2002:a17:902:7d8b:: with SMTP id a11-v6mr7781237plm.216.1518053483052; Wed, 07 Feb 2018 17:31:23 -0800 (PST) From: Michael Clark To: qemu-devel@nongnu.org Date: Thu, 8 Feb 2018 14:28:44 +1300 Message-Id: <1518053328-34687-20-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1518053328-34687-1-git-send-email-mjc@sifive.com> References: <1518053328-34687-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PATCH v5 19/23] SiFive RISC-V PRCI Block X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Michael Clark , Palmer Dabbelt , Sagar Karandikar , RISC-V Patches Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Simple model of the PRCI (Power, Reset, Clock, Interrupt) to emulate register reads made by the SDK BSP. Signed-off-by: Michael Clark --- hw/riscv/sifive_prci.c | 95 ++++++++++++++++++++++++++++++++++++++= ++++ include/hw/riscv/sifive_prci.h | 43 +++++++++++++++++++ 2 files changed, 138 insertions(+) create mode 100644 hw/riscv/sifive_prci.c create mode 100644 include/hw/riscv/sifive_prci.h diff --git a/hw/riscv/sifive_prci.c b/hw/riscv/sifive_prci.c new file mode 100644 index 0000000..fc19089 --- /dev/null +++ b/hw/riscv/sifive_prci.c @@ -0,0 +1,95 @@ +/* + * QEMU SiFive PRCI (Power, Reset, Clock, Interrupt) + * + * Copyright (c) 2017 SiFive, Inc. + * + * Simple model of the PRCI to emulate register reads made by the SDK BSP + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "target/riscv/cpu.h" +#include "hw/riscv/sifive_prci.h" + +/* currently implements enough to mock freedom-e-sdk BSP clock programming= */ + +static uint64_t sifive_prci_read(void *opaque, hwaddr addr, unsigned int s= ize) +{ + if (addr =3D=3D 0 /* PRCI_HFROSCCFG */) { + return 1 << 31; /* ROSC_RDY */ + } + if (addr =3D=3D 8 /* PRCI_PLLCFG */) { + return 1 << 31; /* PLL_LOCK */ + } + hw_error("%s: read: addr=3D0x%x\n", __func__, (int)addr); + return 0; +} + +static void sifive_prci_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + /* discard writes */ +} + +static const MemoryRegionOps sifive_prci_ops =3D { + .read =3D sifive_prci_read, + .write =3D sifive_prci_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4 + } +}; + +static void sifive_prci_init(Object *obj) +{ + SiFivePRCIState *s =3D SIFIVE_PRCI(obj); + + memory_region_init_io(&s->mmio, obj, &sifive_prci_ops, s, + TYPE_SIFIVE_PRCI, 0x8000); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); +} + +static const TypeInfo sifive_prci_info =3D { + .name =3D TYPE_SIFIVE_PRCI, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(SiFivePRCIState), + .instance_init =3D sifive_prci_init, +}; + +static void sifive_prci_register_types(void) +{ + type_register_static(&sifive_prci_info); +} + +type_init(sifive_prci_register_types) + + +/* + * Create PRCI device. + */ +DeviceState *sifive_prci_create(hwaddr addr) +{ + DeviceState *dev =3D qdev_create(NULL, TYPE_SIFIVE_PRCI); + qdev_init_nofail(dev); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); + return dev; +} diff --git a/include/hw/riscv/sifive_prci.h b/include/hw/riscv/sifive_prci.h new file mode 100644 index 0000000..0e032e5 --- /dev/null +++ b/include/hw/riscv/sifive_prci.h @@ -0,0 +1,43 @@ +/* + * QEMU SiFive PRCI (Power, Reset, Clock, Interrupt) interface + * + * Copyright (c) 2017 SiFive, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef HW_SIFIVE_PRCI_H +#define HW_SIFIVE_PRCI_H + +#define TYPE_SIFIVE_PRCI "riscv.sifive.prci" + +#define SIFIVE_PRCI(obj) \ + OBJECT_CHECK(SiFivePRCIState, (obj), TYPE_SIFIVE_PRCI) + +typedef struct SiFivePRCIState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion mmio; +} SiFivePRCIState; + +DeviceState *sifive_prci_create(hwaddr addr); + +#endif --=20 2.7.0