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X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 12/21] target/arm: Hoist store to flags output in cpu_get_tb_cpu_state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 From: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20180119045438.28582-15-richard.henderson@linaro.org Reviewed-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Peter Maydell --- target/arm/helper.c | 35 +++++++++++++++++++---------------- 1 file changed, 19 insertions(+), 16 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 1e64bb9..e0c139d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11688,34 +11688,36 @@ static inline int fp_exception_el(CPUARMState *en= v) } =20 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, - target_ulong *cs_base, uint32_t *flags) + target_ulong *cs_base, uint32_t *pflags) { ARMMMUIdx mmu_idx =3D core_to_arm_mmu_idx(env, cpu_mmu_index(env, fals= e)); + uint32_t flags; + if (is_a64(env)) { *pc =3D env->pc; - *flags =3D ARM_TBFLAG_AARCH64_STATE_MASK; + flags =3D ARM_TBFLAG_AARCH64_STATE_MASK; /* Get control bits for tagged addresses */ - *flags |=3D (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIF= T); - *flags |=3D (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIF= T); + flags |=3D (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIFT= ); + flags |=3D (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIFT= ); } else { *pc =3D env->regs[15]; - *flags =3D (env->thumb << ARM_TBFLAG_THUMB_SHIFT) + flags =3D (env->thumb << ARM_TBFLAG_THUMB_SHIFT) | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT) | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT) | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT) | (arm_sctlr_b(env) << ARM_TBFLAG_SCTLR_B_SHIFT); if (!(access_secure_reg(env))) { - *flags |=3D ARM_TBFLAG_NS_MASK; + flags |=3D ARM_TBFLAG_NS_MASK; } if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) || arm_el_is_aa64(env, 1)) { - *flags |=3D ARM_TBFLAG_VFPEN_MASK; + flags |=3D ARM_TBFLAG_VFPEN_MASK; } - *flags |=3D (extract32(env->cp15.c15_cpar, 0, 2) - << ARM_TBFLAG_XSCALE_CPAR_SHIFT); + flags |=3D (extract32(env->cp15.c15_cpar, 0, 2) + << ARM_TBFLAG_XSCALE_CPAR_SHIFT); } =20 - *flags |=3D (arm_to_core_mmu_idx(mmu_idx) << ARM_TBFLAG_MMUIDX_SHIFT); + flags |=3D (arm_to_core_mmu_idx(mmu_idx) << ARM_TBFLAG_MMUIDX_SHIFT); =20 /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine * states defined in the ARM ARM for software singlestep: @@ -11725,25 +11727,26 @@ void cpu_get_tb_cpu_state(CPUARMState *env, targe= t_ulong *pc, * 1 1 Active-not-pending */ if (arm_singlestep_active(env)) { - *flags |=3D ARM_TBFLAG_SS_ACTIVE_MASK; + flags |=3D ARM_TBFLAG_SS_ACTIVE_MASK; if (is_a64(env)) { if (env->pstate & PSTATE_SS) { - *flags |=3D ARM_TBFLAG_PSTATE_SS_MASK; + flags |=3D ARM_TBFLAG_PSTATE_SS_MASK; } } else { if (env->uncached_cpsr & PSTATE_SS) { - *flags |=3D ARM_TBFLAG_PSTATE_SS_MASK; + flags |=3D ARM_TBFLAG_PSTATE_SS_MASK; } } } if (arm_cpu_data_is_big_endian(env)) { - *flags |=3D ARM_TBFLAG_BE_DATA_MASK; + flags |=3D ARM_TBFLAG_BE_DATA_MASK; } - *flags |=3D fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT; + flags |=3D fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT; =20 if (arm_v7m_is_handler_mode(env)) { - *flags |=3D ARM_TBFLAG_HANDLER_MASK; + flags |=3D ARM_TBFLAG_HANDLER_MASK; } =20 + *pflags =3D flags; *cs_base =3D 0; } --=20 2.7.4