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[78.12.229.84]) by smtp.gmail.com with ESMTPSA id u10sm1537758wrg.6.2018.01.16.06.17.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 16 Jan 2018 06:17:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=dJpVhCyBEhB4PzFsnZCeRSMC+Jtbthdz5umfkprMfgQ=; b=p7b3HRWFN5lCC8kzSiZmgVX2oue706QOfSWjwkGjMJ3Z/zjl+gAI0KyWWBROGjeowg ubn5KRJRYsl8mmK+Jrt1WpfqvIRsHR3Rym9KYc+P/mbmMP5o3YhYer+mQqGCcSRdROrL 4IGbBdOGBkBjFspSM98kXKzO11voL7pcRQ55vvur6hDs06h1xv4Ig3HBZz/+MJOb8/9F Ymm3t4e5VJasfoYTqqH7GZRxRXK4JiSZfJL6UYqbW0gS26C0252KI/l5LjDKbUr/KdfE r+F9sygnpKfKd2E9+MKXpaVCuJyaIgGrAs1sxZnkyUpc2Bmmwq16/G89u94W6e63bswN tDDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=dJpVhCyBEhB4PzFsnZCeRSMC+Jtbthdz5umfkprMfgQ=; b=BrO46evSyMCuo29qqPFmnCplVH8UWrbDmTtnR5WlsLelNZ48kFfygPGyeh0Sw8DQ6r ziq4AlSNQgcvciuv65hDW+V5bfPgMqNYO1XXtF2SxHpmi7aq/s7foi3UmVwG6M3CL4+l 5fnKq4NOjiuyibE9UGacswySWT7n64tZOFQ6/Ia1kVBoglqvVgwL7g7LFtrcY5vGSgvM UpEjyKHGS93ZqCMFUtQjqJcnEO4kvxuFcuoY2faPGQcjORo1+KudeaYhT00E2uiPoAL1 8wzpbCN0vQzySDkJd/VzrmSFHDEwJdxvfA/6oqpajjMYWGbJiS0zYsSAbQ/RLNv7iFEl DEoA== X-Gm-Message-State: AKGB3mLcL9UhALxJk0W83Jk2oyku2Znmbmwb9yDmoG38FGPYVHN8jbID GFe8oYhDaU/qBmeGweduCYE1xJZ4 X-Google-Smtp-Source: ACJfBovTofaepyYoDm75abwL2Ci+65QaWp+EXR9w5FYe/j0WUevGbla9lAPOse+tUGhgJe6pM3/58A== X-Received: by 10.223.135.115 with SMTP id 48mr25798441wrz.122.1516112265104; Tue, 16 Jan 2018 06:17:45 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Tue, 16 Jan 2018 15:16:47 +0100 Message-Id: <1516112253-14480-6-git-send-email-pbonzini@redhat.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1516112253-14480-1-git-send-email-pbonzini@redhat.com> References: <1516112253-14480-1-git-send-email-pbonzini@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::241 Subject: [Qemu-devel] [PULL 05/51] i386/cpu/kvm: look at PMU's CPUID before setting MSRs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jan Dakinevich Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Jan Dakinevich Certain PMU-related MSRs are not supported for CPUs with PMU architecture below version 2. KVM rejects any access to them (see intel_is_valid_msr_idx routine in KVM), and QEMU fails on the following assertion: kvm_put_msrs: Assertion `ret =3D=3D cpu->kvm_msr_buf->nmsrs' failed. QEMU also could fail if KVM exposes less fixed counters then 3. It could happen if host system run inside another hypervisor, which is tweaking PMU-related CPUID. To prevent possible fail, number of fixed counters now is obtained in the same way as number of GP counters. Reviewed-by: Roman Kagan Signed-off-by: Jan Dakinevich Message-Id: <1514383466-7257-1-git-send-email-jan.dakinevich@virtuozzo.com> Signed-off-by: Paolo Bonzini --- target/i386/kvm.c | 80 +++++++++++++++++++++++++++++++++------------------= ---- 1 file changed, 48 insertions(+), 32 deletions(-) diff --git a/target/i386/kvm.c b/target/i386/kvm.c index 6f69e2f..d23127c 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -92,8 +92,9 @@ static bool has_msr_hv_stimer; static bool has_msr_hv_frequencies; static bool has_msr_xss; =20 -static bool has_msr_architectural_pmu; -static uint32_t num_architectural_pmu_counters; +static uint32_t has_architectural_pmu_version; +static uint32_t num_architectural_pmu_gp_counters; +static uint32_t num_architectural_pmu_fixed_counters; =20 static int has_xsave; static int has_xcrs; @@ -872,19 +873,28 @@ int kvm_arch_init_vcpu(CPUState *cs) } =20 if (limit >=3D 0x0a) { - uint32_t ver; + uint32_t eax, edx; =20 - cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused); - if ((ver & 0xff) > 0) { - has_msr_architectural_pmu =3D true; - num_architectural_pmu_counters =3D (ver & 0xff00) >> 8; + cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx); + + has_architectural_pmu_version =3D eax & 0xff; + if (has_architectural_pmu_version > 0) { + num_architectural_pmu_gp_counters =3D (eax & 0xff00) >> 8; =20 /* Shouldn't be more than 32, since that's the number of bits * available in EBX to tell us _which_ counters are available. * Play it safe. */ - if (num_architectural_pmu_counters > MAX_GP_COUNTERS) { - num_architectural_pmu_counters =3D MAX_GP_COUNTERS; + if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) { + num_architectural_pmu_gp_counters =3D MAX_GP_COUNTERS; + } + + if (has_architectural_pmu_version > 1) { + num_architectural_pmu_fixed_counters =3D edx & 0x1f; + + if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNT= ERS) { + num_architectural_pmu_fixed_counters =3D MAX_FIXED_COU= NTERS; + } } } } @@ -1650,32 +1660,36 @@ static int kvm_put_msrs(X86CPU *cpu, int level) if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) { kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr= ); } - if (has_msr_architectural_pmu) { - /* Stop the counter. */ - kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0); - kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0); + if (has_architectural_pmu_version > 0) { + if (has_architectural_pmu_version > 1) { + /* Stop the counter. */ + kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0); + kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0); + } =20 /* Set the counter values. */ - for (i =3D 0; i < MAX_FIXED_COUNTERS; i++) { + for (i =3D 0; i < num_architectural_pmu_fixed_counters; i++) { kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, env->msr_fixed_counters[i]); } - for (i =3D 0; i < num_architectural_pmu_counters; i++) { + for (i =3D 0; i < num_architectural_pmu_gp_counters; i++) { kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, env->msr_gp_counters[i]); kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, env->msr_gp_evtsel[i]); } - kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, - env->msr_global_status); - kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, - env->msr_global_ovf_ctrl); - - /* Now start the PMU. */ - kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, - env->msr_fixed_ctr_ctrl); - kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, - env->msr_global_ctrl); + if (has_architectural_pmu_version > 1) { + kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, + env->msr_global_status); + kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, + env->msr_global_ovf_ctrl); + + /* Now start the PMU. */ + kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, + env->msr_fixed_ctr_ctrl); + kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, + env->msr_global_ctrl); + } } /* * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-= add, @@ -2030,15 +2044,17 @@ static int kvm_get_msrs(X86CPU *cpu) if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) { kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0); } - if (has_msr_architectural_pmu) { - kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0); - kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0); - kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0); - kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0); - for (i =3D 0; i < MAX_FIXED_COUNTERS; i++) { + if (has_architectural_pmu_version > 0) { + if (has_architectural_pmu_version > 1) { + kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0); + kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0); + kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0); + kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0); + } + for (i =3D 0; i < num_architectural_pmu_fixed_counters; i++) { kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0); } - for (i =3D 0; i < num_architectural_pmu_counters; i++) { + for (i =3D 0; i < num_architectural_pmu_gp_counters; i++) { kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0); kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0); } --=20 1.8.3.1