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X-Received-From: 2a00:1450:400c:c0c::244 Subject: [Qemu-devel] [PULL 29/51] target/i386: move hflags update code to a function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tao Wu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Tao Wu We will share the same code for hax/kvm. Signed-off-by: Tao Wu Message-Id: <20180110195056.85403-1-lepton@google.com> Signed-off-by: Paolo Bonzini --- target/i386/cpu.c | 42 ++++++++++++++++++++++++++++++++++++++++++ target/i386/cpu.h | 2 ++ target/i386/kvm.c | 40 +--------------------------------------- 3 files changed, 45 insertions(+), 39 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 3818d72..ad8196b 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4147,6 +4147,48 @@ static void x86_disas_set_info(CPUState *cs, disasse= mble_info *info) info->cap_insn_split =3D 8; } =20 +void x86_update_hflags(CPUX86State *env) +{ + uint32_t hflags; +#define HFLAG_COPY_MASK \ + ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ + HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ + HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ + HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) + + hflags =3D env->hflags & HFLAG_COPY_MASK; + hflags |=3D (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; + hflags |=3D (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); + hflags |=3D (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & + (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); + hflags |=3D (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); + + if (env->cr[4] & CR4_OSFXSR_MASK) { + hflags |=3D HF_OSFXSR_MASK; + } + + if (env->efer & MSR_EFER_LMA) { + hflags |=3D HF_LMA_MASK; + } + + if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { + hflags |=3D HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; + } else { + hflags |=3D (env->segs[R_CS].flags & DESC_B_MASK) >> + (DESC_B_SHIFT - HF_CS32_SHIFT); + hflags |=3D (env->segs[R_SS].flags & DESC_B_MASK) >> + (DESC_B_SHIFT - HF_SS32_SHIFT); + if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || + !(hflags & HF_CS32_MASK)) { + hflags |=3D HF_ADDSEG_MASK; + } else { + hflags |=3D ((env->segs[R_DS].base | env->segs[R_ES].base | + env->segs[R_SS].base) !=3D 0) << HF_ADDSEG_SHIFT; + } + } + env->hflags =3D hflags; +} + static Property x86_cpu_properties[] =3D { #ifdef CONFIG_USER_ONLY /* apic_id =3D 0 by default for *-user, see commit 9886e834 */ diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 62c4742..f64e5ed 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1778,4 +1778,6 @@ bool cpu_is_bsp(X86CPU *cpu); =20 void x86_cpu_xrstor_all_areas(X86CPU *cpu, const X86XSaveArea *buf); void x86_cpu_xsave_all_areas(X86CPU *cpu, X86XSaveArea *buf); +void x86_update_hflags(CPUX86State* env); + #endif /* I386_CPU_H */ diff --git a/target/i386/kvm.c b/target/i386/kvm.c index d23127c..825aea5 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -1891,7 +1891,6 @@ static int kvm_get_sregs(X86CPU *cpu) { CPUX86State *env =3D &cpu->env; struct kvm_sregs sregs; - uint32_t hflags; int bit, i, ret; =20 ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs); @@ -1933,44 +1932,7 @@ static int kvm_get_sregs(X86CPU *cpu) env->efer =3D sregs.efer; =20 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_ru= n */ - -#define HFLAG_COPY_MASK \ - ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ - HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ - HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ - HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) - - hflags =3D env->hflags & HFLAG_COPY_MASK; - hflags |=3D (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; - hflags |=3D (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); - hflags |=3D (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & - (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); - hflags |=3D (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); - - if (env->cr[4] & CR4_OSFXSR_MASK) { - hflags |=3D HF_OSFXSR_MASK; - } - - if (env->efer & MSR_EFER_LMA) { - hflags |=3D HF_LMA_MASK; - } - - if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { - hflags |=3D HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; - } else { - hflags |=3D (env->segs[R_CS].flags & DESC_B_MASK) >> - (DESC_B_SHIFT - HF_CS32_SHIFT); - hflags |=3D (env->segs[R_SS].flags & DESC_B_MASK) >> - (DESC_B_SHIFT - HF_SS32_SHIFT); - if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || - !(hflags & HF_CS32_MASK)) { - hflags |=3D HF_ADDSEG_MASK; - } else { - hflags |=3D ((env->segs[R_DS].base | env->segs[R_ES].base | - env->segs[R_SS].base) !=3D 0) << HF_ADDSEG_SHIFT; - } - } - env->hflags =3D hflags; + x86_update_hflags(env); =20 return 0; } --=20 1.8.3.1