From nobody Tue Feb 10 07:41:13 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1515637551638612.8168623121883; Wed, 10 Jan 2018 18:25:51 -0800 (PST) Received: from localhost ([::1]:59907 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eZSYw-0004nH-Om for importer@patchew.org; Wed, 10 Jan 2018 21:25:50 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48098) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eZSWk-0003G8-Ki for qemu-devel@nongnu.org; Wed, 10 Jan 2018 21:23:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eZSWi-0008KS-H4 for qemu-devel@nongnu.org; Wed, 10 Jan 2018 21:23:34 -0500 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:41295) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eZSWi-0008K0-8b for qemu-devel@nongnu.org; Wed, 10 Jan 2018 21:23:32 -0500 Received: by mail-pg0-x242.google.com with SMTP id 136so1113344pgd.8 for ; Wed, 10 Jan 2018 18:23:32 -0800 (PST) Received: from monty.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id e12sm33545939pgu.81.2018.01.10.18.23.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 10 Jan 2018 18:23:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=43K0Q4QSORYmP58AF10p8wntW1hChB5IjoxynmABNT4=; b=Kz+OHJs5PQ7JxOp3Eq5/Rlc19paDel4MGZqlFqsul3bcgjgd1kTurtVaULZ8Ar0PPH NkQXqaQL/shj2i9+nSxtU+lc2SenQoPCTngoGbfK1edqTmMJ6G53L8JgaVdVEv8U6PY4 R2SpqokKKFka1Js8iOPEHtWTI6MtXOQiak1ngfwCLuQ4S5J1yUMTwg9slO8BatAMgnE4 K1YO72qFF2Q2/JHOzCypqDUr/2SvDl5wjJryEF3sZvtxurlKPKSvJgc3bRODMu0AjpSN zViavt3qbv5k/3Z9GIAO2huPl1h9ORvbF44e6o+2iDTyj/Mk4FoeaEHjvk/BDSCg4SBP 5Htg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=43K0Q4QSORYmP58AF10p8wntW1hChB5IjoxynmABNT4=; b=JNlBM8h8hmqdNJBGhPSkKt8GJR29K6uMoP9Q48g9PwFFVmibrH0MdkfDiIWXtB7aIZ J9RH6LV/SCwvG65KGgUsVLECrNyIHKpotFjRKvvYEG4pGhHWCwdxgNwyOY5SxuyPser3 H6W+ZLRit8MqnUStrLtiiehxZSM6DRT5nNQ5YOc9Sv5UOZejmhzfxpdPOwFg4oB9FaSn Go7KjMKabQtfeY/flfcOq/2tlgzBH2I+CWrvnaqF+Wp1oxuCqORF2EMEDD1VNsxiEafa 3036YAhWgUQ10/lsfZ8h92qU0EWs7YuCsN9qiguRBcQDrez0bftzz98St7YeZSy+dBkl b9Dg== X-Gm-Message-State: AKGB3mLxYZDPEXoI0YB97lN0v1/p9RvOo4Li5O5zHWsxSeEBY6IQWdjw J1VYxIoQP8B/ji/6bnLdFHMjq7Af5k4= X-Google-Smtp-Source: ACJfBosPYoQRmK00FEjJQAKWYHZPnAZl3XE6BXWtx6ASKHzJh1ixBIAzy9x0HH0zoAIla5DXfLwVmA== X-Received: by 10.159.242.193 with SMTP id x1mr15597422plw.85.1515637411257; Wed, 10 Jan 2018 18:23:31 -0800 (PST) From: Michael Clark To: qemu-devel@nongnu.org Date: Wed, 10 Jan 2018 18:21:55 -0800 Message-Id: <1515637324-96034-13-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1515637324-96034-1-git-send-email-mjc@sifive.com> References: <1515637324-96034-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v3 12/21] RISC-V HART Array X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Michael Clark , Palmer Dabbelt , Sagar Karandikar , RISC-V Patches Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Holds the state of a heterogenous array of RISC-V hardware threads. Signed-off-by: Michael Clark --- hw/riscv/riscv_hart.c | 95 +++++++++++++++++++++++++++++++++++++++= ++++ include/hw/riscv/riscv_hart.h | 45 ++++++++++++++++++++ 2 files changed, 140 insertions(+) create mode 100644 hw/riscv/riscv_hart.c create mode 100644 include/hw/riscv/riscv_hart.h diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c new file mode 100644 index 0000000..a7e079e --- /dev/null +++ b/hw/riscv/riscv_hart.c @@ -0,0 +1,95 @@ +/* + * QEMU RISCV Hart Array + * + * Copyright (c) 2017 SiFive, Inc. + * + * Holds the state of a heterogenous array of RISC-V harts + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/sysbus.h" +#include "target/riscv/cpu.h" +#include "hw/riscv/riscv_hart.h" + +static Property riscv_harts_props[] =3D { + DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1), + DEFINE_PROP_STRING("cpu-model", RISCVHartArrayState, cpu_model), + DEFINE_PROP_END_OF_LIST(), +}; + +static void riscv_harts_cpu_reset(void *opaque) +{ + RISCVCPU *cpu =3D opaque; + cpu_reset(CPU(cpu)); +} + +static void riscv_harts_realize(DeviceState *dev, Error **errp) +{ + RISCVHartArrayState *s =3D RISCV_HART_ARRAY(dev); + Error *err =3D NULL; + int n; + + s->harts =3D g_new0(RISCVCPU, s->num_harts); + + for (n =3D 0; n < s->num_harts; n++) { + + object_initialize(&s->harts[n], sizeof(RISCVCPU), s->cpu_model); + s->harts[n].env.mhartid =3D n; + object_property_add_child(OBJECT(s), "harts[*]", OBJECT(&s->harts[= n]), + &error_abort); + qemu_register_reset(riscv_harts_cpu_reset, &s->harts[n]); + object_property_set_bool(OBJECT(&s->harts[n]), true, + "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + } +} + +static void riscv_harts_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->props =3D riscv_harts_props; + dc->realize =3D riscv_harts_realize; +} + +static void riscv_harts_init(Object *obj) +{ + /* RISCVHartArrayState *s =3D SIFIVE_COREPLEX(obj); */ +} + +static const TypeInfo riscv_harts_info =3D { + .name =3D TYPE_RISCV_HART_ARRAY, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(RISCVHartArrayState), + .instance_init =3D riscv_harts_init, + .class_init =3D riscv_harts_class_init, +}; + +static void riscv_harts_register_types(void) +{ + type_register_static(&riscv_harts_info); +} + +type_init(riscv_harts_register_types) diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h new file mode 100644 index 0000000..c45e987 --- /dev/null +++ b/include/hw/riscv/riscv_hart.h @@ -0,0 +1,45 @@ +/* + * QEMU RISC-V Hart Array interface + * + * Copyright (c) 2017 SiFive, Inc. + * + * Holds the state of a heterogenous array of RISC-V harts + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef HW_RISCV_HART_H +#define HW_RISCV_HART_H + +#define TYPE_RISCV_HART_ARRAY "riscv.hart_array" + +#define RISCV_HART_ARRAY(obj) \ + OBJECT_CHECK(RISCVHartArrayState, (obj), TYPE_RISCV_HART_ARRAY) + +typedef struct RISCVHartArrayState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + uint32_t num_harts; + char *cpu_model; + RISCVCPU *harts; +} RISCVHartArrayState; + +#endif --=20 2.7.0