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[125.237.39.90]) by smtp.gmail.com with ESMTPSA id 75sm97691351pfo.103.2018.01.02.16.47.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 02 Jan 2018 16:47:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=X2SeXt9Mxj2qFATHnXKZTeQ7o0Et5imgZ4hrm8nkPBU=; b=esRBIna3PUA0BrKb3q/gj6EBErLcpu7K+WPOfFR7ltiyy6X+XSHx80YI1p4Eulq9xp 29YPv+0pLE0ey+Sc38KsnaLPbkaMOUW+nDtlUoU5AfLfubXfVmU2t9LWKNNVVWXqgqTX bCCv8g7jEOyqn3+lGJhT8hNzsjotv/RZ+xyUm/iE9K3MlLeW8257zcFvb32YL/ltig7u oXgD93AeeYbnbG5DXo/EwIyu88fv1jHGrDMag8Ds/rwcBg+DXR3PXSYAzjVL6MlLRmf2 RTdTAW3K6gWr66fM7CIcHlK5lra9aeAxHh3TnjNLeiMr7Z8nz13XfPQVULcjPXK2kpTO BtuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=X2SeXt9Mxj2qFATHnXKZTeQ7o0Et5imgZ4hrm8nkPBU=; b=lzvK/0g//r+zRqk5ZGDVPop21JEP+r1IJGSYsi+6KSVKL09aorF3pnNwnImSUIBAO4 W/naE1HW9/lDaOjbAoF6SN83kBdjLwmOhh1daDtT3/qaGabMCG+wLGeUf3LyuT1x61AT PIcrR12VMH3QHAiM8XwhqGCU4JhI0PKHCdENHJSGWbxb49m4MmoWIOwty/jOxCtKZ2iR hyKklXDEF7hWq+Bqt0wpvR+75uYQzpBtaeHcMDFAlQkFx+kNErK3xo9sOfPeVjMNKO/2 W0+n62xRHRA6V6WVaGcDgDzhx+Z0HkwcENeuTRwqy/a/u9Od9cONaEzEll9FavMlmtMA IGaQ== X-Gm-Message-State: AKGB3mKJmW4WmEA1s78R2d7ArH3kr2aQZ1Uef8+nsMPzZ4EEQgKkJjIH 5NIcWskQTy4O4s5VtgGznx/qCr4GRnM= X-Google-Smtp-Source: ACJfBouIdNAfWqkGeHeZpD8e9KpXKgziqmrHrKpfDlU2I7whidPhigNyRxnBJVDQ+vitsQnV+L2J3A== X-Received: by 10.159.204.146 with SMTP id t18mr155107plo.236.1514940439943; Tue, 02 Jan 2018 16:47:19 -0800 (PST) From: Michael Clark To: qemu-devel@nongnu.org Date: Wed, 3 Jan 2018 13:44:25 +1300 Message-Id: <1514940265-18093-22-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1514940265-18093-1-git-send-email-mjc@sifive.com> References: <1514940265-18093-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH v1 21/21] RISC-V Build Infrastructure X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Michael Clark , Sagar Karandikar Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This adds RISC-V into the build system enabling the following targets: - riscv32-softmmu - riscv64-softmmu - riscv32-linux-user - riscv64-linux-user This adds defaults configs for RISC-V, enables the build for the RISC-V CPU core, hardware, and Linux User Emulation. The 'qemu-binfmt-conf.sh' script is updated to add the RISC-V ELF magic. Expected checkpatch errors for consistency reasons: ERROR: line over 90 characters FILE: scripts/qemu-binfmt-conf.sh Signed-off-by: Michael Clark --- Makefile.objs | 1 + arch_init.c | 2 ++ configure | 11 +++++++++++ cpus.c | 6 ++++++ default-configs/riscv32-linux-user.mak | 1 + default-configs/riscv32-softmmu.mak | 4 ++++ default-configs/riscv64-linux-user.mak | 1 + default-configs/riscv64-softmmu.mak | 4 ++++ hw/riscv/Makefile.objs | 12 ++++++++++++ include/sysemu/arch_init.h | 1 + qapi-schema.json | 14 +++++++++++++- scripts/qemu-binfmt-conf.sh | 13 ++++++++++++- target/riscv/Makefile.objs | 2 ++ target/riscv/trace-events | 1 + 14 files changed, 71 insertions(+), 2 deletions(-) create mode 100644 default-configs/riscv32-linux-user.mak create mode 100644 default-configs/riscv32-softmmu.mak create mode 100644 default-configs/riscv64-linux-user.mak create mode 100644 default-configs/riscv64-softmmu.mak create mode 100644 hw/riscv/Makefile.objs create mode 100644 target/riscv/Makefile.objs create mode 100644 target/riscv/trace-events diff --git a/Makefile.objs b/Makefile.objs index 285c6f3..ae8658e 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -164,6 +164,7 @@ trace-events-subdirs +=3D target/mips trace-events-subdirs +=3D target/sparc trace-events-subdirs +=3D target/s390x trace-events-subdirs +=3D target/ppc +trace-events-subdirs +=3D target/riscv trace-events-subdirs +=3D qom trace-events-subdirs +=3D linux-user trace-events-subdirs +=3D qapi diff --git a/arch_init.c b/arch_init.c index a0b8ed6..dcf356b 100644 --- a/arch_init.c +++ b/arch_init.c @@ -69,6 +69,8 @@ int graphic_depth =3D 32; #define QEMU_ARCH QEMU_ARCH_OPENRISC #elif defined(TARGET_PPC) #define QEMU_ARCH QEMU_ARCH_PPC +#elif defined(TARGET_RISCV) +#define QEMU_ARCH QEMU_ARCH_RISCV #elif defined(TARGET_S390X) #define QEMU_ARCH QEMU_ARCH_S390X #elif defined(TARGET_SH4) diff --git a/configure b/configure index 100309c..832e025 100755 --- a/configure +++ b/configure @@ -6530,6 +6530,14 @@ case "$target_name" in echo "TARGET_ABI32=3Dy" >> $config_target_mak gdb_xml_files=3D"power64-core.xml power-fpu.xml power-altivec.xml powe= r-spe.xml power-vsx.xml" ;; + riscv32) + TARGET_BASE_ARCH=3Driscv + TARGET_ABI_DIR=3Driscv + ;; + riscv64) + TARGET_BASE_ARCH=3Driscv + TARGET_ABI_DIR=3Driscv + ;; sh4|sh4eb) TARGET_ARCH=3Dsh4 bflt=3D"yes" @@ -6692,6 +6700,9 @@ for i in $ARCH $TARGET_BASE_ARCH ; do ppc*) disas_config "PPC" ;; + riscv) + disas_config "RISCV" + ;; s390*) disas_config "S390" ;; diff --git a/cpus.c b/cpus.c index 83700c1..702da8b 100644 --- a/cpus.c +++ b/cpus.c @@ -1909,6 +1909,9 @@ CpuInfoList *qmp_query_cpus(Error **errp) #elif defined(TARGET_SPARC) SPARCCPU *sparc_cpu =3D SPARC_CPU(cpu); CPUSPARCState *env =3D &sparc_cpu->env; +#elif defined(TARGET_RISCV) + RISCVCPU *riscv_cpu =3D RISCV_CPU(cpu); + CPURISCVState *env =3D &riscv_cpu->env; #elif defined(TARGET_MIPS) MIPSCPU *mips_cpu =3D MIPS_CPU(cpu); CPUMIPSState *env =3D &mips_cpu->env; @@ -1942,6 +1945,9 @@ CpuInfoList *qmp_query_cpus(Error **errp) #elif defined(TARGET_TRICORE) info->value->arch =3D CPU_INFO_ARCH_TRICORE; info->value->u.tricore.PC =3D env->PC; +#elif defined(TARGET_RISCV) + info->value->arch =3D CPU_INFO_ARCH_RISCV; + info->value->u.riscv.pc =3D env->pc; #else info->value->arch =3D CPU_INFO_ARCH_OTHER; #endif diff --git a/default-configs/riscv32-linux-user.mak b/default-configs/riscv= 32-linux-user.mak new file mode 100644 index 0000000..865b362 --- /dev/null +++ b/default-configs/riscv32-linux-user.mak @@ -0,0 +1 @@ +# Default configuration for riscv-linux-user diff --git a/default-configs/riscv32-softmmu.mak b/default-configs/riscv32-= softmmu.mak new file mode 100644 index 0000000..f9e7421 --- /dev/null +++ b/default-configs/riscv32-softmmu.mak @@ -0,0 +1,4 @@ +# Default configuration for riscv-softmmu + +CONFIG_SERIAL=3Dy +CONFIG_VIRTIO=3Dy diff --git a/default-configs/riscv64-linux-user.mak b/default-configs/riscv= 64-linux-user.mak new file mode 100644 index 0000000..865b362 --- /dev/null +++ b/default-configs/riscv64-linux-user.mak @@ -0,0 +1 @@ +# Default configuration for riscv-linux-user diff --git a/default-configs/riscv64-softmmu.mak b/default-configs/riscv64-= softmmu.mak new file mode 100644 index 0000000..f9e7421 --- /dev/null +++ b/default-configs/riscv64-softmmu.mak @@ -0,0 +1,4 @@ +# Default configuration for riscv-softmmu + +CONFIG_SERIAL=3Dy +CONFIG_VIRTIO=3Dy diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs new file mode 100644 index 0000000..a0c31ae --- /dev/null +++ b/hw/riscv/Makefile.objs @@ -0,0 +1,12 @@ +obj-y +=3D riscv_elf.o +obj-y +=3D riscv_htif.o +obj-y +=3D riscv_hart.o +obj-y +=3D sifive_e300.o +obj-y +=3D sifive_clint.o +obj-y +=3D sifive_prci.o +obj-y +=3D sifive_plic.o +obj-y +=3D sifive_u500.o +obj-y +=3D sifive_uart.o +obj-y +=3D spike_v1_09.o +obj-y +=3D spike_v1_10.o +obj-y +=3D virt.o diff --git a/include/sysemu/arch_init.h b/include/sysemu/arch_init.h index 8751c46..63c6152 100644 --- a/include/sysemu/arch_init.h +++ b/include/sysemu/arch_init.h @@ -24,6 +24,7 @@ enum { QEMU_ARCH_MOXIE =3D (1 << 15), QEMU_ARCH_TRICORE =3D (1 << 16), QEMU_ARCH_NIOS2 =3D (1 << 17), + QEMU_ARCH_RISCV =3D (1 << 18), }; =20 extern const uint32_t arch_type; diff --git a/qapi-schema.json b/qapi-schema.json index 5c06745..a69c9fe 100644 --- a/qapi-schema.json +++ b/qapi-schema.json @@ -413,7 +413,7 @@ # Since: 2.6 ## { 'enum': 'CpuInfoArch', - 'data': ['x86', 'sparc', 'ppc', 'mips', 'tricore', 'other' ] } + 'data': ['x86', 'sparc', 'ppc', 'mips', 'tricore', 'riscv', 'other' ] } =20 ## # @CpuInfo: @@ -452,6 +452,7 @@ 'ppc': 'CpuInfoPPC', 'mips': 'CpuInfoMIPS', 'tricore': 'CpuInfoTricore', + 'riscv': 'CpuInfoRISCV', 'other': 'CpuInfoOther' } } =20 ## @@ -512,6 +513,17 @@ { 'struct': 'CpuInfoTricore', 'data': { 'PC': 'int' } } =20 ## +# @CpuInfoRISCV: +# +# Additional information about a virtual RISCV CPU +# +# @pc: the instruction pointer +# +# Since 2.8 +## +{ 'struct': 'CpuInfoRISCV', 'data': { 'pc': 'int' } } + +## # @CpuInfoOther: # # No additional information is available about the virtual CPU diff --git a/scripts/qemu-binfmt-conf.sh b/scripts/qemu-binfmt-conf.sh index 8afc3eb..c5ac660 100755 --- a/scripts/qemu-binfmt-conf.sh +++ b/scripts/qemu-binfmt-conf.sh @@ -4,7 +4,7 @@ =20 qemu_target_list=3D"i386 i486 alpha arm sparc32plus ppc ppc64 ppc64le m68k= \ mips mipsel mipsn32 mipsn32el mips64 mips64el \ -sh4 sh4eb s390x aarch64 hppa" +sh4 sh4eb s390x aarch64 hppa riscv32 riscv64" =20 i386_magic=3D'\x7fELF\x01\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\= x00\x03\x00' i386_mask=3D'\xff\xff\xff\xff\xff\xfe\xfe\xff\xff\xff\xff\xff\xff\xff\xff\= xff\xfe\xff\xff\xff' @@ -96,6 +96,14 @@ hppa_magic=3D'\x7f\x45\x4c\x46\x01\x02\x01\x00\x00\x00\x= 00\x00\x00\x00\x00\x00\x00 hppa_mask=3D'\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\xff\= xff\xff\xfe\xff\xff' hppa_family=3Dhppa =20 +riscv32_magic=3D'\x7fELF\x01\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x= 02\x00\xf3\x00' +riscv32_mask=3D'\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\x= ff\xff\xfe\xff\xff\xff' +riscv32_family=3Driscv + +riscv64_magic=3D'\x7fELF\x02\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x= 02\x00\xf3\x00' +riscv64_mask=3D'\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\x= ff\xff\xfe\xff\xff\xff' +riscv64_family=3Driscv + qemu_get_family() { cpu=3D${HOST_ARCH:-$(uname -m)} case "$cpu" in @@ -117,6 +125,9 @@ qemu_get_family() { sparc*) echo "sparc" ;; + riscv*) + echo "riscv" + ;; *) echo "$cpu" ;; diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs new file mode 100644 index 0000000..0c08263 --- /dev/null +++ b/target/riscv/Makefile.objs @@ -0,0 +1,2 @@ +obj-y +=3D translate.o op_helper.o helper.o cpu.o fpu_helper.o \ + user_syscall.o user_atomic.o gdbstub.o pmp.o diff --git a/target/riscv/trace-events b/target/riscv/trace-events new file mode 100644 index 0000000..9284b1f --- /dev/null +++ b/target/riscv/trace-events @@ -0,0 +1 @@ +# See docs/devel/tracing.txt for syntax documentation. --=20 2.7.0