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X-Received-From: 2a00:1450:400c:c0c::241 Subject: [Qemu-devel] [PATCH v2 12/16] target/xtensa: add internal/noop SRs and opcodes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add two special registers: MMID and DDR: - MMID is write-only and the only side effect of writing to it is output to the trace port, which is not emulated; - DDR is only accessible in debug mode, which is not emulated. Add two debug-mode-only opcodes: - rfdd and rfdo do return from the debug mode, which is not emulated. Add three internal opcodes for full MMU: - hwwdtlba and hwwitlba are the internal opcodes that write a value into autoupdate DTLB or ITLB entry. - ldpte is internal opcode that loads PTE entry that covers the most recent page fault address. None of these three opcodes may appear in a valid instruction. Signed-off-by: Max Filippov --- target/xtensa/cpu.h | 2 ++ target/xtensa/translate.c | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index e93bbb3c6d1e..80e9b47e84e9 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -127,6 +127,7 @@ enum { WINDOW_BASE =3D 72, WINDOW_START =3D 73, PTEVADDR =3D 83, + MMID =3D 89, RASID =3D 90, ITLBCFG =3D 91, DTLBCFG =3D 92, @@ -134,6 +135,7 @@ enum { MEMCTL =3D 97, CACHEATTR =3D 98, ATOMCTL =3D 99, + DDR =3D 104, IBREAKA =3D 128, DBREAKA =3D 144, DBREAKC =3D 160, diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index fb6a4c979590..f644d9fed22a 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -135,6 +135,7 @@ static const XtensaReg sregnames[256] =3D { [WINDOW_START] =3D XTENSA_REG("WINDOW_START", XTENSA_OPTION_WINDOWED_REGISTER), [PTEVADDR] =3D XTENSA_REG("PTEVADDR", XTENSA_OPTION_MMU), + [MMID] =3D XTENSA_REG_BITS("MMID", XTENSA_OPTION_ALL), [RASID] =3D XTENSA_REG("RASID", XTENSA_OPTION_MMU), [ITLBCFG] =3D XTENSA_REG("ITLBCFG", XTENSA_OPTION_MMU), [DTLBCFG] =3D XTENSA_REG("DTLBCFG", XTENSA_OPTION_MMU), @@ -142,6 +143,7 @@ static const XtensaReg sregnames[256] =3D { [MEMCTL] =3D XTENSA_REG_BITS("MEMCTL", XTENSA_OPTION_ALL), [CACHEATTR] =3D XTENSA_REG("CACHEATTR", XTENSA_OPTION_CACHEATTR), [ATOMCTL] =3D XTENSA_REG("ATOMCTL", XTENSA_OPTION_ATOMCTL), + [DDR] =3D XTENSA_REG("DDR", XTENSA_OPTION_DEBUG), [IBREAKA] =3D XTENSA_REG("IBREAKA0", XTENSA_OPTION_DEBUG), [IBREAKA + 1] =3D XTENSA_REG("IBREAKA1", XTENSA_OPTION_DEBUG), [DBREAKA] =3D XTENSA_REG("DBREAKA0", XTENSA_OPTION_DEBUG), @@ -2767,6 +2769,12 @@ static const XtensaOpcodeOps core_ops[] =3D { .name =3D "extw", .translate =3D translate_nop, }, { + .name =3D "hwwdtlba", + .translate =3D translate_ill, + }, { + .name =3D "hwwitlba", + .translate =3D translate_ill, + }, { .name =3D "idtlb", .translate =3D translate_itlb, .par =3D (const uint32_t[]){true}, @@ -2852,6 +2860,9 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_NONE, 0, 0, 4}, }, { + .name =3D "ldpte", + .translate =3D translate_ill, + }, { .name =3D "loop", .translate =3D translate_loop, .par =3D (const uint32_t[]){TCG_COND_NEVER}, @@ -3270,9 +3281,15 @@ static const XtensaOpcodeOps core_ops[] =3D { .name =3D "retw.n", .translate =3D translate_retw, }, { + .name =3D "rfdd", + .translate =3D translate_ill, + }, { .name =3D "rfde", .translate =3D translate_rfde, }, { + .name =3D "rfdo", + .translate =3D translate_ill, + }, { .name =3D "rfe", .translate =3D translate_rfe, }, { @@ -3373,6 +3390,10 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_rsr, .par =3D (const uint32_t[]){DBREAKC + 1}, }, { + .name =3D "rsr.ddr", + .translate =3D translate_rsr, + .par =3D (const uint32_t[]){DDR}, + }, { .name =3D "rsr.debugcause", .translate =3D translate_rsr, .par =3D (const uint32_t[]){DEBUGCAUSE}, @@ -3808,6 +3829,10 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_wsr, .par =3D (const uint32_t[]){DBREAKC + 1}, }, { + .name =3D "wsr.ddr", + .translate =3D translate_wsr, + .par =3D (const uint32_t[]){DDR}, + }, { .name =3D "wsr.debugcause", .translate =3D translate_wsr, .par =3D (const uint32_t[]){DEBUGCAUSE}, @@ -4000,6 +4025,10 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_wsr, .par =3D (const uint32_t[]){MISC + 3}, }, { + .name =3D "wsr.mmid", + .translate =3D translate_wsr, + .par =3D (const uint32_t[]){MMID}, + }, { .name =3D "wsr.prid", .translate =3D translate_wsr, .par =3D (const uint32_t[]){PRID}, @@ -4127,6 +4156,10 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_xsr, .par =3D (const uint32_t[]){DBREAKC + 1}, }, { + .name =3D "xsr.ddr", + .translate =3D translate_xsr, + .par =3D (const uint32_t[]){DDR}, + }, { .name =3D "xsr.debugcause", .translate =3D translate_xsr, .par =3D (const uint32_t[]){DEBUGCAUSE}, --=20 2.1.4