From nobody Wed Oct 29 05:57:24 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1513573346297481.4443574881192; Sun, 17 Dec 2017 21:02:26 -0800 (PST) Received: from localhost ([::1]:56797 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eQnZE-0000Ls-9H for importer@patchew.org; Mon, 18 Dec 2017 00:02:20 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37379) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eQnYF-0008NB-42 for qemu-devel@nongnu.org; Mon, 18 Dec 2017 00:01:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eQnYC-0000PV-39 for qemu-devel@nongnu.org; Mon, 18 Dec 2017 00:01:19 -0500 Received: from mail-pl0-x241.google.com ([2607:f8b0:400e:c01::241]:36702) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eQnYB-0000Oe-Sz; Mon, 18 Dec 2017 00:01:16 -0500 Received: by mail-pl0-x241.google.com with SMTP id b12so4165940plm.3; Sun, 17 Dec 2017 21:01:15 -0800 (PST) Received: from localhost (113x36x63x49.ap113.ftth.ucom.ne.jp. [113.36.63.49]) by smtp.gmail.com with ESMTPSA id f3sm20106401pgt.15.2017.12.17.21.01.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 17 Dec 2017 21:01:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=Bd2j3nkAvX78RfuwI7vcQtajx0cacQwa8BnpxifFygA=; b=LFUZ/wAER7gRboh5oINHJJNHP7YZEN3TNLiCK/iXedfMpU8PuFtYns+Riu1t3IrgQa oF4J9ITavsGw1iQi17U9qklkNbz+Kb2MosK3h3se4xNFheC+0ti6rdaBhFUoZQkByFTy Hay9fxefKs8Z8yqMQxay6UkRutPVy/PF1/8n91hmm+mc1x0661jUnmahqj1roFD/PoeN lI/0YmKNKPBaszo9HDosxW/x/FZz4YqPzxWvOV1PmxjfJc8uNSqFoA7NQs6hOYBdVLdI I2LmVuKBFdfcBvUWldegpPWF7VfSrzjt81L4UYLLdyDvhxwlIiBQvZoII/msWKA6OHmk mhYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=Bd2j3nkAvX78RfuwI7vcQtajx0cacQwa8BnpxifFygA=; b=Cw264HrOlrn+GhoNzoQL9Q/PS1GM2tjBFLAMFI/xruQ7BSqUaq75Qeon9wxPt9mXtr uwOD/3HzW5qD1uJoVBJ0VOny0cAgwKbauUiwYRbcuog3eC6ZdfbKxvBKh6DDHXIaMxVw liR4Gzw/QQ1Cr/Sf7w6IuYaIMSDW90lmgY1hE6zwpyyJA1R0h6++OTRT+ZrKNRZJ7rB5 1GDjAH+19pDYJHRKuejv2OtsTdZvnT0kk8dm/AqbtJglSy81nBGi8xQ247b0RKt/CvfJ e1lmCnWISVDRfUkocVkEP7NkC/eIFJr54BE8qPMhMtfqjwd+WJJ+VRI+EFLA2YY9zrkl XvlQ== X-Gm-Message-State: AKGB3mLmTp6mO4f2TA5KbY3NZDHX9lfkN55by42FM83uQn6bYhK9yJm2 kQ3K2qgdWGomEL4Dn85UX1doB8WO6Io= X-Google-Smtp-Source: ACJfBos5Yd54t6pkkQ95fWrgWmcVOKXVi4b7z3YutB5EUyUo8LchIt9gEdGDTPUvovt8RaXfTTm64Q== X-Received: by 10.159.235.132 with SMTP id f4mr21160365plr.122.1513573273859; Sun, 17 Dec 2017 21:01:13 -0800 (PST) From: Hikaru Nishida To: qemu-devel@nongnu.org Date: Mon, 18 Dec 2017 14:00:43 +0900 Message-Id: <1513573243-29022-1-git-send-email-hikarupsp@gmail.com> X-Mailer: git-send-email 2.7.4 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::241 Subject: [Qemu-devel] [PATCH] hw/block: Fix pin-based interrupt behaviour of NVMe X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Keith Busch , Kevin Wolf , Hikaru Nishida , "open list:nvme" , Max Reitz Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Pin-based interrupt of NVMe controller did not work properly because using an obsolated function pci_irq_pulse(). To fix this, change to use pci_irq_assert() / pci_irq_deassert() instead of pci_irq_pulse(). Signed-off-by: Hikaru Nishida Reviewed-by: Keith Busch --- hw/block/nvme.c | 39 ++++++++++++++++++++++++++++++++++----- hw/block/nvme.h | 1 + 2 files changed, 35 insertions(+), 5 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 441e21e..2d164fc 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -82,13 +82,40 @@ static uint8_t nvme_sq_empty(NvmeSQueue *sq) return sq->head =3D=3D sq->tail; } =20 -static void nvme_isr_notify(NvmeCtrl *n, NvmeCQueue *cq) +static void nvme_irq_check(NvmeCtrl *n) +{ + if (msix_enabled(&(n->parent_obj))) { + return; + } + if (~n->bar.intms & n->irq_status) { + pci_irq_assert(&n->parent_obj); + } else { + pci_irq_deassert(&n->parent_obj); + } +} + +static void nvme_irq_assert(NvmeCtrl *n, NvmeCQueue *cq) { if (cq->irq_enabled) { if (msix_enabled(&(n->parent_obj))) { msix_notify(&(n->parent_obj), cq->vector); } else { - pci_irq_pulse(&n->parent_obj); + assert(cq->cqid < 64); + n->irq_status |=3D 1 << cq->cqid; + nvme_irq_check(n); + } + } +} + +static void nvme_irq_deassert(NvmeCtrl *n, NvmeCQueue *cq) +{ + if (cq->irq_enabled) { + if (msix_enabled(&(n->parent_obj))) { + return; + } else { + assert(cq->cqid < 64); + n->irq_status &=3D ~(1 << cq->cqid); + nvme_irq_check(n); } } } @@ -220,7 +247,7 @@ static void nvme_post_cqes(void *opaque) sizeof(req->cqe)); QTAILQ_INSERT_TAIL(&sq->req_list, req, entry); } - nvme_isr_notify(n, cq); + nvme_irq_assert(n, cq); } =20 static void nvme_enqueue_req_completion(NvmeCQueue *cq, NvmeRequest *req) @@ -753,10 +780,12 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset= , uint64_t data, case 0xc: n->bar.intms |=3D data & 0xffffffff; n->bar.intmc =3D n->bar.intms; + nvme_irq_check(n); break; case 0x10: n->bar.intms &=3D ~(data & 0xffffffff); n->bar.intmc =3D n->bar.intms; + nvme_irq_check(n); break; case 0x14: /* Windows first sends data, then sends enable bit */ @@ -851,8 +880,8 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr, i= nt val) timer_mod(cq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 5= 00); } =20 - if (cq->tail !=3D cq->head) { - nvme_isr_notify(n, cq); + if (cq->tail =3D=3D cq->head) { + nvme_irq_deassert(n, cq); } } else { uint16_t new_tail =3D val & 0xffff; diff --git a/hw/block/nvme.h b/hw/block/nvme.h index 6aab338..7b62dad 100644 --- a/hw/block/nvme.h +++ b/hw/block/nvme.h @@ -775,6 +775,7 @@ typedef struct NvmeCtrl { uint32_t cmbsz; uint32_t cmbloc; uint8_t *cmbuf; + uint64_t irq_status; =20 char *serial; NvmeNamespace *namespaces; --=20 2.7.4