From nobody Wed Apr 16 05:23:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1513189061978498.12699140237225; Wed, 13 Dec 2017 10:17:41 -0800 (PST) Received: from localhost ([::1]:36816 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ePBay-0008Ey-NT for importer@patchew.org; Wed, 13 Dec 2017 13:17:28 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51341) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ePBWT-0004a7-50 for qemu-devel@nongnu.org; Wed, 13 Dec 2017 13:12:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ePBWR-0007ZK-ND for qemu-devel@nongnu.org; Wed, 13 Dec 2017 13:12:49 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:39114) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ePBWR-0007XQ-Fy for qemu-devel@nongnu.org; Wed, 13 Dec 2017 13:12:47 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1ePBWQ-0007bC-G0 for qemu-devel@nongnu.org; Wed, 13 Dec 2017 18:12:46 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Wed, 13 Dec 2017 18:12:04 +0000 Message-Id: <1513188761-20784-7-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1513188761-20784-1-git-send-email-peter.maydell@linaro.org> References: <1513188761-20784-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 06/43] xilinx_spips: Update striping to be big-endian bit order X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Francisco Iglesias Update striping functionality to be big-endian bit order (as according to the Zynq-7000 Technical Reference Manual). Output thereafter the even bits into the flash memory connected to the lower QSPI bus and the odd bits into the flash memory connected to the upper QSPI bus. Signed-off-by: Francisco Iglesias Acked-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias Message-id: 20171126231634.9531-7-frasse.iglesias@gmail.com Signed-off-by: Peter Maydell --- hw/ssi/xilinx_spips.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 559fa79e..231aa5b 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -208,14 +208,14 @@ static void xilinx_spips_reset(DeviceState *d) xilinx_spips_update_cs_lines(s); } =20 -/* N way (num) in place bit striper. Lay out row wise bits (LSB to MSB) +/* N way (num) in place bit striper. Lay out row wise bits (MSB to LSB) * column wise (from element 0 to N-1). num is the length of x, and dir * reverses the direction of the transform. Best illustrated by example: * Each digit in the below array is a single bit (num =3D=3D 3): * - * {{ 76543210, } ----- stripe (dir =3D=3D false) -----> {{ FCheb630, } - * { hgfedcba, } { GDAfc741, } - * { HGFEDCBA, }} <---- upstripe (dir =3D=3D true) ----- { HEBgda52, }} + * {{ 76543210, } ----- stripe (dir =3D=3D false) -----> {{ 741gdaFC, } + * { hgfedcba, } { 630fcHEB, } + * { HGFEDCBA, }} <---- upstripe (dir =3D=3D true) ----- { 52hebGDA, }} */ =20 static inline void stripe8(uint8_t *x, int num, bool dir) @@ -223,15 +223,15 @@ static inline void stripe8(uint8_t *x, int num, bool = dir) uint8_t r[num]; memset(r, 0, sizeof(uint8_t) * num); int idx[2] =3D {0, 0}; - int bit[2] =3D {0, 0}; + int bit[2] =3D {0, 7}; int d =3D dir; =20 for (idx[0] =3D 0; idx[0] < num; ++idx[0]) { - for (bit[0] =3D 0; bit[0] < 8; ++bit[0]) { - r[idx[d]] |=3D x[idx[!d]] & 1 << bit[!d] ? 1 << bit[d] : 0; + for (bit[0] =3D 7; bit[0] >=3D 0; bit[0]--) { + r[idx[!d]] |=3D x[idx[d]] & 1 << bit[d] ? 1 << bit[!d] : 0; idx[1] =3D (idx[1] + 1) % num; if (!idx[1]) { - bit[1]++; + bit[1]--; } } } @@ -266,8 +266,9 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) } =20 for (i =3D 0; i < num_effective_busses(s); ++i) { + int bus =3D num_effective_busses(s) - 1 - i; DB_PRINT_L(debug_level, "tx =3D %02x\n", tx_rx[i]); - tx_rx[i] =3D ssi_transfer(s->spi[i], (uint32_t)tx_rx[i]); + tx_rx[i] =3D ssi_transfer(s->spi[bus], (uint32_t)tx_rx[i]); DB_PRINT_L(debug_level, "rx =3D %02x\n", tx_rx[i]); } =20 --=20 2.7.4