From nobody Wed Apr 16 06:36:44 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1513191301573391.4378932265437; Wed, 13 Dec 2017 10:55:01 -0800 (PST) Received: from localhost ([::1]:36997 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ePC6R-0001u9-K8 for importer@patchew.org; Wed, 13 Dec 2017 13:49:59 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51780) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ePBWo-0004yf-4T for qemu-devel@nongnu.org; Wed, 13 Dec 2017 13:13:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ePBWm-0008BT-Q5 for qemu-devel@nongnu.org; Wed, 13 Dec 2017 13:13:10 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:39150) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ePBWm-00089j-G9 for qemu-devel@nongnu.org; Wed, 13 Dec 2017 13:13:08 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1ePBWl-0007oR-8u for qemu-devel@nongnu.org; Wed, 13 Dec 2017 18:13:07 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Wed, 13 Dec 2017 18:12:33 +0000 Message-Id: <1513188761-20784-36-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1513188761-20784-1-git-send-email-peter.maydell@linaro.org> References: <1513188761-20784-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 35/43] target/arm: Remove fsr argument from get_phys_addr() and arm_tlb_fill() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" All of the callers of get_phys_addr() and arm_tlb_fill() now ignore the FSR values they return, so we can just remove the argument entirely. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Edgar E. Iglesias Tested-by: Stefano Stabellini Message-id: 1512503192-2239-12-git-send-email-peter.maydell@linaro.org --- target/arm/internals.h | 2 +- target/arm/helper.c | 45 ++++++++++++++------------------------------- target/arm/op_helper.c | 3 +-- 3 files changed, 16 insertions(+), 34 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 67b9a52..876854d 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -690,7 +690,7 @@ static inline uint32_t arm_fi_to_lfsc(ARMMMUFaultInfo *= fi) /* Do a page table walk and add page to TLB if possible */ bool arm_tlb_fill(CPUState *cpu, vaddr address, MMUAccessType access_type, int mmu_idx, - uint32_t *fsr, ARMMMUFaultInfo *fi); + ARMMMUFaultInfo *fi); =20 /* Return true if the stage 1 translation regime is using LPAE format page * tables */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 79ab277..c469e6a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -28,7 +28,7 @@ typedef struct ARMCacheAttrs { static bool get_phys_addr(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, - target_ulong *page_size, uint32_t *fsr, + target_ulong *page_size, ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs); =20 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, @@ -2160,7 +2160,6 @@ static uint64_t do_ats_write(CPUARMState *env, uint64= _t value, hwaddr phys_addr; target_ulong page_size; int prot; - uint32_t fsr_unused; bool ret; uint64_t par64; MemTxAttrs attrs =3D {}; @@ -2168,7 +2167,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64= _t value, ARMCacheAttrs cacheattrs =3D {}; =20 ret =3D get_phys_addr(env, value, access_type, mmu_idx, &phys_addr, &a= ttrs, - &prot, &page_size, &fsr_unused, &fi, &cacheattrs); + &prot, &page_size, &fi, &cacheattrs); /* TODO: this is not the correct condition to use to decide whether * to report a PAR in 64-bit or 32-bit format. */ @@ -6981,7 +6980,6 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx= mmu_idx, target_ulong page_size; hwaddr physaddr; int prot; - uint32_t fsr; =20 v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, &sattrs); if (!sattrs.nsc || sattrs.ns) { @@ -6995,7 +6993,7 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx= mmu_idx, return false; } if (get_phys_addr(env, addr, MMU_INST_FETCH, mmu_idx, - &physaddr, &attrs, &prot, &page_size, &fsr, &fi, NUL= L)) { + &physaddr, &attrs, &prot, &page_size, &fi, NULL)) { /* the MPU lookup failed */ env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_IACCVIOL_MASK; armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, env->v7m.secur= e); @@ -9749,14 +9747,13 @@ static ARMCacheAttrs combine_cacheattrs(ARMCacheAtt= rs s1, ARMCacheAttrs s2) * @attrs: set to the memory transaction attributes to use * @prot: set to the permissions for the page containing phys_ptr * @page_size: set to the size of the page containing phys_ptr - * @fsr: set to the DFSR/IFSR value on failure * @fi: set to fault info if the translation fails * @cacheattrs: (if non-NULL) set to the cacheability/shareability attribu= tes */ static bool get_phys_addr(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, - target_ulong *page_size, uint32_t *fsr, + target_ulong *page_size, ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) { if (mmu_idx =3D=3D ARMMMUIdx_S12NSE0 || mmu_idx =3D=3D ARMMMUIdx_S12NS= E1) { @@ -9771,7 +9768,7 @@ static bool get_phys_addr(CPUARMState *env, target_ul= ong address, =20 ret =3D get_phys_addr(env, address, access_type, stage_1_mmu_idx(mmu_idx), &ipa, attrs, - prot, page_size, fsr, fi, cacheattrs); + prot, page_size, fi, cacheattrs); =20 /* If S1 fails or S2 is disabled, return early. */ if (ret || regime_translation_disabled(env, ARMMMUIdx_S2NS)) { @@ -9784,7 +9781,6 @@ static bool get_phys_addr(CPUARMState *env, target_ul= ong address, phys_ptr, attrs, &s2_prot, page_size, fi, cacheattrs !=3D NULL ? &cacheattrs2 := NULL); - *fsr =3D arm_fi_to_lfsc(fi); fi->s2addr =3D ipa; /* Combine the S1 and S2 perms. */ *prot &=3D s2_prot; @@ -9830,17 +9826,14 @@ static bool get_phys_addr(CPUARMState *env, target_= ulong address, /* PMSAv8 */ ret =3D get_phys_addr_pmsav8(env, address, access_type, mmu_id= x, phys_ptr, attrs, prot, fi); - *fsr =3D arm_fi_to_sfsc(fi); } else if (arm_feature(env, ARM_FEATURE_V7)) { /* PMSAv7 */ ret =3D get_phys_addr_pmsav7(env, address, access_type, mmu_id= x, phys_ptr, prot, fi); - *fsr =3D arm_fi_to_sfsc(fi); } else { /* Pre-v7 MPU */ ret =3D get_phys_addr_pmsav5(env, address, access_type, mmu_id= x, phys_ptr, prot, fi); - *fsr =3D arm_fi_to_sfsc(fi); } qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32 " mmu_idx %u -> %s (prot %c%c%c)\n", @@ -9866,24 +9859,15 @@ static bool get_phys_addr(CPUARMState *env, target_= ulong address, } =20 if (regime_using_lpae_format(env, mmu_idx)) { - bool ret =3D get_phys_addr_lpae(env, address, access_type, mmu_idx, - phys_ptr, attrs, prot, page_size, - fi, cacheattrs); - - *fsr =3D arm_fi_to_lfsc(fi); - return ret; + return get_phys_addr_lpae(env, address, access_type, mmu_idx, + phys_ptr, attrs, prot, page_size, + fi, cacheattrs); } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { - bool ret =3D get_phys_addr_v6(env, address, access_type, mmu_idx, - phys_ptr, attrs, prot, page_size, fi); - - *fsr =3D arm_fi_to_sfsc(fi); - return ret; + return get_phys_addr_v6(env, address, access_type, mmu_idx, + phys_ptr, attrs, prot, page_size, fi); } else { - bool ret =3D get_phys_addr_v5(env, address, access_type, mmu_idx, + return get_phys_addr_v5(env, address, access_type, mmu_idx, phys_ptr, prot, page_size, fi); - - *fsr =3D arm_fi_to_sfsc(fi); - return ret; } } =20 @@ -9892,7 +9876,7 @@ static bool get_phys_addr(CPUARMState *env, target_ul= ong address, * fsr with ARM DFSR/IFSR fault register format value on failure. */ bool arm_tlb_fill(CPUState *cs, vaddr address, - MMUAccessType access_type, int mmu_idx, uint32_t *fsr, + MMUAccessType access_type, int mmu_idx, ARMMMUFaultInfo *fi) { ARMCPU *cpu =3D ARM_CPU(cs); @@ -9905,7 +9889,7 @@ bool arm_tlb_fill(CPUState *cs, vaddr address, =20 ret =3D get_phys_addr(env, address, access_type, core_to_arm_mmu_idx(env, mmu_idx), &phys_addr, - &attrs, &prot, &page_size, fsr, fi, NULL); + &attrs, &prot, &page_size, fi, NULL); if (!ret) { /* Map a single [sub]page. */ phys_addr &=3D TARGET_PAGE_MASK; @@ -9927,14 +9911,13 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *= cs, vaddr addr, target_ulong page_size; int prot; bool ret; - uint32_t fsr; ARMMMUFaultInfo fi =3D {}; ARMMMUIdx mmu_idx =3D core_to_arm_mmu_idx(env, cpu_mmu_index(env, fals= e)); =20 *attrs =3D (MemTxAttrs) {}; =20 ret =3D get_phys_addr(env, addr, 0, mmu_idx, &phys_addr, - attrs, &prot, &page_size, &fsr, &fi, NULL); + attrs, &prot, &page_size, &fi, NULL); =20 if (ret) { return -1; diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 38e6993..c2bb4f3 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -176,10 +176,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAcce= ssType access_type, int mmu_idx, uintptr_t retaddr) { bool ret; - uint32_t fsr =3D 0; ARMMMUFaultInfo fi =3D {}; =20 - ret =3D arm_tlb_fill(cs, addr, access_type, mmu_idx, &fsr, &fi); + ret =3D arm_tlb_fill(cs, addr, access_type, mmu_idx, &fi); if (unlikely(ret)) { ARMCPU *cpu =3D ARM_CPU(cs); =20 --=20 2.7.4