From nobody Wed Apr 16 05:29:23 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1513190462307121.26109480110597; Wed, 13 Dec 2017 10:41:02 -0800 (PST) Received: from localhost ([::1]:36950 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ePBxW-0002aR-Hp for importer@patchew.org; Wed, 13 Dec 2017 13:40:46 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51549) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ePBWc-0004kI-H9 for qemu-devel@nongnu.org; Wed, 13 Dec 2017 13:12:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ePBWb-0007sM-C5 for qemu-devel@nongnu.org; Wed, 13 Dec 2017 13:12:58 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:39132) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ePBWb-0007pU-5o for qemu-devel@nongnu.org; Wed, 13 Dec 2017 13:12:57 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1ePBWa-0007gs-0e for qemu-devel@nongnu.org; Wed, 13 Dec 2017 18:12:56 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Wed, 13 Dec 2017 18:12:17 +0000 Message-Id: <1513188761-20784-20-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1513188761-20784-1-git-send-email-peter.maydell@linaro.org> References: <1513188761-20784-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 19/43] target/arm: Allow explicit writes to CONTROL.SPSEL in Handler mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In ARMv7M the CPU ignores explicit writes to CONTROL.SPSEL in Handler mode. In v8M the behaviour is slightly different: writes to the bit are permitted but will have no effect. We've already done the hard work to handle the value in CONTROL.SPSEL being out of sync with what stack pointer is actually in use, so all we need to do to fix this last loose end is to update the condition we use to guard whether we call write_v7m_control_spsel() on the register write. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 1512153879-5291-3-git-send-email-peter.maydell@linaro.org --- target/arm/helper.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 88394d4..f21c142 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10091,8 +10091,11 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t ma= skreg, uint32_t val) * thread mode; other bits can be updated by any privileged code. * write_v7m_control_spsel() deals with updating the SPSEL bit in * env->v7m.control, so we only need update the others. + * For v7M, we must just ignore explicit writes to SPSEL in handler + * mode; for v8M the write is permitted but will have no effect. */ - if (!arm_v7m_is_handler_mode(env)) { + if (arm_feature(env, ARM_FEATURE_V8) || + !arm_v7m_is_handler_mode(env)) { write_v7m_control_spsel(env, (val & R_V7M_CONTROL_SPSEL_MASK) = !=3D 0); } env->v7m.control[env->v7m.secure] &=3D ~R_V7M_CONTROL_NPRIV_MASK; --=20 2.7.4