From nobody Tue Oct 28 23:09:53 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 151318924903767.74843675092268; Wed, 13 Dec 2017 10:20:49 -0800 (PST) Received: from localhost ([::1]:36834 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ePBeC-0002hB-9g for importer@patchew.org; Wed, 13 Dec 2017 13:20:48 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51427) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ePBWV-0004d1-Qk for qemu-devel@nongnu.org; Wed, 13 Dec 2017 13:12:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ePBWU-0007fc-Sb for qemu-devel@nongnu.org; Wed, 13 Dec 2017 13:12:51 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:39114) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ePBWU-0007XQ-Ln for qemu-devel@nongnu.org; Wed, 13 Dec 2017 13:12:50 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1ePBCp-0007VA-Sa; Wed, 13 Dec 2017 17:52:31 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Wed, 13 Dec 2017 17:52:28 +0000 Message-Id: <1513187549-2435-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1513187549-2435-1-git-send-email-peter.maydell@linaro.org> References: <1513187549-2435-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 1/2] exec: Don't reuse unassigned_mem_ops for io_mem_rom X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Paul Burton , Yongbok Kim , Aurelien Jarno , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We set up the io_mem_rom special memory region using the unassigned_mem_ops structure; this is then used when a guest tries to write to ROM. This is incorrect, because the behaviour of unassigned memory may be different from that of ROM for writes. In particular, on some architectures writing to unassigned memory generates a guest exception, whereas writing to ROM is generally ignored. Use a special readonly_mem_ops for this purpose instead, so writes to ROM are ignored for all guest CPUs. Signed-off-by: Peter Maydell --- exec.c | 34 +++++++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/exec.c b/exec.c index 03238a3..74b8727 100644 --- a/exec.c +++ b/exec.c @@ -2720,6 +2720,37 @@ static uint16_t dummy_section(PhysPageMap *map, Flat= View *fv, MemoryRegion *mr) return phys_section_add(map, §ion); } =20 +static void readonly_mem_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + /* Ignore any write to ROM. */ +} + +static bool readonly_mem_accepts(void *opaque, hwaddr addr, + unsigned size, bool is_write) +{ + return is_write; +} + +/* This will only be used for writes, because reads are special cased + * to directly access the underlying host ram. + */ +static const MemoryRegionOps readonly_mem_ops =3D { + .write =3D readonly_mem_write, + .valid.accepts =3D readonly_mem_accepts, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 8, + .unaligned =3D false, + }, + .impl =3D { + .min_access_size =3D 1, + .max_access_size =3D 8, + .unaligned =3D false, + }, +}; + MemoryRegion *iotlb_to_region(CPUState *cpu, hwaddr index, MemTxAttrs attr= s) { int asidx =3D cpu_asidx_from_attrs(cpu, attrs); @@ -2732,7 +2763,8 @@ MemoryRegion *iotlb_to_region(CPUState *cpu, hwaddr i= ndex, MemTxAttrs attrs) =20 static void io_mem_init(void) { - memory_region_init_io(&io_mem_rom, NULL, &unassigned_mem_ops, NULL, NU= LL, UINT64_MAX); + memory_region_init_io(&io_mem_rom, NULL, &readonly_mem_ops, + NULL, NULL, UINT64_MAX); memory_region_init_io(&io_mem_unassigned, NULL, &unassigned_mem_ops, N= ULL, NULL, UINT64_MAX); =20 --=20 2.7.4