From nobody Tue Feb 10 17:45:40 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1513000502684212.10867365135653; Mon, 11 Dec 2017 05:55:02 -0800 (PST) Received: from localhost ([::1]:53177 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eOOXn-0003LD-R5 for importer@patchew.org; Mon, 11 Dec 2017 08:54:55 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35138) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eOO5j-0004pM-4t for qemu-devel@nongnu.org; Mon, 11 Dec 2017 08:25:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eOO5f-0004HN-Ph for qemu-devel@nongnu.org; Mon, 11 Dec 2017 08:25:55 -0500 Received: from mail.ispras.ru ([83.149.199.45]:44288) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eOO5f-0004GZ-8d for qemu-devel@nongnu.org; Mon, 11 Dec 2017 08:25:51 -0500 Received: from Misha-PC.lan02.inno (unknown [85.142.117.226]) by mail.ispras.ru (Postfix) with ESMTPSA id 74F9854006A; Mon, 11 Dec 2017 16:25:50 +0300 (MSK) From: Mihail Abakumov To: qemu-devel@nongnu.org Date: Mon, 11 Dec 2017 16:25:36 +0300 Message-ID: <151299873579.4808.10809590157198430235.stgit@Misha-PC.lan02.inno> In-Reply-To: <151299847127.4808.14646046517426494416.stgit@Misha-PC.lan02.inno> References: <151299847127.4808.14646046517426494416.stgit@Misha-PC.lan02.inno> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 83.149.199.45 Subject: [Qemu-devel] [PATCH v4 45/46] windbg: changed kd_api_read_msr and kd_api_write_msr X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, lprosek@redhat.com, dovgaluk@ispras.ru, rkagan@virtuozzo.com, pbonzini@redhat.com, den@openvz.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Added sub functions for helper_wrmsr and helper_rdmsr: cpu_x86_write_msr an= d cpu_x86_read_msr. Also they are used in packet handlers, i.e. duplication= of code is removed. Signed-off-by: Mihail Abakumov Signed-off-by: Pavel Dovgalyuk Signed-off-by: Dmitriy Koltunov --- target/i386/cpu.h | 3=20 target/i386/misc_helper.c | 49 +++++-- target/i386/windbgstub.c | 303 +----------------------------------------= ---- 3 files changed, 43 insertions(+), 312 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 051867399b..04c5aac795 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1481,6 +1481,9 @@ void cpu_x86_update_cr3(CPUX86State *env, target_ulon= g new_cr3); void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4); void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7); =20 +void cpu_x86_write_msr(CPUX86State *env, uint64_t val); +uint64_t cpu_x86_read_msr(CPUX86State *env); + /* hw/pc.c */ uint64_t cpu_get_tsc(CPUX86State *env); =20 diff --git a/target/i386/misc_helper.c b/target/i386/misc_helper.c index ec1fcd2899..5d74c31998 100644 --- a/target/i386/misc_helper.c +++ b/target/i386/misc_helper.c @@ -220,6 +220,14 @@ void helper_rdpmc(CPUX86State *env) } =20 #if defined(CONFIG_USER_ONLY) +void cpu_x86_write_msr(CPUX86State *env, uint64_t val) +{ +} + +uint64_t cpu_x86_read_msr(CPUX86State *env) +{ +} + void helper_wrmsr(CPUX86State *env) { } @@ -228,15 +236,8 @@ void helper_rdmsr(CPUX86State *env) { } #else -void helper_wrmsr(CPUX86State *env) +void cpu_x86_write_msr(CPUX86State *env, uint64_t val) { - uint64_t val; - - cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 1, GETPC()); - - val =3D ((uint32_t)env->regs[R_EAX]) | - ((uint64_t)((uint32_t)env->regs[R_EDX]) << 32); - switch ((uint32_t)env->regs[R_ECX]) { case MSR_IA32_SYSENTER_CS: env->sysenter_cs =3D val & 0xffff; @@ -386,16 +387,12 @@ void helper_wrmsr(CPUX86State *env) /* XXX: exception? */ break; } - - windbg_try_load(); } =20 -void helper_rdmsr(CPUX86State *env) +uint64_t cpu_x86_read_msr(CPUX86State *env) { uint64_t val; =20 - cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 0, GETPC()); - switch ((uint32_t)env->regs[R_ECX]) { case MSR_IA32_SYSENTER_CS: val =3D env->sysenter_cs; @@ -534,6 +531,32 @@ void helper_rdmsr(CPUX86State *env) val =3D 0; break; } + + return val; +} + +void helper_wrmsr(CPUX86State *env) +{ + uint64_t val; + + cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 1, GETPC()); + + val =3D ((uint32_t)env->regs[R_EAX]) | + ((uint64_t)((uint32_t)env->regs[R_EDX]) << 32); + + cpu_x86_write_msr(env, val); + + windbg_try_load(); +} + +void helper_rdmsr(CPUX86State *env) +{ + uint64_t val; + + cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 0, GETPC()); + + val =3D cpu_x86_read_msr(env); + env->regs[R_EAX] =3D (uint32_t)(val); env->regs[R_EDX] =3D (uint32_t)(val >> 32); } diff --git a/target/i386/windbgstub.c b/target/i386/windbgstub.c index 96cb015752..c38bfa7448 100755 --- a/target/i386/windbgstub.c +++ b/target/i386/windbgstub.c @@ -1076,150 +1076,9 @@ void kd_api_read_msr(CPUState *cpu, PacketData *pd) DBGKD_READ_WRITE_MSR *m64c =3D &pd->m64.u.ReadWriteMsr; CPUArchState *env =3D cpu->env_ptr; =20 - uint64_t val; - - cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 0, 0); - - switch ((uint32_t)env->regs[R_ECX]) { - case MSR_IA32_SYSENTER_CS: - val =3D env->sysenter_cs; - break; - case MSR_IA32_SYSENTER_ESP: - val =3D env->sysenter_esp; - break; - case MSR_IA32_SYSENTER_EIP: - val =3D env->sysenter_eip; - break; - case MSR_IA32_APICBASE: - val =3D cpu_get_apic_base(x86_env_get_cpu(env)->apic_state); - break; - case MSR_EFER: - val =3D env->efer; - break; - case MSR_STAR: - val =3D env->star; - break; - case MSR_PAT: - val =3D env->pat; - break; - case MSR_VM_HSAVE_PA: - val =3D env->vm_hsave; - break; - case MSR_IA32_PERF_STATUS: - /* tsc_increment_by_tick */ - val =3D 1000ULL; - /* CPU multiplier */ - val |=3D (((uint64_t)4ULL) << 40); - break; -#ifdef TARGET_X86_64 - case MSR_LSTAR: - val =3D env->lstar; - break; - case MSR_CSTAR: - val =3D env->cstar; - break; - case MSR_FMASK: - val =3D env->fmask; - break; - case MSR_FSBASE: - val =3D env->segs[R_FS].base; - break; - case MSR_GSBASE: - val =3D env->segs[R_GS].base; - break; - case MSR_KERNELGSBASE: - val =3D env->kernelgsbase; - break; - case MSR_TSC_AUX: - val =3D env->tsc_aux; - break; -#endif - case MSR_MTRRphysBase(0): - case MSR_MTRRphysBase(1): - case MSR_MTRRphysBase(2): - case MSR_MTRRphysBase(3): - case MSR_MTRRphysBase(4): - case MSR_MTRRphysBase(5): - case MSR_MTRRphysBase(6): - case MSR_MTRRphysBase(7): - val =3D env->mtrr_var[((uint32_t)env->regs[R_ECX] - - MSR_MTRRphysBase(0)) / 2].base; - break; - case MSR_MTRRphysMask(0): - case MSR_MTRRphysMask(1): - case MSR_MTRRphysMask(2): - case MSR_MTRRphysMask(3): - case MSR_MTRRphysMask(4): - case MSR_MTRRphysMask(5): - case MSR_MTRRphysMask(6): - case MSR_MTRRphysMask(7): - val =3D env->mtrr_var[((uint32_t)env->regs[R_ECX] - - MSR_MTRRphysMask(0)) / 2].mask; - break; - case MSR_MTRRfix64K_00000: - val =3D env->mtrr_fixed[0]; - break; - case MSR_MTRRfix16K_80000: - case MSR_MTRRfix16K_A0000: - val =3D env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - - MSR_MTRRfix16K_80000 + 1]; - break; - case MSR_MTRRfix4K_C0000: - case MSR_MTRRfix4K_C8000: - case MSR_MTRRfix4K_D0000: - case MSR_MTRRfix4K_D8000: - case MSR_MTRRfix4K_E0000: - case MSR_MTRRfix4K_E8000: - case MSR_MTRRfix4K_F0000: - case MSR_MTRRfix4K_F8000: - val =3D env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - - MSR_MTRRfix4K_C0000 + 3]; - break; - case MSR_MTRRdefType: - val =3D env->mtrr_deftype; - break; - case MSR_MTRRcap: - if (env->features[FEAT_1_EDX] & CPUID_MTRR) { - val =3D MSR_MTRRcap_VCNT | MSR_MTRRcap_FIXRANGE_SUPPORT | - MSR_MTRRcap_WC_SUPPORTED; - } else { - /* XXX: exception? */ - val =3D 0; - } - break; - case MSR_MCG_CAP: - val =3D env->mcg_cap; - break; - case MSR_MCG_CTL: - if (env->mcg_cap & MCG_CTL_P) { - val =3D env->mcg_ctl; - } else { - val =3D 0; - } - break; - case MSR_MCG_STATUS: - val =3D env->mcg_status; - break; - case MSR_IA32_MISC_ENABLE: - val =3D env->msr_ia32_misc_enable; - break; - case MSR_IA32_BNDCFGS: - val =3D env->msr_bndcfgs; - break; - default: - if ((uint32_t)env->regs[R_ECX] >=3D MSR_MC0_CTL - && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL + - (4 * env->mcg_cap & 0xff)) { - uint32_t offset =3D (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL; - val =3D env->mce_banks[offset]; - break; - } - /* XXX: exception? */ - val =3D 0; - break; - } - + uint64_t val =3D cpu_x86_read_msr(env); stq_p(&val, val); + m64c->DataValueLow =3D val; m64c->DataValueHigh =3D val >> 32; pd->m64.ReturnStatus =3D STATUS_SUCCESS; @@ -1230,162 +1089,8 @@ void kd_api_write_msr(CPUState *cpu, PacketData *pd) DBGKD_READ_WRITE_MSR *m64c =3D &pd->m64.u.ReadWriteMsr; CPUArchState *env =3D cpu->env_ptr; =20 - uint64_t val; - - cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 1, 0); - - val =3D m64c->DataValueLow | ((uint64_t) m64c->DataValueHigh) << 32; - val =3D ldq_p(&val); - - switch ((uint32_t)env->regs[R_ECX]) { - case MSR_IA32_SYSENTER_CS: - env->sysenter_cs =3D val & 0xffff; - break; - case MSR_IA32_SYSENTER_ESP: - env->sysenter_esp =3D val; - break; - case MSR_IA32_SYSENTER_EIP: - env->sysenter_eip =3D val; - break; - case MSR_IA32_APICBASE: - cpu_set_apic_base(x86_env_get_cpu(env)->apic_state, val); - break; - case MSR_EFER: - { - uint64_t update_mask; - - update_mask =3D 0; - if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_SYSCALL) { - update_mask |=3D MSR_EFER_SCE; - } - if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { - update_mask |=3D MSR_EFER_LME; - } - if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_FFXSR) { - update_mask |=3D MSR_EFER_FFXSR; - } - if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_NX) { - update_mask |=3D MSR_EFER_NXE; - } - if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { - update_mask |=3D MSR_EFER_SVME; - } - if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_FFXSR) { - update_mask |=3D MSR_EFER_FFXSR; - } - cpu_load_efer(env, (env->efer & ~update_mask) | - (val & update_mask)); - } - break; - case MSR_STAR: - env->star =3D val; - break; - case MSR_PAT: - env->pat =3D val; - break; - case MSR_VM_HSAVE_PA: - env->vm_hsave =3D val; - break; -#ifdef TARGET_X86_64 - case MSR_LSTAR: - env->lstar =3D val; - break; - case MSR_CSTAR: - env->cstar =3D val; - break; - case MSR_FMASK: - env->fmask =3D val; - break; - case MSR_FSBASE: - env->segs[R_FS].base =3D val; - break; - case MSR_GSBASE: - env->segs[R_GS].base =3D val; - break; - case MSR_KERNELGSBASE: - env->kernelgsbase =3D val; - break; -#endif - case MSR_MTRRphysBase(0): - case MSR_MTRRphysBase(1): - case MSR_MTRRphysBase(2): - case MSR_MTRRphysBase(3): - case MSR_MTRRphysBase(4): - case MSR_MTRRphysBase(5): - case MSR_MTRRphysBase(6): - case MSR_MTRRphysBase(7): - env->mtrr_var[((uint32_t)env->regs[R_ECX] - - MSR_MTRRphysBase(0)) / 2].base =3D val; - break; - case MSR_MTRRphysMask(0): - case MSR_MTRRphysMask(1): - case MSR_MTRRphysMask(2): - case MSR_MTRRphysMask(3): - case MSR_MTRRphysMask(4): - case MSR_MTRRphysMask(5): - case MSR_MTRRphysMask(6): - case MSR_MTRRphysMask(7): - env->mtrr_var[((uint32_t)env->regs[R_ECX] - - MSR_MTRRphysMask(0)) / 2].mask =3D val; - break; - case MSR_MTRRfix64K_00000: - env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - - MSR_MTRRfix64K_00000] =3D val; - break; - case MSR_MTRRfix16K_80000: - case MSR_MTRRfix16K_A0000: - env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - - MSR_MTRRfix16K_80000 + 1] =3D val; - break; - case MSR_MTRRfix4K_C0000: - case MSR_MTRRfix4K_C8000: - case MSR_MTRRfix4K_D0000: - case MSR_MTRRfix4K_D8000: - case MSR_MTRRfix4K_E0000: - case MSR_MTRRfix4K_E8000: - case MSR_MTRRfix4K_F0000: - case MSR_MTRRfix4K_F8000: - env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - - MSR_MTRRfix4K_C0000 + 3] =3D val; - break; - case MSR_MTRRdefType: - env->mtrr_deftype =3D val; - break; - case MSR_MCG_STATUS: - env->mcg_status =3D val; - break; - case MSR_MCG_CTL: - if ((env->mcg_cap & MCG_CTL_P) - && (val =3D=3D 0 || val =3D=3D ~(uint64_t)0)) { - env->mcg_ctl =3D val; - } - break; - case MSR_TSC_AUX: - env->tsc_aux =3D val; - break; - case MSR_IA32_MISC_ENABLE: - env->msr_ia32_misc_enable =3D val; - break; - case MSR_IA32_BNDCFGS: - /* FIXME: #GP if reserved bits are set. */ - /* FIXME: Extend highest implemented bit of linear address. */ - env->msr_bndcfgs =3D val; - cpu_sync_bndcs_hflags(env); - break; - default: - if ((uint32_t)env->regs[R_ECX] >=3D MSR_MC0_CTL - && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL + - (4 * env->mcg_cap & 0xff)) { - uint32_t offset =3D (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL; - if ((offset & 0x3) !=3D 0 - || (val =3D=3D 0 || val =3D=3D ~(uint64_t)0)) { - env->mce_banks[offset] =3D val; - } - break; - } - /* XXX: exception? */ - break; - } + uint64_t val =3D m64c->DataValueLow | ((uint64_t) m64c->DataValueHigh)= << 32; + cpu_x86_write_msr(env, ldq_p(&val)); =20 pd->m64.ReturnStatus =3D STATUS_SUCCESS; }