From nobody Tue Feb 10 10:57:20 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 151300036962910.83880385686382; Mon, 11 Dec 2017 05:52:49 -0800 (PST) Received: from localhost ([::1]:53161 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eOOVa-0008LO-TM for importer@patchew.org; Mon, 11 Dec 2017 08:52:38 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34849) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eOO5E-0004QN-Dj for qemu-devel@nongnu.org; Mon, 11 Dec 2017 08:25:29 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eOO57-0003r5-Mw for qemu-devel@nongnu.org; Mon, 11 Dec 2017 08:25:24 -0500 Received: from mail.ispras.ru ([83.149.199.45]:44166) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eOO57-0003pe-99 for qemu-devel@nongnu.org; Mon, 11 Dec 2017 08:25:17 -0500 Received: from Misha-PC.lan02.inno (unknown [85.142.117.226]) by mail.ispras.ru (Postfix) with ESMTPSA id 6903354006A; Mon, 11 Dec 2017 16:25:16 +0300 (MSK) From: Mihail Abakumov To: qemu-devel@nongnu.org Date: Mon, 11 Dec 2017 16:25:01 +0300 Message-ID: <151299870172.4808.15431911733778760401.stgit@Misha-PC.lan02.inno> In-Reply-To: <151299847127.4808.14646046517426494416.stgit@Misha-PC.lan02.inno> References: <151299847127.4808.14646046517426494416.stgit@Misha-PC.lan02.inno> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 83.149.199.45 Subject: [Qemu-devel] [PATCH v4 39/46] windbg: implemented kd_api_read_msr and kd_api_write_msr X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, lprosek@redhat.com, dovgaluk@ispras.ru, rkagan@virtuozzo.com, pbonzini@redhat.com, den@openvz.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Signed-off-by: Mihail Abakumov Signed-off-by: Pavel Dovgalyuk Signed-off-by: Dmitriy Koltunov --- include/exec/windbgstub-utils.h | 2=20 target/i386/windbgstub.c | 328 +++++++++++++++++++++++++++++++++++= ++++ windbgstub.c | 8 + 3 files changed, 338 insertions(+) diff --git a/include/exec/windbgstub-utils.h b/include/exec/windbgstub-util= s.h index 8cdb275555..6e73ef973c 100755 --- a/include/exec/windbgstub-utils.h +++ b/include/exec/windbgstub-utils.h @@ -88,6 +88,8 @@ void kd_api_write_io_space(CPUState *cpu, PacketData *pd); void kd_api_read_physical_memory(CPUState *cpu, PacketData *pd); void kd_api_write_physical_memory(CPUState *cpu, PacketData *pd); void kd_api_get_version(CPUState *cpu, PacketData *pd); +void kd_api_read_msr(CPUState *cpu, PacketData *pd); +void kd_api_write_msr(CPUState *cpu, PacketData *pd); void kd_api_unsupported(CPUState *cpu, PacketData *pd); =20 SizedBuf kd_gen_exception_sc(CPUState *cpu); diff --git a/target/i386/windbgstub.c b/target/i386/windbgstub.c index 5e094e81d7..7985dcfaf0 100755 --- a/target/i386/windbgstub.c +++ b/target/i386/windbgstub.c @@ -1007,6 +1007,334 @@ void kd_api_write_control_space(CPUState *cpu, Pack= etData *pd) stl_p(&mem->ActualBytesWritten, len); } =20 +#if defined(CONFIG_USER_ONLY) +void kd_api_read_msr(CPUState *cpu, PacketData *pd) +{ +} + +void kd_api_write_msr(CPUState *cpu, PacketData *pd) +{ +} +#else +void kd_api_read_msr(CPUState *cpu, PacketData *pd) +{ + DBGKD_READ_WRITE_MSR *m64c =3D &pd->m64.u.ReadWriteMsr; + CPUArchState *env =3D cpu->env_ptr; + + uint64_t val; + + cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 0, 0); + + switch ((uint32_t)env->regs[R_ECX]) { + case MSR_IA32_SYSENTER_CS: + val =3D env->sysenter_cs; + break; + case MSR_IA32_SYSENTER_ESP: + val =3D env->sysenter_esp; + break; + case MSR_IA32_SYSENTER_EIP: + val =3D env->sysenter_eip; + break; + case MSR_IA32_APICBASE: + val =3D cpu_get_apic_base(x86_env_get_cpu(env)->apic_state); + break; + case MSR_EFER: + val =3D env->efer; + break; + case MSR_STAR: + val =3D env->star; + break; + case MSR_PAT: + val =3D env->pat; + break; + case MSR_VM_HSAVE_PA: + val =3D env->vm_hsave; + break; + case MSR_IA32_PERF_STATUS: + /* tsc_increment_by_tick */ + val =3D 1000ULL; + /* CPU multiplier */ + val |=3D (((uint64_t)4ULL) << 40); + break; +#ifdef TARGET_X86_64 + case MSR_LSTAR: + val =3D env->lstar; + break; + case MSR_CSTAR: + val =3D env->cstar; + break; + case MSR_FMASK: + val =3D env->fmask; + break; + case MSR_FSBASE: + val =3D env->segs[R_FS].base; + break; + case MSR_GSBASE: + val =3D env->segs[R_GS].base; + break; + case MSR_KERNELGSBASE: + val =3D env->kernelgsbase; + break; + case MSR_TSC_AUX: + val =3D env->tsc_aux; + break; +#endif + case MSR_MTRRphysBase(0): + case MSR_MTRRphysBase(1): + case MSR_MTRRphysBase(2): + case MSR_MTRRphysBase(3): + case MSR_MTRRphysBase(4): + case MSR_MTRRphysBase(5): + case MSR_MTRRphysBase(6): + case MSR_MTRRphysBase(7): + val =3D env->mtrr_var[((uint32_t)env->regs[R_ECX] - + MSR_MTRRphysBase(0)) / 2].base; + break; + case MSR_MTRRphysMask(0): + case MSR_MTRRphysMask(1): + case MSR_MTRRphysMask(2): + case MSR_MTRRphysMask(3): + case MSR_MTRRphysMask(4): + case MSR_MTRRphysMask(5): + case MSR_MTRRphysMask(6): + case MSR_MTRRphysMask(7): + val =3D env->mtrr_var[((uint32_t)env->regs[R_ECX] - + MSR_MTRRphysMask(0)) / 2].mask; + break; + case MSR_MTRRfix64K_00000: + val =3D env->mtrr_fixed[0]; + break; + case MSR_MTRRfix16K_80000: + case MSR_MTRRfix16K_A0000: + val =3D env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - + MSR_MTRRfix16K_80000 + 1]; + break; + case MSR_MTRRfix4K_C0000: + case MSR_MTRRfix4K_C8000: + case MSR_MTRRfix4K_D0000: + case MSR_MTRRfix4K_D8000: + case MSR_MTRRfix4K_E0000: + case MSR_MTRRfix4K_E8000: + case MSR_MTRRfix4K_F0000: + case MSR_MTRRfix4K_F8000: + val =3D env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - + MSR_MTRRfix4K_C0000 + 3]; + break; + case MSR_MTRRdefType: + val =3D env->mtrr_deftype; + break; + case MSR_MTRRcap: + if (env->features[FEAT_1_EDX] & CPUID_MTRR) { + val =3D MSR_MTRRcap_VCNT | MSR_MTRRcap_FIXRANGE_SUPPORT | + MSR_MTRRcap_WC_SUPPORTED; + } else { + /* XXX: exception? */ + val =3D 0; + } + break; + case MSR_MCG_CAP: + val =3D env->mcg_cap; + break; + case MSR_MCG_CTL: + if (env->mcg_cap & MCG_CTL_P) { + val =3D env->mcg_ctl; + } else { + val =3D 0; + } + break; + case MSR_MCG_STATUS: + val =3D env->mcg_status; + break; + case MSR_IA32_MISC_ENABLE: + val =3D env->msr_ia32_misc_enable; + break; + case MSR_IA32_BNDCFGS: + val =3D env->msr_bndcfgs; + break; + default: + if ((uint32_t)env->regs[R_ECX] >=3D MSR_MC0_CTL + && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL + + (4 * env->mcg_cap & 0xff)) { + uint32_t offset =3D (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL; + val =3D env->mce_banks[offset]; + break; + } + /* XXX: exception? */ + val =3D 0; + break; + } + + stq_p(&val, val); + m64c->DataValueLow =3D val; + m64c->DataValueHigh =3D val >> 32; + pd->m64.ReturnStatus =3D STATUS_SUCCESS; +} + +void kd_api_write_msr(CPUState *cpu, PacketData *pd) +{ + DBGKD_READ_WRITE_MSR *m64c =3D &pd->m64.u.ReadWriteMsr; + CPUArchState *env =3D cpu->env_ptr; + + uint64_t val; + + cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 1, 0); + + val =3D m64c->DataValueLow | ((uint64_t) m64c->DataValueHigh) << 32; + val =3D ldq_p(&val); + + switch ((uint32_t)env->regs[R_ECX]) { + case MSR_IA32_SYSENTER_CS: + env->sysenter_cs =3D val & 0xffff; + break; + case MSR_IA32_SYSENTER_ESP: + env->sysenter_esp =3D val; + break; + case MSR_IA32_SYSENTER_EIP: + env->sysenter_eip =3D val; + break; + case MSR_IA32_APICBASE: + cpu_set_apic_base(x86_env_get_cpu(env)->apic_state, val); + break; + case MSR_EFER: + { + uint64_t update_mask; + + update_mask =3D 0; + if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_SYSCALL) { + update_mask |=3D MSR_EFER_SCE; + } + if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { + update_mask |=3D MSR_EFER_LME; + } + if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_FFXSR) { + update_mask |=3D MSR_EFER_FFXSR; + } + if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_NX) { + update_mask |=3D MSR_EFER_NXE; + } + if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { + update_mask |=3D MSR_EFER_SVME; + } + if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_FFXSR) { + update_mask |=3D MSR_EFER_FFXSR; + } + cpu_load_efer(env, (env->efer & ~update_mask) | + (val & update_mask)); + } + break; + case MSR_STAR: + env->star =3D val; + break; + case MSR_PAT: + env->pat =3D val; + break; + case MSR_VM_HSAVE_PA: + env->vm_hsave =3D val; + break; +#ifdef TARGET_X86_64 + case MSR_LSTAR: + env->lstar =3D val; + break; + case MSR_CSTAR: + env->cstar =3D val; + break; + case MSR_FMASK: + env->fmask =3D val; + break; + case MSR_FSBASE: + env->segs[R_FS].base =3D val; + break; + case MSR_GSBASE: + env->segs[R_GS].base =3D val; + break; + case MSR_KERNELGSBASE: + env->kernelgsbase =3D val; + break; +#endif + case MSR_MTRRphysBase(0): + case MSR_MTRRphysBase(1): + case MSR_MTRRphysBase(2): + case MSR_MTRRphysBase(3): + case MSR_MTRRphysBase(4): + case MSR_MTRRphysBase(5): + case MSR_MTRRphysBase(6): + case MSR_MTRRphysBase(7): + env->mtrr_var[((uint32_t)env->regs[R_ECX] - + MSR_MTRRphysBase(0)) / 2].base =3D val; + break; + case MSR_MTRRphysMask(0): + case MSR_MTRRphysMask(1): + case MSR_MTRRphysMask(2): + case MSR_MTRRphysMask(3): + case MSR_MTRRphysMask(4): + case MSR_MTRRphysMask(5): + case MSR_MTRRphysMask(6): + case MSR_MTRRphysMask(7): + env->mtrr_var[((uint32_t)env->regs[R_ECX] - + MSR_MTRRphysMask(0)) / 2].mask =3D val; + break; + case MSR_MTRRfix64K_00000: + env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - + MSR_MTRRfix64K_00000] =3D val; + break; + case MSR_MTRRfix16K_80000: + case MSR_MTRRfix16K_A0000: + env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - + MSR_MTRRfix16K_80000 + 1] =3D val; + break; + case MSR_MTRRfix4K_C0000: + case MSR_MTRRfix4K_C8000: + case MSR_MTRRfix4K_D0000: + case MSR_MTRRfix4K_D8000: + case MSR_MTRRfix4K_E0000: + case MSR_MTRRfix4K_E8000: + case MSR_MTRRfix4K_F0000: + case MSR_MTRRfix4K_F8000: + env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - + MSR_MTRRfix4K_C0000 + 3] =3D val; + break; + case MSR_MTRRdefType: + env->mtrr_deftype =3D val; + break; + case MSR_MCG_STATUS: + env->mcg_status =3D val; + break; + case MSR_MCG_CTL: + if ((env->mcg_cap & MCG_CTL_P) + && (val =3D=3D 0 || val =3D=3D ~(uint64_t)0)) { + env->mcg_ctl =3D val; + } + break; + case MSR_TSC_AUX: + env->tsc_aux =3D val; + break; + case MSR_IA32_MISC_ENABLE: + env->msr_ia32_misc_enable =3D val; + break; + case MSR_IA32_BNDCFGS: + /* FIXME: #GP if reserved bits are set. */ + /* FIXME: Extend highest implemented bit of linear address. */ + env->msr_bndcfgs =3D val; + cpu_sync_bndcs_hflags(env); + break; + default: + if ((uint32_t)env->regs[R_ECX] >=3D MSR_MC0_CTL + && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL + + (4 * env->mcg_cap & 0xff)) { + uint32_t offset =3D (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL; + if ((offset & 0x3) !=3D 0 + || (val =3D=3D 0 || val =3D=3D ~(uint64_t)0)) { + env->mce_banks[offset] =3D val; + } + break; + } + /* XXX: exception? */ + break; + } + + pd->m64.ReturnStatus =3D STATUS_SUCCESS; +} + bool windbg_on_load(void) { CPUState *cpu =3D qemu_get_cpu(0); diff --git a/windbgstub.c b/windbgstub.c index 06e99199b6..45f61917d9 100755 --- a/windbgstub.c +++ b/windbgstub.c @@ -197,6 +197,14 @@ static void windbg_process_manipulate_packet(ParsingCo= ntext *ctx) kd_api_write_physical_memory(cpu, &ctx->data); break; =20 + case DbgKdReadMachineSpecificRegister: + kd_api_read_msr(cpu, &ctx->data); + break; + + case DbgKdWriteMachineSpecificRegister: + kd_api_write_msr(cpu, &ctx->data); + break; + case DbgKdGetVersionApi: kd_api_get_version(cpu, &ctx->data); break;