From nobody Tue Feb 10 11:23:54 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1512503602985984.0960060669133; Tue, 5 Dec 2017 11:53:22 -0800 (PST) Received: from localhost ([::1]:51799 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eMJHJ-00085M-5M for importer@patchew.org; Tue, 05 Dec 2017 14:53:17 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56750) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eMJB7-000185-Vo for qemu-devel@nongnu.org; Tue, 05 Dec 2017 14:46:55 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eMJB6-0002Nv-TU for qemu-devel@nongnu.org; Tue, 05 Dec 2017 14:46:54 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:38776) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eMJB3-0002CW-TI; Tue, 05 Dec 2017 14:46:50 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eMJAq-0005AF-U6; Tue, 05 Dec 2017 19:46:36 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 5 Dec 2017 19:46:25 +0000 Message-Id: <1512503192-2239-6-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1512503192-2239-1-git-send-email-peter.maydell@linaro.org> References: <1512503192-2239-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 05/12] target/arm: Convert get_phys_addr_lpae() to not return FSC values X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , Stefano Stabellini , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Make get_phys_addr_v6() return a fault type in the ARMMMUFaultInfo structure, which we convert to the FSC at the callsite. Signed-off-by: Peter Maydell --- target/arm/helper.c | 41 ++++++++++++++++++----------------------- 1 file changed, 18 insertions(+), 23 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 1e95e3d..a2a0784 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -34,7 +34,7 @@ static bool get_phys_addr(CPUARMState *env, target_ulong = address, static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_id= x, hwaddr *phys_ptr, MemTxAttrs *txattrs, int = *prot, - target_ulong *page_size_ptr, uint32_t *fsr, + target_ulong *page_size_ptr, ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheat= trs); =20 /* Security attributes for an address, as returned by v8m_security_lookup.= */ @@ -8277,10 +8277,9 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARM= MMUIdx mmu_idx, hwaddr s2pa; int s2prot; int ret; - uint32_t fsr; =20 ret =3D get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_S2NS, &s2pa, - &txattrs, &s2prot, &s2size, &fsr, fi, NUL= L); + &txattrs, &s2prot, &s2size, fi, NULL); if (ret) { fi->s2addr =3D addr; fi->stage2 =3D true; @@ -8603,15 +8602,6 @@ do_fault: return true; } =20 -/* Fault type for long-descriptor MMU fault reporting; this corresponds - * to bits [5..2] in the STATUS field in long-format DFSR/IFSR. - */ -typedef enum { - translation_fault =3D 1, - access_fault =3D 2, - permission_fault =3D 3, -} MMUFaultType; - /* * check_s2_mmu_setup * @cpu: ARMCPU @@ -8713,13 +8703,13 @@ static uint8_t convert_stage2_attrs(CPUARMState *en= v, uint8_t s2attrs) static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_id= x, hwaddr *phys_ptr, MemTxAttrs *txattrs, int = *prot, - target_ulong *page_size_ptr, uint32_t *fsr, + target_ulong *page_size_ptr, ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheat= trs) { ARMCPU *cpu =3D arm_env_get_cpu(env); CPUState *cs =3D CPU(cpu); /* Read an LPAE long-descriptor translation table. */ - MMUFaultType fault_type =3D translation_fault; + ARMFaultType fault_type =3D ARMFault_Translation; uint32_t level; uint32_t epd =3D 0; int32_t t0sz, t1sz; @@ -8829,7 +8819,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, targ= et_ulong address, ttbr_select =3D 1; } else { /* in the gap between the two regions, this is a Translation fault= */ - fault_type =3D translation_fault; + fault_type =3D ARMFault_Translation; goto do_fault; } =20 @@ -8915,7 +8905,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, targ= et_ulong address, ok =3D check_s2_mmu_setup(cpu, aarch64, startlevel, inputsize, stride); if (!ok) { - fault_type =3D translation_fault; + fault_type =3D ARMFault_Translation; goto do_fault; } level =3D startlevel; @@ -9001,7 +8991,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, targ= et_ulong address, /* Here descaddr is the final physical address, and attributes * are all in attrs. */ - fault_type =3D access_fault; + fault_type =3D ARMFault_AccessFlag; if ((attrs & (1 << 8)) =3D=3D 0) { /* Access flag */ goto do_fault; @@ -9019,7 +9009,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, targ= et_ulong address, *prot =3D get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn); } =20 - fault_type =3D permission_fault; + fault_type =3D ARMFault_Permission; if (!(*prot & (1 << access_type))) { goto do_fault; } @@ -9051,8 +9041,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, targ= et_ulong address, return false; =20 do_fault: - /* Long-descriptor format IFSR/DFSR value */ - *fsr =3D (1 << 9) | (fault_type << 2) | level; + fi->type =3D fault_type; + fi->level =3D level; /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */ fi->stage2 =3D fi->s1ptw || (mmu_idx =3D=3D ARMMMUIdx_S2NS); return true; @@ -9778,8 +9768,9 @@ static bool get_phys_addr(CPUARMState *env, target_ul= ong address, /* S1 is done. Now do S2 translation. */ ret =3D get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_S2= NS, phys_ptr, attrs, &s2_prot, - page_size, fsr, fi, + page_size, fi, cacheattrs !=3D NULL ? &cacheattrs2 := NULL); + *fsr =3D arm_fi_to_lfsc(fi); fi->s2addr =3D ipa; /* Combine the S1 and S2 perms. */ *prot &=3D s2_prot; @@ -9858,8 +9849,12 @@ static bool get_phys_addr(CPUARMState *env, target_u= long address, } =20 if (regime_using_lpae_format(env, mmu_idx)) { - return get_phys_addr_lpae(env, address, access_type, mmu_idx, phys= _ptr, - attrs, prot, page_size, fsr, fi, cacheat= trs); + bool ret =3D get_phys_addr_lpae(env, address, access_type, mmu_idx, + phys_ptr, attrs, prot, page_size, + fi, cacheattrs); + + *fsr =3D arm_fi_to_lfsc(fi); + return ret; } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { bool ret =3D get_phys_addr_v6(env, address, access_type, mmu_idx, phys_ptr, attrs, prot, page_size, fi); --=20 2.7.4