From nobody Tue Feb 10 20:28:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1512503675010496.6868810140264; Tue, 5 Dec 2017 11:54:35 -0800 (PST) Received: from localhost ([::1]:51810 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eMJIU-0000l8-TP for importer@patchew.org; Tue, 05 Dec 2017 14:54:30 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56775) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eMJB8-00018s-Q2 for qemu-devel@nongnu.org; Tue, 05 Dec 2017 14:46:55 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eMJB7-0002OV-QD for qemu-devel@nongnu.org; Tue, 05 Dec 2017 14:46:54 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:38776) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eMJB4-0002CW-SI; Tue, 05 Dec 2017 14:46:51 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eMJAq-00059h-9b; Tue, 05 Dec 2017 19:46:36 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 5 Dec 2017 19:46:24 +0000 Message-Id: <1512503192-2239-5-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1512503192-2239-1-git-send-email-peter.maydell@linaro.org> References: <1512503192-2239-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 04/12] target/arm: Convert get_phys_addr_v6() to not return FSC values X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , Stefano Stabellini , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Make get_phys_addr_v6() return a fault type in the ARMMMUFaultInfo structure, which we convert to the FSC at the callsite. Signed-off-by: Peter Maydell --- target/arm/helper.c | 40 ++++++++++++++++++++++------------------ 1 file changed, 22 insertions(+), 18 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 6aed681..1e95e3d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8460,11 +8460,10 @@ do_fault: static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *attrs, int *pro= t, - target_ulong *page_size, uint32_t *fsr, - ARMMMUFaultInfo *fi) + target_ulong *page_size, ARMMMUFaultInfo *fi) { CPUState *cs =3D CPU(arm_env_get_cpu(env)); - int code; + int level =3D 1; uint32_t table; uint32_t desc; uint32_t xn; @@ -8481,7 +8480,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32= _t address, /* Lookup l1 descriptor. */ if (!get_level1_table_address(env, mmu_idx, &table, address)) { /* Section translation fault if page walk is disabled by PD0 or PD= 1 */ - code =3D 5; + fi->type =3D ARMFault_Translation; goto do_fault; } desc =3D arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), @@ -8491,7 +8490,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32= _t address, /* Section translation fault, or attempt to use the encoding * which is Reserved on implementations without PXN. */ - code =3D 5; + fi->type =3D ARMFault_Translation; goto do_fault; } if ((type =3D=3D 1) || !(desc & (1 << 18))) { @@ -8503,13 +8502,13 @@ static bool get_phys_addr_v6(CPUARMState *env, uint= 32_t address, } else { dacr =3D env->cp15.dacr_s; } + if (type =3D=3D 1) { + level =3D 2; + } domain_prot =3D (dacr >> (domain * 2)) & 3; if (domain_prot =3D=3D 0 || domain_prot =3D=3D 2) { - if (type !=3D 1) { - code =3D 9; /* Section domain fault. */ - } else { - code =3D 11; /* Page domain fault. */ - } + /* Section or Page domain fault */ + fi->type =3D ARMFault_Domain; goto do_fault; } if (type !=3D 1) { @@ -8527,7 +8526,6 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32= _t address, ap =3D ((desc >> 10) & 3) | ((desc >> 13) & 4); xn =3D desc & (1 << 4); pxn =3D desc & 1; - code =3D 13; ns =3D extract32(desc, 19, 1); } else { if (arm_feature(env, ARM_FEATURE_PXN)) { @@ -8541,7 +8539,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32= _t address, ap =3D ((desc >> 4) & 3) | ((desc >> 7) & 4); switch (desc & 3) { case 0: /* Page translation fault. */ - code =3D 7; + fi->type =3D ARMFault_Translation; goto do_fault; case 1: /* 64k page. */ phys_addr =3D (desc & 0xffff0000) | (address & 0xffff); @@ -8557,7 +8555,6 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32= _t address, /* Never happens, but compiler isn't smart enough to tell. */ abort(); } - code =3D 15; } if (domain_prot =3D=3D 3) { *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; @@ -8565,15 +8562,17 @@ static bool get_phys_addr_v6(CPUARMState *env, uint= 32_t address, if (pxn && !regime_is_user(env, mmu_idx)) { xn =3D 1; } - if (xn && access_type =3D=3D MMU_INST_FETCH) + if (xn && access_type =3D=3D MMU_INST_FETCH) { + fi->type =3D ARMFault_Permission; goto do_fault; + } =20 if (arm_feature(env, ARM_FEATURE_V6K) && (regime_sctlr(env, mmu_idx) & SCTLR_AFE)) { /* The simplified model uses AP[0] as an access control bit. = */ if ((ap & 1) =3D=3D 0) { /* Access flag fault. */ - code =3D (code =3D=3D 15) ? 6 : 3; + fi->type =3D ARMFault_AccessFlag; goto do_fault; } *prot =3D simple_ap_to_rw_prot(env, mmu_idx, ap >> 1); @@ -8585,6 +8584,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32= _t address, } if (!(*prot & (1 << access_type))) { /* Access permission fault. */ + fi->type =3D ARMFault_Permission; goto do_fault; } } @@ -8598,7 +8598,8 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32= _t address, *phys_ptr =3D phys_addr; return false; do_fault: - *fsr =3D code | (domain << 4); + fi->domain =3D domain; + fi->level =3D level; return true; } =20 @@ -9860,8 +9861,11 @@ static bool get_phys_addr(CPUARMState *env, target_u= long address, return get_phys_addr_lpae(env, address, access_type, mmu_idx, phys= _ptr, attrs, prot, page_size, fsr, fi, cacheat= trs); } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { - return get_phys_addr_v6(env, address, access_type, mmu_idx, phys_p= tr, - attrs, prot, page_size, fsr, fi); + bool ret =3D get_phys_addr_v6(env, address, access_type, mmu_idx, + phys_ptr, attrs, prot, page_size, fi); + + *fsr =3D arm_fi_to_sfsc(fi); + return ret; } else { bool ret =3D get_phys_addr_v5(env, address, access_type, mmu_idx, phys_ptr, prot, page_size, fi); --=20 2.7.4