From nobody Wed Feb 11 05:12:11 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1511700375801161.60858584120876; Sun, 26 Nov 2017 04:46:15 -0800 (PST) Received: from localhost ([::1]:56405 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eIwK5-0005LT-2t for importer@patchew.org; Sun, 26 Nov 2017 07:46:13 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53526) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eIwAY-0005c2-VN for qemu-devel@nongnu.org; Sun, 26 Nov 2017 07:36:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eIwAW-0006A1-RR for qemu-devel@nongnu.org; Sun, 26 Nov 2017 07:36:22 -0500 Received: from chuckie.co.uk ([82.165.15.123]:48689 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eIwAW-00068v-Kv for qemu-devel@nongnu.org; Sun, 26 Nov 2017 07:36:20 -0500 Received: from host86-189-155-83.range86-189.btcentralplus.com ([86.189.155.83] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1eIw9m-0004of-Bw; Sun, 26 Nov 2017 12:35:35 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, atar4qemu@gmail.com Date: Sun, 26 Nov 2017 12:34:42 +0000 Message-Id: <1511699686-12605-12-git-send-email-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1511699686-12605-1-git-send-email-mark.cave-ayland@ilande.co.uk> References: <1511699686-12605-1-git-send-email-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 86.189.155.83 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCHv2 11/15] apb: split pci_pbm_map_irq() into separate functions for bus A and bus B X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" After the previous refactoring it is now possible to use separate functions to improve clarity of the interrupt paths. Similarly by checking the PCI devnfn to identify busA during apb_pci_bridge_realize() it becomes possible to completely remove the busA property from the PBMPCIBridge state. Signed-off-by: Mark Cave-Ayland --- hw/pci-host/apb.c | 60 +++++++++++++++++++----------------------= ---- include/hw/pci-host/apb.h | 3 --- 2 files changed, 25 insertions(+), 38 deletions(-) diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c index 6c20285..d260db3 100644 --- a/hw/pci-host/apb.c +++ b/hw/pci-host/apb.c @@ -517,32 +517,27 @@ static int pci_apb_map_irq(PCIDevice *pci_dev, int ir= q_num) return irq_num; } =20 -static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num) +static int pci_pbmA_map_irq(PCIDevice *pci_dev, int irq_num) { - PBMPCIBridge *br =3D PBM_PCI_BRIDGE(pci_bridge_get_device( - PCI_BUS(qdev_get_parent_bus(DEVICE(pci_dev))))); - - int bus_offset; - if (br->busA) { - bus_offset =3D 0x0; + /* The on-board devices have fixed (legacy) OBIO intnos */ + switch (PCI_SLOT(pci_dev->devfn)) { + case 1: + /* Onboard NIC */ + return 0x21; + case 3: + /* Onboard IDE */ + return 0x20; + default: + /* Normal intno, fall through */ + break; + } =20 - /* The on-board devices have fixed (legacy) OBIO intnos */ - switch (PCI_SLOT(pci_dev->devfn)) { - case 1: - /* Onboard NIC */ - return 0x21; - case 3: - /* Onboard IDE */ - return 0x20; + return ((PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f; +} =20 - default: - /* Normal intno, fall through */ - break; - } - } else { - bus_offset =3D 0x10; - } - return (bus_offset + (PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f; +static int pci_pbmB_map_irq(PCIDevice *pci_dev, int irq_num) +{ + return (0x10 + (PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f; } =20 static void pci_apb_set_irq(void *opaque, int irq_num, int level) @@ -591,9 +586,11 @@ static void apb_pci_bridge_realize(PCIDevice *dev, Err= or **errp) =20 pci_bridge_initfn(dev, TYPE_PCI_BUS); =20 - /* If initialising busA, ensure that we allow IO transactions so that - we get the early serial console until OpenBIOS configures the bridg= e */ - if (br->busA) { + /* If this is the busA PCI bridge which contains the on-board devices + * attached to the ebus, ensure that we initially allow IO transactions + * so that we get the early serial console until OpenBIOS can properly + * configure the PCI bridge itself */ + if (dev->devfn =3D=3D PCI_DEVFN(1, 1)) { cmd |=3D PCI_COMMAND_IO; } =20 @@ -673,14 +670,13 @@ static void pci_pbm_realize(DeviceState *dev, Error *= *errp) pci_dev =3D pci_create_multifunction(phb->bus, PCI_DEVFN(1, 0), true, TYPE_PBM_PCI_BRIDGE); s->bridgeB =3D PCI_BRIDGE(pci_dev); - pci_bridge_map_irq(s->bridgeB, "pciB", pci_pbm_map_irq); + pci_bridge_map_irq(s->bridgeB, "pciB", pci_pbmB_map_irq); qdev_init_nofail(&pci_dev->qdev); =20 pci_dev =3D pci_create_multifunction(phb->bus, PCI_DEVFN(1, 1), true, TYPE_PBM_PCI_BRIDGE); s->bridgeA =3D PCI_BRIDGE(pci_dev); - pci_bridge_map_irq(s->bridgeA, "pciA", pci_pbm_map_irq); - qdev_prop_set_bit(DEVICE(pci_dev), "busA", true); + pci_bridge_map_irq(s->bridgeA, "pciA", pci_pbmA_map_irq); qdev_init_nofail(&pci_dev->qdev); } =20 @@ -789,11 +785,6 @@ static const TypeInfo pbm_host_info =3D { .class_init =3D pbm_host_class_init, }; =20 -static Property pbm_pci_properties[] =3D { - DEFINE_PROP_BOOL("busA", PBMPCIBridge, busA, false), - DEFINE_PROP_END_OF_LIST(), -}; - static void pbm_pci_bridge_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -809,7 +800,6 @@ static void pbm_pci_bridge_class_init(ObjectClass *klas= s, void *data) set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); dc->reset =3D pci_bridge_reset; dc->vmsd =3D &vmstate_pci_device; - dc->props =3D pbm_pci_properties; } =20 static const TypeInfo pbm_pci_bridge_info =3D { diff --git a/include/hw/pci-host/apb.h b/include/hw/pci-host/apb.h index f0074f7..dd49437 100644 --- a/include/hw/pci-host/apb.h +++ b/include/hw/pci-host/apb.h @@ -86,9 +86,6 @@ typedef struct APBState { typedef struct PBMPCIBridge { /*< private >*/ PCIBridge parent_obj; - - /* Is this busA with in-built devices (ebus)? */ - bool busA; } PBMPCIBridge; =20 #define TYPE_PBM_PCI_BRIDGE "pbm-bridge" --=20 1.7.10.4