From nobody Tue Feb 10 09:02:08 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1511199686677657.4528852499036; Mon, 20 Nov 2017 09:41:26 -0800 (PST) Received: from localhost ([::1]:58601 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eGq4K-0002TQ-Ue for importer@patchew.org; Mon, 20 Nov 2017 12:41:16 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37497) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eGq0g-0008HH-Qb for qemu-devel@nongnu.org; Mon, 20 Nov 2017 12:37:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eGq0f-0006IQ-K7 for qemu-devel@nongnu.org; Mon, 20 Nov 2017 12:37:30 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:38454) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eGq0f-0006H1-Bf for qemu-devel@nongnu.org; Mon, 20 Nov 2017 12:37:29 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eGq0e-0006Nv-Am for qemu-devel@nongnu.org; Mon, 20 Nov 2017 17:37:28 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 20 Nov 2017 17:37:23 +0000 Message-Id: <1511199444-17922-5-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1511199444-17922-1-git-send-email-peter.maydell@linaro.org> References: <1511199444-17922-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 4/5] hw/arm/aspeed: Unlock SCU when running kernel X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 From: Joel Stanley The ASPEED hardware contains a lock register for the SCU that disables any writes to the SCU when it is locked. The machine comes up with the lock enabled, but on all known hardware u-boot will unlock it and leave it unlocked when loading the kernel. This means the kernel expects the SCU to be unlocked. When booting from an emulated ROM the normal u-boot unlock path is executed. Things don't go well when booting using the -kernel command line, as u-boot does not run first. Change behaviour so that when a kernel is passed to the machine, set the reset value of the SCU to be unlocked. Signed-off-by: Joel Stanley Reviewed-by: C=C3=A9dric Le Goater Message-id: 20171114122018.12204-1-joel@jms.id.au Signed-off-by: Peter Maydell --- include/hw/misc/aspeed_scu.h | 3 +++ hw/arm/aspeed.c | 9 +++++++++ hw/arm/aspeed_soc.c | 2 ++ hw/misc/aspeed_scu.c | 5 +++-- 4 files changed, 17 insertions(+), 2 deletions(-) diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h index bd4ac01..d70cc0a 100644 --- a/include/hw/misc/aspeed_scu.h +++ b/include/hw/misc/aspeed_scu.h @@ -29,6 +29,7 @@ typedef struct AspeedSCUState { uint32_t silicon_rev; uint32_t hw_strap1; uint32_t hw_strap2; + uint32_t hw_prot_key; } AspeedSCUState; =20 #define AST2400_A0_SILICON_REV 0x02000303U @@ -38,6 +39,8 @@ typedef struct AspeedSCUState { =20 extern bool is_supported_silicon_rev(uint32_t silicon_rev); =20 +#define ASPEED_SCU_PROT_KEY 0x1688A8A8 + /* * Extracted from Aspeed SDK v00.03.21. Fixes and extra definitions * were added. diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index ab895ad..7088c90 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -186,6 +186,15 @@ static void aspeed_board_init(MachineState *machine, &error_abort); object_property_set_int(OBJECT(&bmc->soc), cfg->num_cs, "num-cs", &error_abort); + if (machine->kernel_filename) { + /* + * When booting with a -kernel command line there is no u-boot + * that runs to unlock the SCU. In this case set the default to + * be unlocked as the kernel expects + */ + object_property_set_int(OBJECT(&bmc->soc), ASPEED_SCU_PROT_KEY, + "hw-prot-key", &error_abort); + } object_property_set_bool(OBJECT(&bmc->soc), true, "realized", &error_abort); =20 diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 5aa3d2d..c83b7e2 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -154,6 +154,8 @@ static void aspeed_soc_init(Object *obj) "hw-strap1", &error_abort); object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), "hw-strap2", &error_abort); + object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), + "hw-prot-key", &error_abort); =20 object_initialize(&s->fmc, sizeof(s->fmc), sc->info->fmc_typename); object_property_add_child(obj, "fmc", OBJECT(&s->fmc), NULL); diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 95022d3..74537ce 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -85,7 +85,6 @@ #define BMC_REV TO_REG(0x19C) #define BMC_DEV_ID TO_REG(0x1A4) =20 -#define PROT_KEY_UNLOCK 0x1688A8A8 #define SCU_IO_REGION_SIZE 0x1000 =20 static const uint32_t ast2400_a0_resets[ASPEED_SCU_NR_REGS] =3D { @@ -192,7 +191,7 @@ static void aspeed_scu_write(void *opaque, hwaddr offse= t, uint64_t data, } =20 if (reg > PROT_KEY && reg < CPU2_BASE_SEG1 && - s->regs[PROT_KEY] !=3D PROT_KEY_UNLOCK) { + s->regs[PROT_KEY] !=3D ASPEED_SCU_PROT_KEY) { qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__); return; } @@ -246,6 +245,7 @@ static void aspeed_scu_reset(DeviceState *dev) s->regs[SILICON_REV] =3D s->silicon_rev; s->regs[HW_STRAP1] =3D s->hw_strap1; s->regs[HW_STRAP2] =3D s->hw_strap2; + s->regs[PROT_KEY] =3D s->hw_prot_key; } =20 static uint32_t aspeed_silicon_revs[] =3D { @@ -299,6 +299,7 @@ static Property aspeed_scu_properties[] =3D { DEFINE_PROP_UINT32("silicon-rev", AspeedSCUState, silicon_rev, 0), DEFINE_PROP_UINT32("hw-strap1", AspeedSCUState, hw_strap1, 0), DEFINE_PROP_UINT32("hw-strap2", AspeedSCUState, hw_strap2, 0), + DEFINE_PROP_UINT32("hw-prot-key", AspeedSCUState, hw_prot_key, 0), DEFINE_PROP_END_OF_LIST(), }; =20 --=20 2.7.4