From nobody Tue Feb 10 03:37:15 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1510343897526808.6222373562773; Fri, 10 Nov 2017 11:58:17 -0800 (PST) Received: from localhost ([::1]:43268 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eDFRM-0000Lg-Ql for importer@patchew.org; Fri, 10 Nov 2017 14:58:12 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47364) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eDFNC-0005Nx-VR for qemu-devel@nongnu.org; Fri, 10 Nov 2017 14:53:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eDFNC-0006F9-1b for qemu-devel@nongnu.org; Fri, 10 Nov 2017 14:53:55 -0500 Received: from out4-smtp.messagingengine.com ([66.111.4.28]:49123) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eDFN5-0006Af-8g; Fri, 10 Nov 2017 14:53:47 -0500 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id C6BB02126E; Fri, 10 Nov 2017 14:53:46 -0500 (EST) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Fri, 10 Nov 2017 14:53:46 -0500 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 9157624631; Fri, 10 Nov 2017 14:53:46 -0500 (EST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc; s=mesmtp; bh=GICqql91n8/XxF +zmvhStmbEqTisJhB0HxKda0g+MjY=; b=lOMgzNX3e1KJN1nnHCzr7xITvaW2YS cE6TRgb17uawKghqzIYLyu6ynpQNEylWWf/CJc3Uott/9Ke22M4KyL7NQ3D1BK5B 9QSRPJjhSDn8wmP3gfysfYiOT9cPNdif3PHCym/pt84l6kKJpJ/uLDu4DDXSqG1s FBa7gJlnkCYQ8= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc; s= fm1; bh=GICqql91n8/XxF+zmvhStmbEqTisJhB0HxKda0g+MjY=; b=D4FbCn0K PaZhF6rhkM4NZAlSeLBh+xXewvJVaJIHHWF5LbMsi2txL0THdzgA+mFDr7UscIqq vEUwMTPHZ9YY8PZ5BTfBk2rjpNP2+mUClfPf4quYPWNVbOfE/JD0CsmlCWFUXGBp cugZJBeC1kJYBMqTTRTfMTAqWoNTLECMWel3+sTi2fodPa/CZaEvto0Ky3lt4Yir T4jvC7OvdGVg3SXPzDpq4Y+sorfqIM/HlP0WJMm5mQ66gP85TH69QCA31pCFuI/H bap+nyTWSewDGkefPnJoGZZSSNgufLk56jPhPuGWqF2/ZTo3PIPHKNWALlzZ0pV2 vNos6n9hpTNT1g== X-ME-Sender: From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Fri, 10 Nov 2017 14:53:42 -0500 Message-Id: <1510343626-25861-2-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1510343626-25861-1-git-send-email-cota@braap.org> References: <1510343626-25861-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.28 Subject: [Qemu-devel] [PATCH for 2.11 1/5] qom: move CPUClass.tcg_initialize to a global X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Thomas Huth , Eduardo Habkost , Igor Mitsyanko , Richard Henderson , Alistair Francis , qemu-arm@nongnu.org, Marcel Apfelbaum , "Edgar E . Iglesias" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" 55c3cee ("qom: Introduce CPUClass.tcg_initialize", 2017-10-24) introduces a per-CPUClass bool that we check so that the target CPU is initialized for TCG only once. This works well except when we end up creating more than one CPUClass, in which case we end up incorrectly initializing TCG more than once, i.e. once for each CPUClass. This can be replicated with: $ aarch64-softmmu/qemu-system-aarch64 -machine xlnx-zcu102 -smp 6 \ -global driver=3Dxlnx,,zynqmp,property=3Dhas_rpu,value=3Don In this case the class name of the "RPUs" is prefixed by "cortex-r5-", whereas the "regular" CPUs are prefixed by "cortex-a53-". This results in two CPUClass instances being created. Fix it by introducing a static variable, so that only the first target CPU being initialized will initialize the target-dependent part of TCG, regardless of CPUClass instances. Fixes: 55c3ceef61fcf06fc98ddc752b7cce788ce7680b Signed-off-by: Emilio G. Cota Reviewed-by: Alistair Francis Reviewed-by: Eduardo Habkost Reviewed-by: Richard Henderson Tested-by: Alistair Francis --- include/qom/cpu.h | 1 - exec.c | 5 +++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/include/qom/cpu.h b/include/qom/cpu.h index fa4b0c9..c2fa151 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -209,7 +209,6 @@ typedef struct CPUClass { /* Keep non-pointer data at the end to minimize holes. */ int gdb_num_core_regs; bool gdb_stop_before_watchpoint; - bool tcg_initialized; } CPUClass; =20 #ifdef HOST_WORDS_BIGENDIAN diff --git a/exec.c b/exec.c index 97a24a8..8b579c0 100644 --- a/exec.c +++ b/exec.c @@ -792,11 +792,12 @@ void cpu_exec_initfn(CPUState *cpu) void cpu_exec_realizefn(CPUState *cpu, Error **errp) { CPUClass *cc =3D CPU_GET_CLASS(cpu); + static bool tcg_target_initialized; =20 cpu_list_add(cpu); =20 - if (tcg_enabled() && !cc->tcg_initialized) { - cc->tcg_initialized =3D true; + if (tcg_enabled() && !tcg_target_initialized) { + tcg_target_initialized =3D true; cc->tcg_initialize(); } =20 --=20 2.7.4