From nobody Sun May 5 01:56:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1510141091528156.48408822319482; Wed, 8 Nov 2017 03:38:11 -0800 (PST) Received: from localhost ([::1]:59010 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eCOgJ-0007GR-MD for importer@patchew.org; Wed, 08 Nov 2017 06:38:07 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33858) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eCOcd-0004wa-Rc for qemu-devel@nongnu.org; Wed, 08 Nov 2017 06:34:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eCOcZ-0002yd-E4 for qemu-devel@nongnu.org; Wed, 08 Nov 2017 06:34:19 -0500 Received: from mel.act-europe.fr ([2a02:2ab8:224:1::a0a:d2]:50779 helo=smtp.eu.adacore.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eCOcZ-0002xX-4Y for qemu-devel@nongnu.org; Wed, 08 Nov 2017 06:34:15 -0500 Received: from localhost (localhost [127.0.0.1]) by filtered-smtp.eu.adacore.com (Postfix) with ESMTP id B489181C43; Wed, 8 Nov 2017 12:34:12 +0100 (CET) Received: from smtp.eu.adacore.com ([127.0.0.1]) by localhost (smtp.eu.adacore.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id m6bwVbE0dLPr; Wed, 8 Nov 2017 12:34:12 +0100 (CET) Received: from wifi-guest-96.act-europe.fr (wifi-guest-96.act-europe.fr [10.10.126.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.eu.adacore.com (Postfix) with ESMTPSA id 920D28223C; Wed, 8 Nov 2017 12:34:12 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at eu.adacore.com From: KONRAD Frederic To: qemu-devel@nongnu.org Date: Wed, 8 Nov 2017 12:32:42 +0100 Message-Id: <1510140763-18256-2-git-send-email-frederic.konrad@adacore.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1510140763-18256-1-git-send-email-frederic.konrad@adacore.com> References: <1510140763-18256-1-git-send-email-frederic.konrad@adacore.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 2a02:2ab8:224:1::a0a:d2 Subject: [Qemu-devel] [PATCH for-2.12 1/2] cadence_ttc: extract CadenceTTCState to a new header file X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, edgar.iglesias@gmail.com, frederic.konrad@adacore.com, alistair.francis@xilinx.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We want to add this model to the xlnx-zynqmp board so let's make CadenceTTCState available in an header file. Signed-off-by: KONRAD Frederic --- hw/timer/cadence_ttc.c | 35 +----------------------- include/hw/timer/cadence_ttc.h | 61 ++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 62 insertions(+), 34 deletions(-) create mode 100644 include/hw/timer/cadence_ttc.h diff --git a/hw/timer/cadence_ttc.c b/hw/timer/cadence_ttc.c index 03f5b9c..bb4a5ef 100644 --- a/hw/timer/cadence_ttc.c +++ b/hw/timer/cadence_ttc.c @@ -16,9 +16,7 @@ * with this program; if not, see . */ =20 -#include "qemu/osdep.h" -#include "hw/sysbus.h" -#include "qemu/timer.h" +#include "hw/timer/cadence_ttc.h" =20 #ifdef CADENCE_TTC_ERR_DEBUG #define DB_PRINT(...) do { \ @@ -45,37 +43,6 @@ #define CLOCK_CTRL_PS_EN 0x00000001 #define CLOCK_CTRL_PS_V 0x0000001e =20 -typedef struct { - QEMUTimer *timer; - int freq; - - uint32_t reg_clock; - uint32_t reg_count; - uint32_t reg_value; - uint16_t reg_interval; - uint16_t reg_match[3]; - uint32_t reg_intr; - uint32_t reg_intr_en; - uint32_t reg_event_ctrl; - uint32_t reg_event; - - uint64_t cpu_time; - unsigned int cpu_time_valid; - - qemu_irq irq; -} CadenceTimerState; - -#define TYPE_CADENCE_TTC "cadence_ttc" -#define CADENCE_TTC(obj) \ - OBJECT_CHECK(CadenceTTCState, (obj), TYPE_CADENCE_TTC) - -typedef struct CadenceTTCState { - SysBusDevice parent_obj; - - MemoryRegion iomem; - CadenceTimerState timer[3]; -} CadenceTTCState; - static void cadence_timer_update(CadenceTimerState *s) { qemu_set_irq(s->irq, !!(s->reg_intr & s->reg_intr_en)); diff --git a/include/hw/timer/cadence_ttc.h b/include/hw/timer/cadence_ttc.h new file mode 100644 index 0000000..0c38789 --- /dev/null +++ b/include/hw/timer/cadence_ttc.h @@ -0,0 +1,61 @@ +/* + * Xilinx Zynq cadence TTC model + * + * Copyright (c) 2011 Xilinx Inc. + * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.= com) + * Copyright (c) 2012 PetaLogix Pty Ltd. + * Written By Haibing Ma + * M. Habib + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef CADENCE_TTC_H +#define CADENCE_TTC_H + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "qemu/timer.h" + +struct CadenceTimerState { + QEMUTimer *timer; + int freq; + + uint32_t reg_clock; + uint32_t reg_count; + uint32_t reg_value; + uint16_t reg_interval; + uint16_t reg_match[3]; + uint32_t reg_intr; + uint32_t reg_intr_en; + uint32_t reg_event_ctrl; + uint32_t reg_event; + + uint64_t cpu_time; + unsigned int cpu_time_valid; + + qemu_irq irq; +}; + +typedef struct CadenceTimerState CadenceTimerState; + +struct CadenceTTCState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + CadenceTimerState timer[3]; +}; + +typedef struct CadenceTTCState CadenceTTCState; + +#define TYPE_CADENCE_TTC "cadence_ttc" +#define CADENCE_TTC(obj) \ + OBJECT_CHECK(CadenceTTCState, (obj), TYPE_CADENCE_TTC) + +#endif /* CADENCE_TTC_H */ --=20 1.8.3.1 From nobody Sun May 5 01:56:09 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 15101409670421016.1691199455956; Wed, 8 Nov 2017 03:36:07 -0800 (PST) Received: from localhost ([::1]:59002 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eCOe4-0005cy-7o for importer@patchew.org; Wed, 08 Nov 2017 06:35:48 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33838) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eCOca-0004w9-Um for qemu-devel@nongnu.org; Wed, 08 Nov 2017 06:34:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eCOca-0002z7-1n for qemu-devel@nongnu.org; Wed, 08 Nov 2017 06:34:16 -0500 Received: from mel.act-europe.fr ([2a02:2ab8:224:1::a0a:d2]:50776 helo=smtp.eu.adacore.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eCOcZ-0002xY-Mu for qemu-devel@nongnu.org; Wed, 08 Nov 2017 06:34:15 -0500 Received: from localhost (localhost [127.0.0.1]) by filtered-smtp.eu.adacore.com (Postfix) with ESMTP id BD3DF8223C; Wed, 8 Nov 2017 12:34:12 +0100 (CET) Received: from smtp.eu.adacore.com ([127.0.0.1]) by localhost (smtp.eu.adacore.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id dasiZoHsu3dT; Wed, 8 Nov 2017 12:34:12 +0100 (CET) Received: from wifi-guest-96.act-europe.fr (wifi-guest-96.act-europe.fr [10.10.126.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.eu.adacore.com (Postfix) with ESMTPSA id A41AA82267; Wed, 8 Nov 2017 12:34:12 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at eu.adacore.com From: KONRAD Frederic To: qemu-devel@nongnu.org Date: Wed, 8 Nov 2017 12:32:43 +0100 Message-Id: <1510140763-18256-3-git-send-email-frederic.konrad@adacore.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1510140763-18256-1-git-send-email-frederic.konrad@adacore.com> References: <1510140763-18256-1-git-send-email-frederic.konrad@adacore.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 2a02:2ab8:224:1::a0a:d2 Subject: [Qemu-devel] [PATCH for-2.12 2/2] xlnx-zynqmp: add the timers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, edgar.iglesias@gmail.com, frederic.konrad@adacore.com, alistair.francis@xilinx.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This adds the TTC to the xlnx-zynqmp board according to the ultrascale TRM. Signed-off-by: KONRAD Frederic --- hw/arm/xlnx-zynqmp.c | 25 +++++++++++++++++++++++++ include/hw/arm/xlnx-zynqmp.h | 3 +++ 2 files changed, 28 insertions(+) diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 2b27daf..bd26a46 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -78,6 +78,14 @@ static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] =3D { 19, 20, }; =20 +static const uint64_t ttc_addr[XLNX_ZYNQMP_NUM_TTC] =3D { + 0xFF110000, 0xFF120000, 0xFF130000, 0xFF140000, +}; + +static const uint64_t ttc_intr[XLNX_ZYNQMP_NUM_TTC] =3D { + 36, 39, 42, 45, +}; + typedef struct XlnxZynqMPGICRegion { int region_index; uint32_t address; @@ -174,6 +182,11 @@ static void xlnx_zynqmp_init(Object *obj) =20 object_initialize(&s->dpdma, sizeof(s->dpdma), TYPE_XLNX_DPDMA); qdev_set_parent_bus(DEVICE(&s->dpdma), sysbus_get_default()); + + for (i =3D 0; i < XLNX_ZYNQMP_NUM_TTC; i++) { + object_initialize(&s->ttc[i], sizeof(s->ttc[i]), TYPE_CADENCE_TTC); + qdev_set_parent_bus(DEVICE(&s->ttc[i]), sysbus_get_default()); + } } =20 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) @@ -422,6 +435,18 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Erro= r **errp) &error_abort); sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR); sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]); + + for (i =3D 0; i < XLNX_ZYNQMP_NUM_TTC; i++) { + object_property_set_bool(OBJECT(&s->ttc[i]), true, "realized", &er= r); + + if (err) { + error_propagate(errp, err); + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ttc[i]), 0, ttc_addr[i]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->ttc[i]), 0, + gic_spi[ttc_intr[i]]); + } } =20 static Property xlnx_zynqmp_props[] =3D { diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 6eff81a..9a20f6e 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -28,6 +28,7 @@ #include "hw/ssi/xilinx_spips.h" #include "hw/dma/xlnx_dpdma.h" #include "hw/display/xlnx_dp.h" +#include "hw/timer/cadence_ttc.h" =20 #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp" #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \ @@ -39,6 +40,7 @@ #define XLNX_ZYNQMP_NUM_UARTS 2 #define XLNX_ZYNQMP_NUM_SDHCI 2 #define XLNX_ZYNQMP_NUM_SPIS 2 +#define XLNX_ZYNQMP_NUM_TTC 4 =20 #define XLNX_ZYNQMP_NUM_OCM_BANKS 4 #define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000 @@ -85,6 +87,7 @@ typedef struct XlnxZynqMPState { XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS]; XlnxDPState dp; XlnxDPDMAState dpdma; + CadenceTTCState ttc[XLNX_ZYNQMP_NUM_TTC]; =20 char *boot_cpu; ARMCPU *boot_cpu_ptr; --=20 1.8.3.1