From nobody Tue May 7 11:56:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1510061921493882.2279313773581; Tue, 7 Nov 2017 05:38:41 -0800 (PST) Received: from localhost ([::1]:53484 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eC45Q-0000Ti-LX for importer@patchew.org; Tue, 07 Nov 2017 08:38:40 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36774) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eC41l-0006Vp-9U for qemu-devel@nongnu.org; Tue, 07 Nov 2017 08:34:55 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eC41j-0005uj-Ga for qemu-devel@nongnu.org; Tue, 07 Nov 2017 08:34:53 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:38238) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eC41j-0005rx-4q for qemu-devel@nongnu.org; Tue, 07 Nov 2017 08:34:51 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eC41g-0004ST-Uj for qemu-devel@nongnu.org; Tue, 07 Nov 2017 13:34:48 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 7 Nov 2017 13:35:16 +0000 Message-Id: <1510061722-14092-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1510061722-14092-1-git-send-email-peter.maydell@linaro.org> References: <1510061722-14092-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 1/7] arm: implement cache/shareability attribute bits for PAR registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Andrew Baumann On a successful address translation instruction, PAR is supposed to contain cacheability and shareability attributes determined by the translation. We previously returned 0 for these bits (in line with the general strategy of ignoring caches and memory attributes), but some guest OSes may depend on them. This patch collects the attribute bits in the page-table walk, and updates PAR with the correct attributes for all LPAE translations. Short descriptor formats still return 0 for these bits, as in the prior implementation. Signed-off-by: Andrew Baumann Message-id: 20171031223830.4608-1-Andrew.Baumann@microsoft.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.c | 178 +++++++++++++++++++++++++++++++++++++++++++++++-= ---- 1 file changed, 164 insertions(+), 14 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 96113fe..f61fb3e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -19,17 +19,23 @@ #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ =20 #ifndef CONFIG_USER_ONLY +/* Cacheability and shareability attributes for a memory access */ +typedef struct ARMCacheAttrs { + unsigned int attrs:8; /* as in the MAIR register encoding */ + unsigned int shareability:2; /* as in the SH field of the VMSAv8-64 PT= Es */ +} ARMCacheAttrs; + static bool get_phys_addr(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, target_ulong *page_size, uint32_t *fsr, - ARMMMUFaultInfo *fi); + ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs); =20 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_id= x, hwaddr *phys_ptr, MemTxAttrs *txattrs, int = *prot, target_ulong *page_size_ptr, uint32_t *fsr, - ARMMMUFaultInfo *fi); + ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheat= trs); =20 /* Security attributes for an address, as returned by v8m_security_lookup.= */ typedef struct V8M_SAttributes { @@ -2159,9 +2165,10 @@ static uint64_t do_ats_write(CPUARMState *env, uint6= 4_t value, uint64_t par64; MemTxAttrs attrs =3D {}; ARMMMUFaultInfo fi =3D {}; + ARMCacheAttrs cacheattrs =3D {}; =20 - ret =3D get_phys_addr(env, value, access_type, mmu_idx, - &phys_addr, &attrs, &prot, &page_size, &fsr, &fi); + ret =3D get_phys_addr(env, value, access_type, mmu_idx, &phys_addr, &a= ttrs, + &prot, &page_size, &fsr, &fi, &cacheattrs); if (extended_addresses_enabled(env)) { /* fsr is a DFSR/IFSR value for the long descriptor * translation table format, but with WnR always clear. @@ -2173,7 +2180,8 @@ static uint64_t do_ats_write(CPUARMState *env, uint64= _t value, if (!attrs.secure) { par64 |=3D (1 << 9); /* NS */ } - /* We don't set the ATTR or SH fields in the PAR. */ + par64 |=3D (uint64_t)cacheattrs.attrs << 56; /* ATTR */ + par64 |=3D cacheattrs.shareability << 7; /* SH */ } else { par64 |=3D 1; /* F */ par64 |=3D (fsr & 0x3f) << 1; /* FS */ @@ -6925,7 +6933,7 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx= mmu_idx, return false; } if (get_phys_addr(env, addr, MMU_INST_FETCH, mmu_idx, - &physaddr, &attrs, &prot, &page_size, &fsr, &fi)) { + &physaddr, &attrs, &prot, &page_size, &fsr, &fi, NUL= L)) { /* the MPU lookup failed */ env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_IACCVIOL_MASK; armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, env->v7m.secur= e); @@ -8207,7 +8215,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMM= MUIdx mmu_idx, int ret; =20 ret =3D get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_S2NS, &s2pa, - &txattrs, &s2prot, &s2size, fsr, fi); + &txattrs, &s2prot, &s2size, fsr, fi, NULL= ); if (ret) { fi->s2addr =3D addr; fi->stage2 =3D true; @@ -8608,11 +8616,41 @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is= _aa64, int level, return true; } =20 +/* Translate from the 4-bit stage 2 representation of + * memory attributes (without cache-allocation hints) to + * the 8-bit representation of the stage 1 MAIR registers + * (which includes allocation hints). + * + * ref: shared/translation/attrs/S2AttrDecode() + * .../S2ConvertAttrsHints() + */ +static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs) +{ + uint8_t hiattr =3D extract32(s2attrs, 2, 2); + uint8_t loattr =3D extract32(s2attrs, 0, 2); + uint8_t hihint =3D 0, lohint =3D 0; + + if (hiattr !=3D 0) { /* normal memory */ + if ((env->cp15.hcr_el2 & HCR_CD) !=3D 0) { /* cache disabled */ + hiattr =3D loattr =3D 1; /* non-cacheable */ + } else { + if (hiattr !=3D 1) { /* Write-through or write-back */ + hihint =3D 3; /* RW allocate */ + } + if (loattr !=3D 1) { /* Write-through or write-back */ + lohint =3D 3; /* RW allocate */ + } + } + } + + return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint; +} + static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_id= x, hwaddr *phys_ptr, MemTxAttrs *txattrs, int = *prot, target_ulong *page_size_ptr, uint32_t *fsr, - ARMMMUFaultInfo *fi) + ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheat= trs) { ARMCPU *cpu =3D arm_env_get_cpu(env); CPUState *cs =3D CPU(cpu); @@ -8929,6 +8967,21 @@ static bool get_phys_addr_lpae(CPUARMState *env, tar= get_ulong address, */ txattrs->secure =3D false; } + + if (cacheattrs !=3D NULL) { + if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { + cacheattrs->attrs =3D convert_stage2_attrs(env, + extract32(attrs, 0, 4= )); + } else { + /* Index into MAIR registers for cache attributes */ + uint8_t attrindx =3D extract32(attrs, 0, 3); + uint64_t mair =3D env->cp15.mair_el[regime_el(env, mmu_idx)]; + assert(attrindx <=3D 7); + cacheattrs->attrs =3D extract64(mair, attrindx * 8, 8); + } + cacheattrs->shareability =3D extract32(attrs, 6, 2); + } + *phys_ptr =3D descaddr; *page_size_ptr =3D page_size; return false; @@ -9490,6 +9543,93 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, u= int32_t address, return false; } =20 +/* Combine either inner or outer cacheability attributes for normal + * memory, according to table D4-42 and pseudocode procedure + * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM). + * + * NB: only stage 1 includes allocation hints (RW bits), leading to + * some asymmetry. + */ +static uint8_t combine_cacheattr_nibble(uint8_t s1, uint8_t s2) +{ + if (s1 =3D=3D 4 || s2 =3D=3D 4) { + /* non-cacheable has precedence */ + return 4; + } else if (extract32(s1, 2, 2) =3D=3D 0 || extract32(s1, 2, 2) =3D=3D = 2) { + /* stage 1 write-through takes precedence */ + return s1; + } else if (extract32(s2, 2, 2) =3D=3D 2) { + /* stage 2 write-through takes precedence, but the allocation hint + * is still taken from stage 1 + */ + return (2 << 2) | extract32(s1, 0, 2); + } else { /* write-back */ + return s1; + } +} + +/* Combine S1 and S2 cacheability/shareability attributes, per D4.5.4 + * and CombineS1S2Desc() + * + * @s1: Attributes from stage 1 walk + * @s2: Attributes from stage 2 walk + */ +static ARMCacheAttrs combine_cacheattrs(ARMCacheAttrs s1, ARMCacheAttrs s2) +{ + uint8_t s1lo =3D extract32(s1.attrs, 0, 4), s2lo =3D extract32(s2.attr= s, 0, 4); + uint8_t s1hi =3D extract32(s1.attrs, 4, 4), s2hi =3D extract32(s2.attr= s, 4, 4); + ARMCacheAttrs ret; + + /* Combine shareability attributes (table D4-43) */ + if (s1.shareability =3D=3D 2 || s2.shareability =3D=3D 2) { + /* if either are outer-shareable, the result is outer-shareable */ + ret.shareability =3D 2; + } else if (s1.shareability =3D=3D 3 || s2.shareability =3D=3D 3) { + /* if either are inner-shareable, the result is inner-shareable */ + ret.shareability =3D 3; + } else { + /* both non-shareable */ + ret.shareability =3D 0; + } + + /* Combine memory type and cacheability attributes */ + if (s1hi =3D=3D 0 || s2hi =3D=3D 0) { + /* Device has precedence over normal */ + if (s1lo =3D=3D 0 || s2lo =3D=3D 0) { + /* nGnRnE has precedence over anything */ + ret.attrs =3D 0; + } else if (s1lo =3D=3D 4 || s2lo =3D=3D 4) { + /* non-Reordering has precedence over Reordering */ + ret.attrs =3D 4; /* nGnRE */ + } else if (s1lo =3D=3D 8 || s2lo =3D=3D 8) { + /* non-Gathering has precedence over Gathering */ + ret.attrs =3D 8; /* nGRE */ + } else { + ret.attrs =3D 0xc; /* GRE */ + } + + /* Any location for which the resultant memory type is any + * type of Device memory is always treated as Outer Shareable. + */ + ret.shareability =3D 2; + } else { /* Normal memory */ + /* Outer/inner cacheability combine independently */ + ret.attrs =3D combine_cacheattr_nibble(s1hi, s2hi) << 4 + | combine_cacheattr_nibble(s1lo, s2lo); + + if (ret.attrs =3D=3D 0x44) { + /* Any location for which the resultant memory type is Normal + * Inner Non-cacheable, Outer Non-cacheable is always treated + * as Outer Shareable. + */ + ret.shareability =3D 2; + } + } + + return ret; +} + + /* get_phys_addr - get the physical address for this virtual address * * Find the physical address corresponding to the given virtual address, @@ -9514,12 +9654,14 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, = uint32_t address, * @prot: set to the permissions for the page containing phys_ptr * @page_size: set to the size of the page containing phys_ptr * @fsr: set to the DFSR/IFSR value on failure + * @fi: set to fault info if the translation fails + * @cacheattrs: (if non-NULL) set to the cacheability/shareability attribu= tes */ static bool get_phys_addr(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, target_ulong *page_size, uint32_t *fsr, - ARMMMUFaultInfo *fi) + ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) { if (mmu_idx =3D=3D ARMMMUIdx_S12NSE0 || mmu_idx =3D=3D ARMMMUIdx_S12NS= E1) { /* Call ourselves recursively to do the stage 1 and then stage 2 @@ -9529,10 +9671,11 @@ static bool get_phys_addr(CPUARMState *env, target_= ulong address, hwaddr ipa; int s2_prot; int ret; + ARMCacheAttrs cacheattrs2 =3D {}; =20 ret =3D get_phys_addr(env, address, access_type, stage_1_mmu_idx(mmu_idx), &ipa, attrs, - prot, page_size, fsr, fi); + prot, page_size, fsr, fi, cacheattrs); =20 /* If S1 fails or S2 is disabled, return early. */ if (ret || regime_translation_disabled(env, ARMMMUIdx_S2NS)) { @@ -9543,10 +9686,17 @@ static bool get_phys_addr(CPUARMState *env, target_= ulong address, /* S1 is done. Now do S2 translation. */ ret =3D get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_S2= NS, phys_ptr, attrs, &s2_prot, - page_size, fsr, fi); + page_size, fsr, fi, + cacheattrs !=3D NULL ? &cacheattrs2 := NULL); fi->s2addr =3D ipa; /* Combine the S1 and S2 perms. */ *prot &=3D s2_prot; + + /* Combine the S1 and S2 cache attributes, if needed */ + if (!ret && cacheattrs !=3D NULL) { + *cacheattrs =3D combine_cacheattrs(*cacheattrs, cacheattrs= 2); + } + return ret; } else { /* @@ -9617,7 +9767,7 @@ static bool get_phys_addr(CPUARMState *env, target_ul= ong address, =20 if (regime_using_lpae_format(env, mmu_idx)) { return get_phys_addr_lpae(env, address, access_type, mmu_idx, phys= _ptr, - attrs, prot, page_size, fsr, fi); + attrs, prot, page_size, fsr, fi, cacheat= trs); } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { return get_phys_addr_v6(env, address, access_type, mmu_idx, phys_p= tr, attrs, prot, page_size, fsr, fi); @@ -9645,7 +9795,7 @@ bool arm_tlb_fill(CPUState *cs, vaddr address, =20 ret =3D get_phys_addr(env, address, access_type, core_to_arm_mmu_idx(env, mmu_idx), &phys_addr, - &attrs, &prot, &page_size, fsr, fi); + &attrs, &prot, &page_size, fsr, fi, NULL); if (!ret) { /* Map a single [sub]page. */ phys_addr &=3D TARGET_PAGE_MASK; @@ -9674,7 +9824,7 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs= , vaddr addr, *attrs =3D (MemTxAttrs) {}; =20 ret =3D get_phys_addr(env, addr, 0, mmu_idx, &phys_addr, - attrs, &prot, &page_size, &fsr, &fi); + attrs, &prot, &page_size, &fsr, &fi, NULL); =20 if (ret) { return -1; --=20 2.7.4 From nobody Tue May 7 11:56:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1510062037444895.4067039413414; Tue, 7 Nov 2017 05:40:37 -0800 (PST) Received: from localhost ([::1]:53490 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eC47A-0001bf-KX for importer@patchew.org; Tue, 07 Nov 2017 08:40:28 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36800) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eC41m-0006Wh-9r for qemu-devel@nongnu.org; Tue, 07 Nov 2017 08:34:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eC41l-0005y7-Iz for qemu-devel@nongnu.org; Tue, 07 Nov 2017 08:34:54 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:38240) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eC41l-0005vT-D6 for qemu-devel@nongnu.org; Tue, 07 Nov 2017 08:34:53 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eC41h-0004Sg-J6 for qemu-devel@nongnu.org; Tue, 07 Nov 2017 13:34:49 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 7 Nov 2017 13:35:17 +0000 Message-Id: <1510061722-14092-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1510061722-14092-1-git-send-email-peter.maydell@linaro.org> References: <1510061722-14092-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 2/7] hw/arm: Mark the "fsl, imx6" device with user_creatable = false X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Thomas Huth This device causes QEMU to abort if the user tries to instantiate it: $ qemu-system-aarch64 -M sabrelite -smp 1,maxcpus=3D2 -device fsl,,imx6 Unexpected error in qemu_chr_fe_init() at chardev/char-fe.c:222: qemu-system-aarch64: -device fsl,,imx6: Device 'serial0' is in use Aborted (core dumped) The device uses serial_hds[] directly in its realize function, so it can not be instantiated again by the user. Signed-off-by: Thomas Huth Message-id: 1509519537-6964-2-git-send-email-thuth@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/fsl-imx6.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c index 26fd214..59ef33e 100644 --- a/hw/arm/fsl-imx6.c +++ b/hw/arm/fsl-imx6.c @@ -440,8 +440,9 @@ static void fsl_imx6_class_init(ObjectClass *oc, void *= data) DeviceClass *dc =3D DEVICE_CLASS(oc); =20 dc->realize =3D fsl_imx6_realize; - dc->desc =3D "i.MX6 SOC"; + /* Reason: Uses serial_hds[] in the realize() function */ + dc->user_creatable =3D false; } =20 static const TypeInfo fsl_imx6_type_info =3D { --=20 2.7.4 From nobody Tue May 7 11:56:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1510062113059807.4852794179684; Tue, 7 Nov 2017 05:41:53 -0800 (PST) Received: from localhost ([::1]:53506 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eC48U-0002fn-98 for importer@patchew.org; Tue, 07 Nov 2017 08:41:50 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36860) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eC41r-0006ac-0O for qemu-devel@nongnu.org; Tue, 07 Nov 2017 08:35:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eC41l-0005xc-B0 for qemu-devel@nongnu.org; Tue, 07 Nov 2017 08:34:58 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:38238) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eC41l-0005rx-4E for qemu-devel@nongnu.org; Tue, 07 Nov 2017 08:34:53 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eC41i-0004TU-6d for qemu-devel@nongnu.org; Tue, 07 Nov 2017 13:34:50 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 7 Nov 2017 13:35:18 +0000 Message-Id: <1510061722-14092-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1510061722-14092-1-git-send-email-peter.maydell@linaro.org> References: <1510061722-14092-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 3/7] hw/arm: Mark the "fsl, imx25" device with user_creatable = false X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Thomas Huth QEMU currently crashes when the user tries to instantiate the fsl,imx25 device manually: $ aarch64-softmmu/qemu-system-aarch64 -S -M imx25-pdk -device fsl,,imx25 ** ERROR:/home/thuth/devel/qemu/tcg/tcg.c:538:tcg_register_thread: assertion failed: (n < max_cpus) The imx25-pdk board (which is the one that uses this CPU type) only supports one CPU, and the realize function of the "fsl,imx25" device also uses serial_hds[] directly, so this device clearly can not be instantiated twice and thus we should mark it with user_creatable =3D 0. Signed-off-by: Thomas Huth Message-id: 1509519537-6964-3-git-send-email-thuth@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/fsl-imx25.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c index 3b97ece..cb988a6 100644 --- a/hw/arm/fsl-imx25.c +++ b/hw/arm/fsl-imx25.c @@ -288,8 +288,12 @@ static void fsl_imx25_class_init(ObjectClass *oc, void= *data) DeviceClass *dc =3D DEVICE_CLASS(oc); =20 dc->realize =3D fsl_imx25_realize; - dc->desc =3D "i.MX25 SOC"; + /* + * Reason: uses serial_hds in realize and the imx25 board does not + * support multiple CPUs + */ + dc->user_creatable =3D false; } =20 static const TypeInfo fsl_imx25_type_info =3D { --=20 2.7.4 From nobody Tue May 7 11:56:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1510061813907804.4604063736339; Tue, 7 Nov 2017 05:36:53 -0800 (PST) Received: from localhost ([::1]:53470 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eC43U-0007Qj-CX for importer@patchew.org; Tue, 07 Nov 2017 08:36:40 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36776) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eC41l-0006Vq-A3 for qemu-devel@nongnu.org; Tue, 07 Nov 2017 08:34:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eC41k-0005wK-FX for qemu-devel@nongnu.org; Tue, 07 Nov 2017 08:34:53 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:38238) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eC41k-0005rx-7f for qemu-devel@nongnu.org; Tue, 07 Nov 2017 08:34:52 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eC41i-0004Tv-PH for qemu-devel@nongnu.org; Tue, 07 Nov 2017 13:34:50 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 7 Nov 2017 13:35:19 +0000 Message-Id: <1510061722-14092-5-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1510061722-14092-1-git-send-email-peter.maydell@linaro.org> References: <1510061722-14092-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 4/7] hw/arm: Mark the "fsl, imx31" device with user_creatable = false X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Thomas Huth QEMU currently crashes when the user tries to instantiate the fsl,imx31 device manually: $ aarch64-softmmu/qemu-system-aarch64 -M kzm -device fsl,,imx31 ** ERROR:/home/thuth/devel/qemu/tcg/tcg.c:538:tcg_register_thread: assertion failed: (n < max_cpus) Aborted (core dumped) The kzm board (which is the one that uses this CPU type) only supports one CPU, and the realize function of the "fsl,imx31" device also uses serial_hds[] directly, so this device clearly can not be instantiated twice and thus we should mark it with user_creatable =3D false. Signed-off-by: Thomas Huth Message-id: 1509519537-6964-4-git-send-email-thuth@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/fsl-imx31.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/arm/fsl-imx31.c b/hw/arm/fsl-imx31.c index 0f2ebe8..3eee83d 100644 --- a/hw/arm/fsl-imx31.c +++ b/hw/arm/fsl-imx31.c @@ -260,8 +260,12 @@ static void fsl_imx31_class_init(ObjectClass *oc, void= *data) DeviceClass *dc =3D DEVICE_CLASS(oc); =20 dc->realize =3D fsl_imx31_realize; - dc->desc =3D "i.MX31 SOC"; + /* + * Reason: uses serial_hds in realize and the kzm board does not + * support multiple CPUs + */ + dc->user_creatable =3D false; } =20 static const TypeInfo fsl_imx31_type_info =3D { --=20 2.7.4 From nobody Tue May 7 11:56:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1510061814004498.1440696649711; Tue, 7 Nov 2017 05:36:54 -0800 (PST) Received: from localhost ([::1]:53471 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eC43U-0007RE-32 for importer@patchew.org; Tue, 07 Nov 2017 08:36:40 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36788) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eC41l-0006Vr-Qz for qemu-devel@nongnu.org; Tue, 07 Nov 2017 08:34:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eC41k-0005wZ-N7 for qemu-devel@nongnu.org; Tue, 07 Nov 2017 08:34:53 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:38240) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eC41k-0005vT-FF for qemu-devel@nongnu.org; Tue, 07 Nov 2017 08:34:52 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eC41j-0004UP-F3 for qemu-devel@nongnu.org; Tue, 07 Nov 2017 13:34:51 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 7 Nov 2017 13:35:20 +0000 Message-Id: <1510061722-14092-6-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1510061722-14092-1-git-send-email-peter.maydell@linaro.org> References: <1510061722-14092-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 5/7] translate.c: Fix usermode big-endian AArch32 LDREXD and STREXD X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For AArch32 LDREXD and STREXD, architecturally the 32-bit word at the lowest address is always Rt and the one at addr+4 is Rt2, even if the CPU is big-endian. Our implementation does these with a single 64-bit store, so if we're big-endian then we need to put the two 32-bit halves together in the opposite order to little-endian, so that they end up in the right places. We were trying to do this with the gen_aa32_frob64() function, but that is not correct for the usermode emulator, because there there is a distinction between "load a 64 bit value" (which does a BE 64-bit access and doesn't need swapping) and "load two 32 bit values as one 64 bit access" (where we still need to do the swapping, like system mode BE32). Fixes: https://bugs.launchpad.net/qemu/+bug/1725267 Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 1509622400-13351-1-git-send-email-peter.maydell@linaro.org --- target/arm/translate.c | 39 ++++++++++++++++++++++++++++++++++----- 1 file changed, 34 insertions(+), 5 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index df57dbb..4afb0c8 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7903,9 +7903,27 @@ static void gen_load_exclusive(DisasContext *s, int = rt, int rt2, TCGv_i32 tmp2 =3D tcg_temp_new_i32(); TCGv_i64 t64 =3D tcg_temp_new_i64(); =20 - gen_aa32_ld_i64(s, t64, addr, get_mem_index(s), opc); + /* For AArch32, architecturally the 32-bit word at the lowest + * address is always Rt and the one at addr+4 is Rt2, even if + * the CPU is big-endian. That means we don't want to do a + * gen_aa32_ld_i64(), which invokes gen_aa32_frob64() as if + * for an architecturally 64-bit access, but instead do a + * 64-bit access using MO_BE if appropriate and then split + * the two halves. + * This only makes a difference for BE32 user-mode, where + * frob64() must not flip the two halves of the 64-bit data + * but this code must treat BE32 user-mode like BE32 system. + */ + TCGv taddr =3D gen_aa32_addr(s, addr, opc); + + tcg_gen_qemu_ld_i64(t64, taddr, get_mem_index(s), opc); + tcg_temp_free(taddr); tcg_gen_mov_i64(cpu_exclusive_val, t64); - tcg_gen_extr_i64_i32(tmp, tmp2, t64); + if (s->be_data =3D=3D MO_BE) { + tcg_gen_extr_i64_i32(tmp2, tmp, t64); + } else { + tcg_gen_extr_i64_i32(tmp, tmp2, t64); + } tcg_temp_free_i64(t64); =20 store_reg(s, rt2, tmp2); @@ -7954,15 +7972,26 @@ static void gen_store_exclusive(DisasContext *s, in= t rd, int rt, int rt2, TCGv_i64 n64 =3D tcg_temp_new_i64(); =20 t2 =3D load_reg(s, rt2); - tcg_gen_concat_i32_i64(n64, t1, t2); + /* For AArch32, architecturally the 32-bit word at the lowest + * address is always Rt and the one at addr+4 is Rt2, even if + * the CPU is big-endian. Since we're going to treat this as a + * single 64-bit BE store, we need to put the two halves in the + * opposite order for BE to LE, so that they end up in the right + * places. + * We don't want gen_aa32_frob64() because that does the wrong + * thing for BE32 usermode. + */ + if (s->be_data =3D=3D MO_BE) { + tcg_gen_concat_i32_i64(n64, t2, t1); + } else { + tcg_gen_concat_i32_i64(n64, t1, t2); + } tcg_temp_free_i32(t2); - gen_aa32_frob64(s, n64); =20 tcg_gen_atomic_cmpxchg_i64(o64, taddr, cpu_exclusive_val, n64, get_mem_index(s), opc); tcg_temp_free_i64(n64); =20 - gen_aa32_frob64(s, o64); tcg_gen_setcond_i64(TCG_COND_NE, o64, o64, cpu_exclusive_val); tcg_gen_extrl_i64_i32(t0, o64); =20 --=20 2.7.4 From nobody Tue May 7 11:56:28 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1510061830856714.1775562565599; Tue, 7 Nov 2017 05:37:10 -0800 (PST) Received: from localhost ([::1]:53472 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eC43f-0007ZP-TC for importer@patchew.org; Tue, 07 Nov 2017 08:36:51 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36828) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eC41n-0006XK-Cr for qemu-devel@nongnu.org; Tue, 07 Nov 2017 08:35:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eC41m-0005zG-7z for qemu-devel@nongnu.org; Tue, 07 Nov 2017 08:34:55 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:38242) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eC41m-0005xq-1Q for qemu-devel@nongnu.org; Tue, 07 Nov 2017 08:34:54 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eC41l-0004Uq-2o for qemu-devel@nongnu.org; Tue, 07 Nov 2017 13:34:53 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 7 Nov 2017 13:35:21 +0000 Message-Id: <1510061722-14092-7-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1510061722-14092-1-git-send-email-peter.maydell@linaro.org> References: <1510061722-14092-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 6/7] hw/intc/arm_gicv3_its: Fix the VM termination in vm_change_state_handler() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Shanker Donthineni The commit cddafd8f353d ("hw/intc/arm_gicv3_its: Implement state save /restore") breaks the backward compatibility with the older kernels where vITS save/restore support is not available. The vmstate function vm_change_state_handler() should not be registered if the running kernel doesn't support ITS save/restore feature. Otherwise VM instance will be killed whenever vmstate callback function is invoked. Observed a virtual machine shutdown with QEMU-2.10+linux-4.11 when testing the reboot command "virsh reboot --mode acpi" instead of reboot. KVM Error: 'KVM_SET_DEVICE_ATTR failed: Group 4 attr 0x00000000000001' Signed-off-by: Shanker Donthineni Reviewed-by: Eric Auger Message-id: 1509712671-16299-1-git-send-email-shankerd@codeaurora.org Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_its_kvm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c index 39903d5..9b00ce5 100644 --- a/hw/intc/arm_gicv3_its_kvm.c +++ b/hw/intc/arm_gicv3_its_kvm.c @@ -111,13 +111,13 @@ static void kvm_arm_its_realize(DeviceState *dev, Err= or **errp) error_free(s->migration_blocker); return; } + } else { + qemu_add_vm_change_state_handler(vm_change_state_handler, s); } =20 kvm_msi_use_devid =3D true; kvm_gsi_direct_mapping =3D false; kvm_msi_via_irqfd_allowed =3D kvm_irqfds_enabled(); - - qemu_add_vm_change_state_handler(vm_change_state_handler, s); } =20 /** --=20 2.7.4 From nobody Tue May 7 11:56:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1510062035443828.9978044288182; Tue, 7 Nov 2017 05:40:35 -0800 (PST) Received: from localhost ([::1]:53492 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eC47B-0001cB-Kz for importer@patchew.org; Tue, 07 Nov 2017 08:40:29 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36867) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eC41r-0006av-DJ for qemu-devel@nongnu.org; Tue, 07 Nov 2017 08:35:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eC41n-00060c-3Y for qemu-devel@nongnu.org; Tue, 07 Nov 2017 08:34:59 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:38242) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eC41m-0005xq-T1 for qemu-devel@nongnu.org; Tue, 07 Nov 2017 08:34:55 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eC41l-0004VK-Mu for qemu-devel@nongnu.org; Tue, 07 Nov 2017 13:34:53 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 7 Nov 2017 13:35:22 +0000 Message-Id: <1510061722-14092-8-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1510061722-14092-1-git-send-email-peter.maydell@linaro.org> References: <1510061722-14092-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 7/7] hw/intc/arm_gicv3_its: Don't abort on table save failure X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Eric Auger The ITS is not fully properly reset at the moment. Caches are not emptied. After a reset, in case we attempt to save the state before the bound devices have registered their MSIs and after the 1st level table has been allocated by the ITS driver (device BASER is valid), the first level entries are still invalid. If the device cache is not empty (devices registered before the reset), vgic_its_save_device_tables fails with -EINVAL. This causes a QEMU abort(). Cc: qemu-stable@nongnu.org Signed-off-by: Eric Auger Reported-by: wanghaibin Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_its_kvm.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c index 9b00ce5..6fb45df 100644 --- a/hw/intc/arm_gicv3_its_kvm.c +++ b/hw/intc/arm_gicv3_its_kvm.c @@ -64,20 +64,16 @@ static void vm_change_state_handler(void *opaque, int r= unning, { GICv3ITSState *s =3D (GICv3ITSState *)opaque; Error *err =3D NULL; - int ret; =20 if (running) { return; } =20 - ret =3D kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, - KVM_DEV_ARM_ITS_SAVE_TABLES, NULL, true, &err); + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, + KVM_DEV_ARM_ITS_SAVE_TABLES, NULL, true, &err); if (err) { error_report_err(err); } - if (ret < 0 && ret !=3D -EFAULT) { - abort(); - } } =20 static void kvm_arm_its_realize(DeviceState *dev, Error **errp) --=20 2.7.4