From nobody Thu May 2 15:13:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1509930144818416.53278215956846; Sun, 5 Nov 2017 17:02:24 -0800 (PST) Received: from localhost ([::1]:46108 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eBVnd-0004tn-Pk for importer@patchew.org; Sun, 05 Nov 2017 20:02:01 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33585) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eBVmn-0004Jh-0D for qemu-devel@nongnu.org; Sun, 05 Nov 2017 20:01:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eBVmj-00023i-U7 for qemu-devel@nongnu.org; Sun, 05 Nov 2017 20:01:09 -0500 Received: from mxhk.zte.com.cn ([63.217.80.70]:37236) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eBVmj-0001ym-CW for qemu-devel@nongnu.org; Sun, 05 Nov 2017 20:01:05 -0500 Received: from mse01.zte.com.cn (unknown [10.30.3.20]) by Forcepoint Email with ESMTPS id 8968BE9F27FE12B6B51D; Mon, 6 Nov 2017 09:00:55 +0800 (CST) Received: from notes_smtp.zte.com.cn ([10.30.1.239]) by mse01.zte.com.cn with ESMTP id vA610cb5052866; Mon, 6 Nov 2017 09:00:38 +0800 (GMT-8) (envelope-from jiang.biao2@zte.com.cn) Received: from localhost.localdomain ([10.75.10.200]) by szsmtp06.zte.com.cn (Lotus Domino Release 8.5.3FP6) with ESMTP id 2017110609003631-606682 ; Mon, 6 Nov 2017 09:00:36 +0800 From: Jiang Biao To: aurelien@aurel32.net, rth@twiddle.net Date: Mon, 6 Nov 2017 08:57:17 +0800 Message-Id: <1509929837-178178-1-git-send-email-jiang.biao2@zte.com.cn> X-Mailer: git-send-email 1.8.3.1 X-MIMETrack: Itemize by SMTP Server on SZSMTP06/server/zte_ltd(Release 8.5.3FP6|November 21, 2013) at 2017-11-06 09:00:36, Serialize by Router on notes_smtp/zte_ltd(Release 9.0.1FP7|August 17, 2016) at 2017-11-06 09:00:38, Serialize complete at 2017-11-06 09:00:38 X-MAIL: mse01.zte.com.cn vA610cb5052866 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 63.217.80.70 Subject: [Qemu-devel] [PATCH] tcg/mips: remove inline keywords. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jiang.biao2@zte.com.cn, zhong.weidong@zte.com.cn, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The compiler will make reasonable default choies for inline functions, so the inline keywords are redundant. Remove them to retain consistant code style. Signed-off-by: Jiang Biao Suggested-by: Richard Henderson Acked-by: Aurelien Jarno --- tcg/mips/tcg-target.inc.c | 52 +++++++++++++++++++++++--------------------= ---- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c index 4b55ab8..77afadc 100644 --- a/tcg/mips/tcg-target.inc.c +++ b/tcg/mips/tcg-target.inc.c @@ -144,7 +144,7 @@ static tcg_insn_unit *bswap32_addr; static tcg_insn_unit *bswap32u_addr; static tcg_insn_unit *bswap64_addr; =20 -static inline uint32_t reloc_pc16_val(tcg_insn_unit *pc, tcg_insn_unit *ta= rget) +static uint32_t reloc_pc16_val(tcg_insn_unit *pc, tcg_insn_unit *target) { /* Let the compiler perform the right-shift as part of the arithmetic.= */ ptrdiff_t disp =3D target - (pc + 1); @@ -152,18 +152,18 @@ static inline uint32_t reloc_pc16_val(tcg_insn_unit *= pc, tcg_insn_unit *target) return disp & 0xffff; } =20 -static inline void reloc_pc16(tcg_insn_unit *pc, tcg_insn_unit *target) +static void reloc_pc16(tcg_insn_unit *pc, tcg_insn_unit *target) { *pc =3D deposit32(*pc, 0, 16, reloc_pc16_val(pc, target)); } =20 -static inline uint32_t reloc_26_val(tcg_insn_unit *pc, tcg_insn_unit *targ= et) +static uint32_t reloc_26_val(tcg_insn_unit *pc, tcg_insn_unit *target) { tcg_debug_assert((((uintptr_t)pc ^ (uintptr_t)target) & 0xf0000000) = =3D=3D 0); return ((uintptr_t)target >> 2) & 0x3ffffff; } =20 -static inline void reloc_26(tcg_insn_unit *pc, tcg_insn_unit *target) +static void reloc_26(tcg_insn_unit *pc, tcg_insn_unit *target) { *pc =3D deposit32(*pc, 0, 26, reloc_26_val(pc, target)); } @@ -183,7 +183,7 @@ static void patch_reloc(tcg_insn_unit *code_ptr, int ty= pe, #define TCG_CT_CONST_N16 0x1000 /* "Negatable" 16-bit: -32767 - 32767 */ #define TCG_CT_CONST_WSZ 0x2000 /* word size */ =20 -static inline bool is_p2m1(tcg_target_long val) +static bool is_p2m1(tcg_target_long val) { return val && ((val + 1) & val) =3D=3D 0; } @@ -248,7 +248,7 @@ static const char *target_parse_constraint(TCGArgConstr= aint *ct, } =20 /* test if a constant matches the constraint */ -static inline int tcg_target_const_match(tcg_target_long val, TCGType type, +static int tcg_target_const_match(tcg_target_long val, TCGType type, const TCGArgConstraint *arg_ct) { int ct; @@ -419,7 +419,7 @@ typedef enum { /* * Type reg */ -static inline void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc, +static void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc, TCGReg rd, TCGReg rs, TCGReg rt) { int32_t inst; @@ -434,7 +434,7 @@ static inline void tcg_out_opc_reg(TCGContext *s, MIPSI= nsn opc, /* * Type immediate */ -static inline void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc, +static void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc, TCGReg rt, TCGReg rs, TCGArg imm) { int32_t inst; @@ -449,7 +449,7 @@ static inline void tcg_out_opc_imm(TCGContext *s, MIPSI= nsn opc, /* * Type bitfield */ -static inline void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt, +static void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt, TCGReg rs, int msb, int lsb) { int32_t inst; @@ -462,7 +462,7 @@ static inline void tcg_out_opc_bf(TCGContext *s, MIPSIn= sn opc, TCGReg rt, tcg_out32(s, inst); } =20 -static inline void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn = opm, +static void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm, MIPSInsn oph, TCGReg rt, TCGReg rs, int msb, int lsb) { @@ -480,7 +480,7 @@ static inline void tcg_out_opc_bf64(TCGContext *s, MIPS= Insn opc, MIPSInsn opm, /* * Type branch */ -static inline void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, +static void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, TCGReg rt, TCGReg rs) { /* We pay attention here to not modify the branch target by reading @@ -494,7 +494,7 @@ static inline void tcg_out_opc_br(TCGContext *s, MIPSIn= sn opc, /* * Type sa */ -static inline void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc, +static void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc, TCGReg rd, TCGReg rt, TCGArg sa) { int32_t inst; @@ -542,27 +542,27 @@ static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn o= pc, void *target) return true; } =20 -static inline void tcg_out_nop(TCGContext *s) +static void tcg_out_nop(TCGContext *s) { tcg_out32(s, 0); } =20 -static inline void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGAr= g sa) +static void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) { tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa); } =20 -static inline void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGAr= g sa) +static void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) { tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa); } =20 -static inline void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGAr= g sa) +static void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) { tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa); } =20 -static inline void tcg_out_mov(TCGContext *s, TCGType type, +static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) { /* Simple reg-reg move, optimising out the 'do nothing' case */ @@ -602,7 +602,7 @@ static void tcg_out_movi(TCGContext *s, TCGType type, } } =20 -static inline void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg) +static void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg) { if (use_mips32r2_instructions) { tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); @@ -619,7 +619,7 @@ static inline void tcg_out_bswap16(TCGContext *s, TCGRe= g ret, TCGReg arg) } } =20 -static inline void tcg_out_bswap16s(TCGContext *s, TCGReg ret, TCGReg arg) +static void tcg_out_bswap16s(TCGContext *s, TCGReg ret, TCGReg arg) { if (use_mips32r2_instructions) { tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); @@ -683,7 +683,7 @@ static void tcg_out_bswap64(TCGContext *s, TCGReg ret, = TCGReg arg) } } =20 -static inline void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg) +static void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg) { if (use_mips32r2_instructions) { tcg_out_opc_reg(s, OPC_SEB, ret, 0, arg); @@ -693,7 +693,7 @@ static inline void tcg_out_ext8s(TCGContext *s, TCGReg = ret, TCGReg arg) } } =20 -static inline void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg) +static void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg) { if (use_mips32r2_instructions) { tcg_out_opc_reg(s, OPC_SEH, ret, 0, arg); @@ -703,7 +703,7 @@ static inline void tcg_out_ext16s(TCGContext *s, TCGReg= ret, TCGReg arg) } } =20 -static inline void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) +static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) { if (use_mips32r2_instructions) { tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0); @@ -727,7 +727,7 @@ static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, T= CGReg data, tcg_out_opc_imm(s, opc, data, addr, lo); } =20 -static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, +static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1, intptr_t arg2) { MIPSInsn opc =3D OPC_LD; @@ -737,7 +737,7 @@ static inline void tcg_out_ld(TCGContext *s, TCGType ty= pe, TCGReg arg, tcg_out_ldst(s, opc, arg, arg1, arg2); } =20 -static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, +static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1, intptr_t arg2) { MIPSInsn opc =3D OPC_SD; @@ -747,7 +747,7 @@ static inline void tcg_out_st(TCGContext *s, TCGType ty= pe, TCGReg arg, tcg_out_ldst(s, opc, arg, arg1, arg2); } =20 -static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, +static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, TCGReg base, intptr_t ofs) { if (val =3D=3D 0) { @@ -1704,7 +1704,7 @@ static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2= , MIPSInsn opcv6, } } =20 -static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, +static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, const int *const_args) { MIPSInsn i1, i2; --=20 2.9.5