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[2001:470:27:1fa::2]) by smtp.gmail.com with ESMTPSA id h3sm1258383lfj.26.2017.11.03.20.45.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 03 Nov 2017 20:45:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8yl5bDzCucA3oLL34EtF7JXf0Cv7eilzTPfch1rFpvo=; b=O20ENc70nx5VlYH6AVxp8gAY2MJUyT052O0nMKaClsMMYA16W4xIvKl19RPcCqfM7H KrgniN1xi2cAj/XWlQmwQ1pEuZYf8Ebl9oCn0lTGssHC51cpNA59S1k23u2v264tvvOy GuD+sgg540hrQqJQ72LiMUTBz/IkHCpK3/sv0SyXxe0PC6ffa/3kGpYwgt7sj69gXFie BdMFlbbKazu6+JYoXyTdHokORm4draXcp8kRSCB6Z9OCGAAd3522bFvBCFNtCcWKf6Ym 0bD2yxGBQe2IpfEXCaqKMadeQUna1FYGdvV92LkLRozveBmgC4GP/EgWRtEgQAhjxUO7 cTsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8yl5bDzCucA3oLL34EtF7JXf0Cv7eilzTPfch1rFpvo=; b=QZnI0h/Ql3GjM5hJn+t8wFzPYLchhXXXSermq8VUSCqL5yUqpaysR0dJ1VDKd7FEQX g3VeJeld4qlXj9n1aswQsMq7jTw5Ov2ryBpdOzZlCocb6Ls2tQsQnHt6O1T6t7qhhadI k01Wmw5ssTrA69HUhYCDPKEOpDoOv7Grl+lhFjZr3n10eYcFCx1fdJt/pJIywOoaM4oV BMKip5fvos6Piz8MQ9vJ6ZeRUxzTZtJ+9na6Q9jpM/wr5D66xTazJ4Boe19W0xlAXBJw 2g9lP6BCWImvpYGO+vpfa5e0Elz8DlU/DDi8FA8sq+JfBb1u3i57NZLYFtiC9jjn4E5q fd2Q== X-Gm-Message-State: AMCzsaUZEcMOMtoEJqVLT5H2i0VX5aixE65qvNaI86qLZIB9otO4e8Bb Q08fxqib+Az2ON7jLRuc0e8b5A== X-Google-Smtp-Source: ABhQp+Rh+44io++EiiuI5ezQXL/TzT6soGvOOhZF3nY5KsXTVnD1ASe8aaeRTIGKlAGVBYHpglSvjg== X-Received: by 10.46.84.29 with SMTP id i29mr3751360ljb.87.1509767159326; Fri, 03 Nov 2017 20:45:59 -0700 (PDT) From: Max Filippov To: qemu-devel@nongnu.org Date: Fri, 3 Nov 2017 20:45:09 -0700 Message-Id: <1509767121-26925-5-git-send-email-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1509767121-26925-1-git-send-email-jcmvbkbc@gmail.com> References: <1509767121-26925-1-git-send-email-jcmvbkbc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::242 Subject: [Qemu-devel] [PATCH 04/16] target/xtensa: extract FPU2000 opcode translators X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" FPU2000 implements basic single-precision floating point operations and can be replaced with a different implementation, like DFPU or HiFi. Move FPU2000 opcode translators into separate functions and list them in a separate array. Signed-off-by: Max Filippov --- target/xtensa/cpu.h | 1 + target/xtensa/translate.c | 374 ++++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 375 insertions(+) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 8b6fd1ff9695..bd77a68a7aa4 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -349,6 +349,7 @@ typedef struct XtensaOpcodeTranslators { } XtensaOpcodeTranslators; =20 extern const XtensaOpcodeTranslators xtensa_core_opcodes; +extern const XtensaOpcodeTranslators xtensa_fpu2000_opcodes; =20 struct XtensaConfig { const char *name; diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 1c227380a64d..f6a53cdfc28f 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -6433,3 +6433,377 @@ const XtensaOpcodeTranslators xtensa_core_opcodes = =3D { .num_opcodes =3D ARRAY_SIZE(core_ops), .opcode =3D core_ops, }; + + +static void translate_abs_s(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_cpenable(dc, 0)) { + gen_helper_abs_s(cpu_FR[arg[0]], cpu_FR[arg[1]]); + } +} + +static void translate_add_s(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_cpenable(dc, 0)) { + gen_helper_add_s(cpu_FR[arg[0]], cpu_env, + cpu_FR[arg[1]], cpu_FR[arg[2]]); + } +} + +enum { + COMPARE_UN, + COMPARE_OEQ, + COMPARE_UEQ, + COMPARE_OLT, + COMPARE_ULT, + COMPARE_OLE, + COMPARE_ULE, +}; + +static void translate_compare_s(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + static void (* const helper[])(TCGv_env env, TCGv_i32 bit, + TCGv_i32 s, TCGv_i32 t) =3D { + [COMPARE_UN] =3D gen_helper_un_s, + [COMPARE_OEQ] =3D gen_helper_oeq_s, + [COMPARE_UEQ] =3D gen_helper_ueq_s, + [COMPARE_OLT] =3D gen_helper_olt_s, + [COMPARE_ULT] =3D gen_helper_ult_s, + [COMPARE_OLE] =3D gen_helper_ole_s, + [COMPARE_ULE] =3D gen_helper_ule_s, + }; + + if (gen_check_cpenable(dc, 0)) { + TCGv_i32 bit =3D tcg_const_i32(1 << arg[0]); + + helper[par[0]](cpu_env, bit, cpu_FR[arg[1]], cpu_FR[arg[2]]); + tcg_temp_free(bit); + } +} + +static void translate_float_s(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[1]) && gen_check_cpenable(dc, 0)) { + TCGv_i32 scale =3D tcg_const_i32(-arg[2]); + + if (par[0]) { + gen_helper_uitof(cpu_FR[arg[0]], cpu_env, cpu_R[arg[1]], scale= ); + } else { + gen_helper_itof(cpu_FR[arg[0]], cpu_env, cpu_R[arg[1]], scale); + } + tcg_temp_free(scale); + } +} + +static void translate_ftoi_s(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[0]) && gen_check_cpenable(dc, 0)) { + TCGv_i32 rounding_mode =3D tcg_const_i32(par[0]); + TCGv_i32 scale =3D tcg_const_i32(arg[2]); + + if (par[1]) { + gen_helper_ftoui(cpu_R[arg[0]], cpu_FR[arg[1]], + rounding_mode, scale); + } else { + gen_helper_ftoi(cpu_R[arg[0]], cpu_FR[arg[1]], + rounding_mode, scale); + } + tcg_temp_free(rounding_mode); + tcg_temp_free(scale); + } +} + +static void translate_ldsti(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[1]) && gen_check_cpenable(dc, 0)) { + TCGv_i32 addr =3D tcg_temp_new_i32(); + + tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]); + gen_load_store_alignment(dc, 2, addr, false); + if (par[0]) { + tcg_gen_qemu_st32(cpu_FR[arg[0]], addr, dc->cring); + } else { + tcg_gen_qemu_ld32u(cpu_FR[arg[0]], addr, dc->cring); + } + if (par[1]) { + tcg_gen_mov_i32(cpu_R[arg[1]], addr); + } + tcg_temp_free(addr); + } +} + +static void translate_ldstx(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[1], arg[2]) && gen_check_cpenable(dc, 0)= ) { + TCGv_i32 addr =3D tcg_temp_new_i32(); + + tcg_gen_add_i32(addr, cpu_R[arg[1]], cpu_R[arg[2]]); + gen_load_store_alignment(dc, 2, addr, false); + if (par[0]) { + tcg_gen_qemu_st32(cpu_FR[arg[0]], addr, dc->cring); + } else { + tcg_gen_qemu_ld32u(cpu_FR[arg[0]], addr, dc->cring); + } + if (par[1]) { + tcg_gen_mov_i32(cpu_R[arg[1]], addr); + } + tcg_temp_free(addr); + } +} + +static void translate_madd_s(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_cpenable(dc, 0)) { + gen_helper_madd_s(cpu_FR[arg[0]], cpu_env, + cpu_FR[arg[0]], cpu_FR[arg[1]], cpu_FR[arg[2]]); + } +} + +static void translate_mov_s(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_cpenable(dc, 0)) { + tcg_gen_mov_i32(cpu_FR[arg[0]], cpu_FR[arg[1]]); + } +} + +static void translate_movcond_s(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[2]) && gen_check_cpenable(dc, 0)) { + TCGv_i32 zero =3D tcg_const_i32(0); + + tcg_gen_movcond_i32(par[0], cpu_FR[arg[0]], + cpu_R[arg[2]], zero, + cpu_FR[arg[1]], cpu_FR[arg[2]]); + tcg_temp_free(zero); + } +} + +static void translate_movp_s(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_cpenable(dc, 0)) { + TCGv_i32 zero =3D tcg_const_i32(0); + TCGv_i32 tmp =3D tcg_temp_new_i32(); + + tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << arg[2]); + tcg_gen_movcond_i32(par[0], + cpu_FR[arg[0]], tmp, zero, + cpu_FR[arg[1]], cpu_FR[arg[0]]); + tcg_temp_free(tmp); + tcg_temp_free(zero); + } +} + +static void translate_mul_s(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_cpenable(dc, 0)) { + gen_helper_mul_s(cpu_FR[arg[0]], cpu_env, + cpu_FR[arg[1]], cpu_FR[arg[2]]); + } +} + +static void translate_msub_s(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_cpenable(dc, 0)) { + gen_helper_msub_s(cpu_FR[arg[0]], cpu_env, + cpu_FR[arg[0]], cpu_FR[arg[1]], cpu_FR[arg[2]]); + } +} + +static void translate_neg_s(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_cpenable(dc, 0)) { + gen_helper_neg_s(cpu_FR[arg[0]], cpu_FR[arg[1]]); + } +} + +static void translate_rfr_s(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[0]) && + gen_check_cpenable(dc, 0)) { + tcg_gen_mov_i32(cpu_R[arg[0]], cpu_FR[arg[1]]); + } +} + +static void translate_sub_s(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_cpenable(dc, 0)) { + gen_helper_sub_s(cpu_FR[arg[0]], cpu_env, + cpu_FR[arg[1]], cpu_FR[arg[2]]); + } +} + +static void translate_wfr_s(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[1]) && + gen_check_cpenable(dc, 0)) { + tcg_gen_mov_i32(cpu_FR[arg[0]], cpu_R[arg[1]]); + } +} + +static const XtensaOpcodeOps fpu2000_ops[] =3D { + { + .name =3D "abs.s", + .translate =3D translate_abs_s, + }, { + .name =3D "add.s", + .translate =3D translate_add_s, + }, { + .name =3D "ceil.s", + .translate =3D translate_ftoi_s, + .par =3D (const uint32_t[]){float_round_up, false}, + }, { + .name =3D "float.s", + .translate =3D translate_float_s, + .par =3D (const uint32_t[]){false}, + }, { + .name =3D "floor.s", + .translate =3D translate_ftoi_s, + .par =3D (const uint32_t[]){float_round_down, false}, + }, { + .name =3D "lsi", + .translate =3D translate_ldsti, + .par =3D (const uint32_t[]){false, false}, + }, { + .name =3D "lsiu", + .translate =3D translate_ldsti, + .par =3D (const uint32_t[]){false, true}, + }, { + .name =3D "lsx", + .translate =3D translate_ldstx, + .par =3D (const uint32_t[]){false, false}, + }, { + .name =3D "lsxu", + .translate =3D translate_ldstx, + .par =3D (const uint32_t[]){false, true}, + }, { + .name =3D "madd.s", + .translate =3D translate_madd_s, + }, { + .name =3D "mov.s", + .translate =3D translate_mov_s, + }, { + .name =3D "moveqz.s", + .translate =3D translate_movcond_s, + .par =3D (const uint32_t[]){TCG_COND_EQ}, + }, { + .name =3D "movf.s", + .translate =3D translate_movp_s, + .par =3D (const uint32_t[]){TCG_COND_EQ}, + }, { + .name =3D "movgez.s", + .translate =3D translate_movcond_s, + .par =3D (const uint32_t[]){TCG_COND_GE}, + }, { + .name =3D "movltz.s", + .translate =3D translate_movcond_s, + .par =3D (const uint32_t[]){TCG_COND_LT}, + }, { + .name =3D "movnez.s", + .translate =3D translate_movcond_s, + .par =3D (const uint32_t[]){TCG_COND_NE}, + }, { + .name =3D "movt.s", + .translate =3D translate_movp_s, + .par =3D (const uint32_t[]){TCG_COND_NE}, + }, { + .name =3D "msub.s", + .translate =3D translate_msub_s, + }, { + .name =3D "mul.s", + .translate =3D translate_mul_s, + }, { + .name =3D "neg.s", + .translate =3D translate_neg_s, + }, { + .name =3D "oeq.s", + .translate =3D translate_compare_s, + .par =3D (const uint32_t[]){COMPARE_OEQ}, + }, { + .name =3D "ole.s", + .translate =3D translate_compare_s, + .par =3D (const uint32_t[]){COMPARE_OLE}, + }, { + .name =3D "olt.s", + .translate =3D translate_compare_s, + .par =3D (const uint32_t[]){COMPARE_OLT}, + }, { + .name =3D "rfr.s", + .translate =3D translate_rfr_s, + }, { + .name =3D "round.s", + .translate =3D translate_ftoi_s, + .par =3D (const uint32_t[]){float_round_nearest_even, false}, + }, { + .name =3D "ssi", + .translate =3D translate_ldsti, + .par =3D (const uint32_t[]){true, false}, + }, { + .name =3D "ssiu", + .translate =3D translate_ldsti, + .par =3D (const uint32_t[]){true, true}, + }, { + .name =3D "ssx", + .translate =3D translate_ldstx, + .par =3D (const uint32_t[]){true, false}, + }, { + .name =3D "ssxu", + .translate =3D translate_ldstx, + .par =3D (const uint32_t[]){true, true}, + }, { + .name =3D "sub.s", + .translate =3D translate_sub_s, + }, { + .name =3D "trunc.s", + .translate =3D translate_ftoi_s, + .par =3D (const uint32_t[]){float_round_to_zero, false}, + }, { + .name =3D "ueq.s", + .translate =3D translate_compare_s, + .par =3D (const uint32_t[]){COMPARE_UEQ}, + }, { + .name =3D "ufloat.s", + .translate =3D translate_float_s, + .par =3D (const uint32_t[]){true}, + }, { + .name =3D "ule.s", + .translate =3D translate_compare_s, + .par =3D (const uint32_t[]){COMPARE_ULE}, + }, { + .name =3D "ult.s", + .translate =3D translate_compare_s, + .par =3D (const uint32_t[]){COMPARE_ULT}, + }, { + .name =3D "un.s", + .translate =3D translate_compare_s, + .par =3D (const uint32_t[]){COMPARE_UN}, + }, { + .name =3D "utrunc.s", + .translate =3D translate_ftoi_s, + .par =3D (const uint32_t[]){float_round_to_zero, true}, + }, { + .name =3D "wfr.s", + .translate =3D translate_wfr_s, + }, +}; + +const XtensaOpcodeTranslators xtensa_fpu2000_opcodes =3D { + .num_opcodes =3D ARRAY_SIZE(fpu2000_ops), + .opcode =3D fpu2000_ops, +}; --=20 2.1.4